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1 | # |
1 | # |
2 | # Copyright (c) 2006 Martin Decky |
2 | # Copyright (c) 2006 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include "regname.h" |
29 | #include "regname.h" |
30 | - | ||
31 | #define INITIAL_STACK 0x80040000 |
30 | #include "main.h" |
32 | 31 | ||
33 | .set noat |
32 | .set noat |
34 | .set noreorder |
33 | .set noreorder |
35 | .set nomacro |
34 | .set nomacro |
36 | 35 | ||
37 | .section BOOTSTRAP |
36 | .section BOOTSTRAP |
38 | 37 | ||
39 | .global start |
38 | .global start |
40 | start: |
39 | start: |
41 | lui $sp, INITIAL_STACK >> 16 |
- | |
42 | ori $sp, $sp, INITIAL_STACK & 0xffff |
- | |
43 | 40 | ||
- | 41 | /* Setup CPU map (on msim this code |
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- | 42 | is executed in parallel on all CPUs, |
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- | 43 | but it not an issue) */ |
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- | 44 | la $a0, CPUMAP |
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- | 45 | ||
- | 46 | sw $zero, 0($a0) |
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- | 47 | sw $zero, 4($a0) |
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44 | j bootstrap |
48 | sw $zero, 8($a0) |
- | 49 | sw $zero, 12($a0) |
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- | 50 | ||
- | 51 | sw $zero, 16($a0) |
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- | 52 | sw $zero, 20($a0) |
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- | 53 | sw $zero, 24($a0) |
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- | 54 | sw $zero, 28($a0) |
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- | 55 | ||
- | 56 | sw $zero, 32($a0) |
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- | 57 | sw $zero, 36($a0) |
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- | 58 | sw $zero, 40($a0) |
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- | 59 | sw $zero, 44($a0) |
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- | 60 | ||
- | 61 | sw $zero, 48($a0) |
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- | 62 | sw $zero, 52($a0) |
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- | 63 | sw $zero, 56($a0) |
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- | 64 | sw $zero, 60($a0) |
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- | 65 | ||
- | 66 | sw $zero, 64($a0) |
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- | 67 | sw $zero, 68($a0) |
|
- | 68 | sw $zero, 72($a0) |
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- | 69 | sw $zero, 76($a0) |
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- | 70 | ||
- | 71 | sw $zero, 80($a0) |
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- | 72 | sw $zero, 84($a0) |
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- | 73 | sw $zero, 88($a0) |
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- | 74 | sw $zero, 92($a0) |
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- | 75 | ||
- | 76 | sw $zero, 96($a0) |
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- | 77 | sw $zero, 100($a0) |
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- | 78 | sw $zero, 104($a0) |
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- | 79 | sw $zero, 108($a0) |
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- | 80 | ||
- | 81 | sw $zero, 112($a0) |
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- | 82 | sw $zero, 116($a0) |
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- | 83 | sw $zero, 120($a0) |
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- | 84 | sw $zero, 124($a0) |
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- | 85 | ||
- | 86 | lui $a1, 1 |
|
- | 87 | ||
- | 88 | #ifdef MACHINE_msim |
|
- | 89 | ||
- | 90 | /* Read dorder value */ |
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- | 91 | la $k0, MSIM_DORDER_ADDRESS |
|
- | 92 | lw $k1, ($k0) |
|
- | 93 | ||
- | 94 | /* If we are not running on BSP |
|
- | 95 | then end in an infinite loop */ |
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- | 96 | beq $k1, $zero, bsp |
|
45 | nop |
97 | nop |
- | 98 | ||
- | 99 | /* Record CPU presence */ |
|
- | 100 | sll $a2, $k1, 2 |
|
- | 101 | addu $a2, $a2, $a0 |
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- | 102 | sw $a1, ($a2) |
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- | 103 | ||
- | 104 | loop: |
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- | 105 | j loop |
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- | 106 | nop |
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- | 107 | ||
- | 108 | #endif |
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- | 109 | ||
- | 110 | bsp: |
|
- | 111 | /* Record CPU presence */ |
|
- | 112 | sw $a1, ($a0) |
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- | 113 | ||
- | 114 | /* Setup initial stack */ |
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- | 115 | la $sp, INITIAL_STACK |
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- | 116 | ||
- | 117 | j bootstrap |
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- | 118 | nop |
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46 | 119 | ||
47 | 120 | ||
48 |
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121 |
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49 | 122 | ||
50 | 123 | ||
51 | 124 |