WebSVN – HelenOS – Diff – /branches/sparc/kernel/generic/src/ipc/irq.c


/*
 * Copyright (C) 2006 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** IRQ notification framework
 *
 * This framework allows applications to register to receive a notification
 * when interrupt is detected. The application may provide a simple 'top-half'
 * handler as part of its registration, which can perform simple operations
 * (read/write port/memory, add information to notification ipc message).
 *
 * The structure of a notification message is as follows:
 * - METHOD: IPC_M_INTERRUPT
 * - ARG1: interrupt number
 * - ARG2: payload modified by a 'top-half' handler
 * - ARG3: interrupt counter (may be needed to assure correct order
 *         in multithreaded drivers)
 */
 
#include <arch.h>
#include <mm/slab.h>
#include <errno.h>
#include <ipc/ipc.h>
#include <ipc/irq.h>
#include <atomic.h>
#include <syscall/copy.h>
#include <console/console.h>
 
typedef struct {
    SPINLOCK_DECLARE(lock);
    answerbox_t *box;
    irq_code_t *code;
    atomic_t counter;
} ipc_irq_t;
 
 
static ipc_irq_t *irq_conns = NULL;
static int irq_conns_size;
 
#include <print.h>
/* Execute code associated with IRQ notification */
static void code_execute(call_t *call, irq_code_t *code)
{
    int i;
 
    if (!code)
        return;
   
    for (i=0; i < code->cmdcount;i++) {
        switch (code->cmds[i].cmd) {
        case CMD_MEM_READ_1:
            IPC_SET_ARG2(call->data, *((__u8 *)code->cmds[i].addr));
            break;
        case CMD_MEM_READ_2:
            IPC_SET_ARG2(call->data, *((__u16 *)code->cmds[i].addr));
            break;
        case CMD_MEM_READ_4:
            IPC_SET_ARG2(call->data, *((__u32 *)code->cmds[i].addr));
            break;
        case CMD_MEM_READ_8:
            IPC_SET_ARG2(call->data, *((__u64 *)code->cmds[i].addr));
            break;
        case CMD_MEM_WRITE_1:
            *((__u8 *)code->cmds[i].addr) = code->cmds[i].value;
            break;
        case CMD_MEM_WRITE_2:
            *((__u16 *)code->cmds[i].addr) = code->cmds[i].value;
            break;
        case CMD_MEM_WRITE_4:
            *((__u32 *)code->cmds[i].addr) = code->cmds[i].value;
            break;
        case CMD_MEM_WRITE_8:
            *((__u64 *)code->cmds[i].addr) = code->cmds[i].value;
            break;
#if defined(ia32) || defined(amd64)
        case CMD_PORT_READ_1:
            IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));
            break;
        case CMD_PORT_WRITE_1:
            outb((long)code->cmds[i].addr, code->cmds[i].value);
            break;
#endif
#if defined(ia64) 
        case CMD_IA64_GETCHAR:
            IPC_SET_ARG2(call->data, _getc(&ski_uconsole));
            break;
#endif
        default:
            break;
        }
    }
}
 
static void code_free(irq_code_t *code)
{
    if (code) {
        free(code->cmds);
        free(code);
    }
}
 
static irq_code_t * code_from_uspace(irq_code_t *ucode)
{
    irq_code_t *code;
    irq_cmd_t *ucmds;
    int rc;
 
    code = malloc(sizeof(*code), 0);
    rc = copy_from_uspace(code, ucode, sizeof(*code));
    if (rc != 0) {
        free(code);
        return NULL;
    }
   
    if (code->cmdcount > IRQ_MAX_PROG_SIZE) {
        free(code);
        return NULL;
    }
    ucmds = code->cmds;
    code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);
    rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));
    if (rc != 0) {
        free(code->cmds);
        free(code);
        return NULL;
    }
 
    return code;
}
 
/** Unregister task from irq */
void ipc_irq_unregister(answerbox_t *box, int irq)
{
    ipl_t ipl;
 
    ipl = interrupts_disable();
    spinlock_lock(&irq_conns[irq].lock);
    if (irq_conns[irq].box == box) {
        irq_conns[irq].box = NULL;
        code_free(irq_conns[irq].code);
        irq_conns[irq].code = NULL;
    }
 
    spinlock_unlock(&irq_conns[irq].lock);
    interrupts_restore(ipl);
}
 
/** Register an answerbox as a receiving end of interrupts notifications */
int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode)
{
    ipl_t ipl;
    irq_code_t *code;
 
    ASSERT(irq_conns);
 
    if (ucode) {
        code = code_from_uspace(ucode);
        if (!code)
            return EBADMEM;
    } else
        code = NULL;
 
    ipl = interrupts_disable();
    spinlock_lock(&irq_conns[irq].lock);
 
    if (irq_conns[irq].box) {
        spinlock_unlock(&irq_conns[irq].lock);
        interrupts_restore(ipl);
        code_free(code);
        return EEXISTS;
    }
    irq_conns[irq].box = box;
    irq_conns[irq].code = code;
    atomic_set(&irq_conns[irq].counter, 0);
    spinlock_unlock(&irq_conns[irq].lock);
    interrupts_restore(ipl);
 
    return 0;
}
 
/** Notify process that an irq had happend
 *
 * We expect interrupts to be disabled
 */
void ipc_irq_send_notif(int irq)
{
    call_t *call;
 
    ASSERT(irq_conns);
    spinlock_lock(&irq_conns[irq].lock);
 
    if (irq_conns[irq].box) {
        call = ipc_call_alloc(FRAME_ATOMIC);
        if (!call) {
            spinlock_unlock(&irq_conns[irq].lock);
            return;
        }
        call->flags |= IPC_CALL_NOTIF;
        IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
        IPC_SET_ARG1(call->data, irq);
        IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter));
 
        /* Execute code to handle irq */
        code_execute(call, irq_conns[irq].code);
 
        spinlock_lock(&irq_conns[irq].box->irq_lock);
        list_append(&call->link, &irq_conns[irq].box->irq_notifs);
        spinlock_unlock(&irq_conns[irq].box->irq_lock);
 
        waitq_wakeup(&irq_conns[irq].box->wq, 0);
    }
       
    spinlock_unlock(&irq_conns[irq].lock);
}
 
 
/** Initialize table of interrupt handlers */
void ipc_irq_make_table(int irqcount)
{
    int i;
 
    irq_conns_size = irqcount;
    irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0);
    for (i=0; i < irqcount; i++) {
        spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock");
        irq_conns[i].box = NULL;
        irq_conns[i].code = NULL;
    }
}
 
/** Disconnect all irq's notifications
 *
 * TODO: It may be better to do some linked list, so that
 *       we wouldn't need to go through whole array every cleanup
 */
void ipc_irq_cleanup(answerbox_t *box)
{
    int i;
    ipl_t ipl;
   
    for (i=0; i < irq_conns_size; i++) {
        ipl = interrupts_disable();
        spinlock_lock(&irq_conns[i].lock);
        if (irq_conns[i].box == box)
            irq_conns[i].box = NULL;
        spinlock_unlock(&irq_conns[i].lock);
        interrupts_restore(ipl);
    }
}
 

Rev 1573	Rev 1591
1	/*	1	/*
2	* Copyright (C) 2006 Ondrej Palkovsky	2	* Copyright (C) 2006 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** IRQ notification framework	29	/** IRQ notification framework
30	*	30	*
31	* This framework allows applications to register to receive a notification	31	* This framework allows applications to register to receive a notification
32	* when interrupt is detected. The application may provide a simple 'top-half'	32	* when interrupt is detected. The application may provide a simple 'top-half'
33	* handler as part of its registration, which can perform simple operations	33	* handler as part of its registration, which can perform simple operations
34	* (read/write port/memory, add information to notification ipc message).	34	* (read/write port/memory, add information to notification ipc message).
35	*	35	*
36	* The structure of a notification message is as follows:	36	* The structure of a notification message is as follows:
37	* - METHOD: IPC_M_INTERRUPT	37	* - METHOD: IPC_M_INTERRUPT
38	* - ARG1: interrupt number	38	* - ARG1: interrupt number
39	* - ARG2: payload modified by a 'top-half' handler	39	* - ARG2: payload modified by a 'top-half' handler
40	* - ARG3: interrupt counter (may be needed to assure correct order	40	* - ARG3: interrupt counter (may be needed to assure correct order
41	* in multithreaded drivers)	41	* in multithreaded drivers)
42	*/	42	*/
43		43
44	#include <arch.h>	44	#include <arch.h>
45	#include <mm/slab.h>	45	#include <mm/slab.h>
46	#include <errno.h>	46	#include <errno.h>
47	#include <ipc/ipc.h>	47	#include <ipc/ipc.h>
48	#include <ipc/irq.h>	48	#include <ipc/irq.h>
49	#include <atomic.h>	49	#include <atomic.h>
50	#include <syscall/copy.h>	50	#include <syscall/copy.h>
51	#include <console/console.h>	51	#include <console/console.h>
52		52
53	typedef struct {	53	typedef struct {
54	SPINLOCK_DECLARE(lock);	54	SPINLOCK_DECLARE(lock);
55	answerbox_t *box;	55	answerbox_t *box;
56	irq_code_t *code;	56	irq_code_t *code;
57	atomic_t counter;	57	atomic_t counter;
58	} ipc_irq_t;	58	} ipc_irq_t;
59		59
60		60
61	static ipc_irq_t *irq_conns = NULL;	61	static ipc_irq_t *irq_conns = NULL;
62	static int irq_conns_size;	62	static int irq_conns_size;
63		63
64	#include <print.h>	64	#include <print.h>
65	/* Execute code associated with IRQ notification */	65	/* Execute code associated with IRQ notification */
66	static void code_execute(call_t call, irq_code_t code)	66	static void code_execute(call_t call, irq_code_t code)
67	{	67	{
68	int i;	68	int i;
69		69
70	if (!code)	70	if (!code)
71	return;	71	return;
72		72
73	for (i=0; i < code->cmdcount;i++) {	73	for (i=0; i < code->cmdcount;i++) {
74	switch (code->cmds[i].cmd) {	74	switch (code->cmds[i].cmd) {
75	case CMD_MEM_READ_1:	75	case CMD_MEM_READ_1:
76	IPC_SET_ARG2(call->data, ((__u8 )code->cmds[i].addr));	76	IPC_SET_ARG2(call->data, ((__u8 )code->cmds[i].addr));
77	break;	77	break;
78	case CMD_MEM_READ_2:	78	case CMD_MEM_READ_2:
79	IPC_SET_ARG2(call->data, ((__u16 )code->cmds[i].addr));	79	IPC_SET_ARG2(call->data, ((__u16 )code->cmds[i].addr));
80	break;	80	break;
81	case CMD_MEM_READ_4:	81	case CMD_MEM_READ_4:
82	IPC_SET_ARG2(call->data, ((__u32 )code->cmds[i].addr));	82	IPC_SET_ARG2(call->data, ((__u32 )code->cmds[i].addr));
83	break;	83	break;
84	case CMD_MEM_READ_8:	84	case CMD_MEM_READ_8:
85	IPC_SET_ARG2(call->data, ((__u64 )code->cmds[i].addr));	85	IPC_SET_ARG2(call->data, ((__u64 )code->cmds[i].addr));
86	break;	86	break;
87	case CMD_MEM_WRITE_1:	87	case CMD_MEM_WRITE_1:
88	((__u8 )code->cmds[i].addr) = code->cmds[i].value;	88	((__u8 )code->cmds[i].addr) = code->cmds[i].value;
89	break;	89	break;
90	case CMD_MEM_WRITE_2:	90	case CMD_MEM_WRITE_2:
91	((__u16 )code->cmds[i].addr) = code->cmds[i].value;	91	((__u16 )code->cmds[i].addr) = code->cmds[i].value;
92	break;	92	break;
93	case CMD_MEM_WRITE_4:	93	case CMD_MEM_WRITE_4:
94	((__u32 )code->cmds[i].addr) = code->cmds[i].value;	94	((__u32 )code->cmds[i].addr) = code->cmds[i].value;
95	break;	95	break;
96	case CMD_MEM_WRITE_8:	96	case CMD_MEM_WRITE_8:
97	((__u64 )code->cmds[i].addr) = code->cmds[i].value;	97	((__u64 )code->cmds[i].addr) = code->cmds[i].value;
98	break;	98	break;
99	#if defined(ia32) \|\| defined(amd64)	99	#if defined(ia32) \|\| defined(amd64)
100	case CMD_PORT_READ_1:	100	case CMD_PORT_READ_1:
101	IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));	101	IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));
102	break;	102	break;
103	case CMD_PORT_WRITE_1:	103	case CMD_PORT_WRITE_1:
104	outb((long)code->cmds[i].addr, code->cmds[i].value);	104	outb((long)code->cmds[i].addr, code->cmds[i].value);
105	break;	105	break;
106	#endif	106	#endif
107	#if defined(ia64)	107	#if defined(ia64)
108	case CMD_IA64_GETCHAR:	108	case CMD_IA64_GETCHAR:
109	IPC_SET_ARG2(call->data, _getc(&ski_uconsole));	109	IPC_SET_ARG2(call->data, _getc(&ski_uconsole));
110	break;	110	break;
111	#endif	111	#endif
112	default:	112	default:
113	break;	113	break;
114	}	114	}
115	}	115	}
116	}	116	}
117		117
118	static void code_free(irq_code_t *code)	118	static void code_free(irq_code_t *code)
119	{	119	{
120	if (code) {	120	if (code) {
121	free(code->cmds);	121	free(code->cmds);
122	free(code);	122	free(code);
123	}	123	}
124	}	124	}
125		125
126	static irq_code_t * code_from_uspace(irq_code_t *ucode)	126	static irq_code_t * code_from_uspace(irq_code_t *ucode)
127	{	127	{
128	irq_code_t *code;	128	irq_code_t *code;
129	irq_cmd_t *ucmds;	129	irq_cmd_t *ucmds;
130	int rc;	130	int rc;
131		131
132	code = malloc(sizeof(*code), 0);	132	code = malloc(sizeof(*code), 0);
133	rc = copy_from_uspace(code, ucode, sizeof(*code));	133	rc = copy_from_uspace(code, ucode, sizeof(*code));
134	if (rc != 0) {	134	if (rc != 0) {
135	free(code);	135	free(code);
136	return NULL;	136	return NULL;
137	}	137	}
138		138
139	if (code->cmdcount > IRQ_MAX_PROG_SIZE) {	139	if (code->cmdcount > IRQ_MAX_PROG_SIZE) {
140	free(code);	140	free(code);
141	return NULL;	141	return NULL;
142	}	142	}
143	ucmds = code->cmds;	143	ucmds = code->cmds;
144	code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);	144	code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);
145	rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));	145	rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));
146	if (rc != 0) {	146	if (rc != 0) {
147	free(code->cmds);	147	free(code->cmds);
148	free(code);	148	free(code);
149	return NULL;	149	return NULL;
150	}	150	}
151		151
152	return code;	152	return code;
153	}	153	}
154		154
155	/** Unregister task from irq */	155	/** Unregister task from irq */
156	void ipc_irq_unregister(answerbox_t *box, int irq)	156	void ipc_irq_unregister(answerbox_t *box, int irq)
157	{	157	{
158	ipl_t ipl;	158	ipl_t ipl;
159		159
160	ipl = interrupts_disable();	160	ipl = interrupts_disable();
161	spinlock_lock(&irq_conns[irq].lock);	161	spinlock_lock(&irq_conns[irq].lock);
162	if (irq_conns[irq].box == box) {	162	if (irq_conns[irq].box == box) {
163	irq_conns[irq].box = NULL;	163	irq_conns[irq].box = NULL;
164	code_free(irq_conns[irq].code);	164	code_free(irq_conns[irq].code);
165	irq_conns[irq].code = NULL;	165	irq_conns[irq].code = NULL;
166	}	166	}
167		167
168	spinlock_unlock(&irq_conns[irq].lock);	168	spinlock_unlock(&irq_conns[irq].lock);
169	interrupts_restore(ipl);	169	interrupts_restore(ipl);
170	}	170	}
171		171
172	/** Register an answerbox as a receiving end of interrupts notifications */	172	/** Register an answerbox as a receiving end of interrupts notifications */
173	int ipc_irq_register(answerbox_t box, int irq, irq_code_t ucode)	173	int ipc_irq_register(answerbox_t box, int irq, irq_code_t ucode)
174	{	174	{
175	ipl_t ipl;	175	ipl_t ipl;
176	irq_code_t *code;	176	irq_code_t *code;
177		177
178	ASSERT(irq_conns);	178	ASSERT(irq_conns);
179		179
180	if (ucode) {	180	if (ucode) {
181	code = code_from_uspace(ucode);	181	code = code_from_uspace(ucode);
182	if (!code)	182	if (!code)
183	return EBADMEM;	183	return EBADMEM;
184	} else	184	} else
185	code = NULL;	185	code = NULL;
186		186
187	ipl = interrupts_disable();	187	ipl = interrupts_disable();
188	spinlock_lock(&irq_conns[irq].lock);	188	spinlock_lock(&irq_conns[irq].lock);
189		189
190	if (irq_conns[irq].box) {	190	if (irq_conns[irq].box) {
191	spinlock_unlock(&irq_conns[irq].lock);	191	spinlock_unlock(&irq_conns[irq].lock);
192	interrupts_restore(ipl);	192	interrupts_restore(ipl);
193	code_free(code);	193	code_free(code);
194	return EEXISTS;	194	return EEXISTS;
195	}	195	}
196	irq_conns[irq].box = box;	196	irq_conns[irq].box = box;
197	irq_conns[irq].code = code;	197	irq_conns[irq].code = code;
198	atomic_set(&irq_conns[irq].counter, 0);	198	atomic_set(&irq_conns[irq].counter, 0);
199	spinlock_unlock(&irq_conns[irq].lock);	199	spinlock_unlock(&irq_conns[irq].lock);
200	interrupts_restore(ipl);	200	interrupts_restore(ipl);
201		201
202	return 0;	202	return 0;
203	}	203	}
204		204
205	/** Notify process that an irq had happend	205	/** Notify process that an irq had happend
206	*	206	*
207	* We expect interrupts to be disabled	207	* We expect interrupts to be disabled
208	*/	208	*/
209	void ipc_irq_send_notif(int irq)	209	void ipc_irq_send_notif(int irq)
210	{	210	{
211	call_t *call;	211	call_t *call;
212		212
213	ASSERT(irq_conns);	213	ASSERT(irq_conns);
214	spinlock_lock(&irq_conns[irq].lock);	214	spinlock_lock(&irq_conns[irq].lock);
215		215
216	if (irq_conns[irq].box) {	216	if (irq_conns[irq].box) {
217	call = ipc_call_alloc(FRAME_ATOMIC);	217	call = ipc_call_alloc(FRAME_ATOMIC);
-		218	if (!call) {
-		219	spinlock_unlock(&irq_conns[irq].lock);
-		220	return;
-		221	}
218	call->flags \|= IPC_CALL_NOTIF;	222	call->flags \|= IPC_CALL_NOTIF;
219	IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);	223	IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
220	IPC_SET_ARG1(call->data, irq);	224	IPC_SET_ARG1(call->data, irq);
221	IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter));	225	IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter));
222		226
223	/* Execute code to handle irq */	227	/* Execute code to handle irq */
224	code_execute(call, irq_conns[irq].code);	228	code_execute(call, irq_conns[irq].code);
225		229
226	spinlock_lock(&irq_conns[irq].box->irq_lock);	230	spinlock_lock(&irq_conns[irq].box->irq_lock);
227	list_append(&call->link, &irq_conns[irq].box->irq_notifs);	231	list_append(&call->link, &irq_conns[irq].box->irq_notifs);
228	spinlock_unlock(&irq_conns[irq].box->irq_lock);	232	spinlock_unlock(&irq_conns[irq].box->irq_lock);
229		233
230	waitq_wakeup(&irq_conns[irq].box->wq, 0);	234	waitq_wakeup(&irq_conns[irq].box->wq, 0);
231	}	235	}
232		236
233	spinlock_unlock(&irq_conns[irq].lock);	237	spinlock_unlock(&irq_conns[irq].lock);
234	}	238	}
235		239
236		240
237	/** Initialize table of interrupt handlers */	241	/** Initialize table of interrupt handlers */
238	void ipc_irq_make_table(int irqcount)	242	void ipc_irq_make_table(int irqcount)
239	{	243	{
240	int i;	244	int i;
241		245
242	irq_conns_size = irqcount;	246	irq_conns_size = irqcount;
243	irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0);	247	irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0);
244	for (i=0; i < irqcount; i++) {	248	for (i=0; i < irqcount; i++) {
245	spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock");	249	spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock");
246	irq_conns[i].box = NULL;	250	irq_conns[i].box = NULL;
247	irq_conns[i].code = NULL;	251	irq_conns[i].code = NULL;
248	}	252	}
249	}	253	}
250		254
251	/** Disconnect all irq's notifications	255	/** Disconnect all irq's notifications
252	*	256	*
253	* TODO: It may be better to do some linked list, so that	257	* TODO: It may be better to do some linked list, so that
254	* we wouldn't need to go through whole array every cleanup	258	* we wouldn't need to go through whole array every cleanup
255	*/	259	*/
256	void ipc_irq_cleanup(answerbox_t *box)	260	void ipc_irq_cleanup(answerbox_t *box)
257	{	261	{
258	int i;	262	int i;
259	ipl_t ipl;	263	ipl_t ipl;
260		264
261	for (i=0; i < irq_conns_size; i++) {	265	for (i=0; i < irq_conns_size; i++) {
262	ipl = interrupts_disable();	266	ipl = interrupts_disable();
263	spinlock_lock(&irq_conns[i].lock);	267	spinlock_lock(&irq_conns[i].lock);
264	if (irq_conns[i].box == box)	268	if (irq_conns[i].box == box)
265	irq_conns[i].box = NULL;	269	irq_conns[i].box = NULL;
266	spinlock_unlock(&irq_conns[i].lock);	270	spinlock_unlock(&irq_conns[i].lock);
267	interrupts_restore(ipl);	271	interrupts_restore(ipl);
268	}	272	}
269	}	273	}
270		274

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/generic/src/ipc/irq.c @ 3862 – Rev 1573 → 1591