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1 | # |
1 | # |
2 | # Copyright (c) 2005 Jakub Jermar |
2 | # Copyright (c) 2005 Jakub Jermar |
3 | # Copyright (c) 2008 Pavel Rimsky |
3 | # Copyright (c) 2008 Pavel Rimsky |
4 | # All rights reserved. |
4 | # All rights reserved. |
5 | # |
5 | # |
6 | # Redistribution and use in source and binary forms, with or without |
6 | # Redistribution and use in source and binary forms, with or without |
7 | # modification, are permitted provided that the following conditions |
7 | # modification, are permitted provided that the following conditions |
8 | # are met: |
8 | # are met: |
9 | # |
9 | # |
10 | # - Redistributions of source code must retain the above copyright |
10 | # - Redistributions of source code must retain the above copyright |
11 | # notice, this list of conditions and the following disclaimer. |
11 | # notice, this list of conditions and the following disclaimer. |
12 | # - Redistributions in binary form must reproduce the above copyright |
12 | # - Redistributions in binary form must reproduce the above copyright |
13 | # notice, this list of conditions and the following disclaimer in the |
13 | # notice, this list of conditions and the following disclaimer in the |
14 | # documentation and/or other materials provided with the distribution. |
14 | # documentation and/or other materials provided with the distribution. |
15 | # - The name of the author may not be used to endorse or promote products |
15 | # - The name of the author may not be used to endorse or promote products |
16 | # derived from this software without specific prior written permission. |
16 | # derived from this software without specific prior written permission. |
17 | # |
17 | # |
18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | # |
28 | # |
29 | 29 | ||
30 | /** |
30 | /** |
31 | * @file |
31 | * @file |
32 | * @brief This file contains kernel trap table. |
32 | * @brief This file contains kernel trap table. |
33 | */ |
33 | */ |
34 | 34 | ||
35 | .register %g2, #scratch |
35 | .register %g2, #scratch |
36 | .register %g3, #scratch |
36 | .register %g3, #scratch |
37 | 37 | ||
38 | .text |
38 | .text |
39 | 39 | ||
40 | #include <arch/trap/trap_table.h> |
40 | #include <arch/trap/trap_table.h> |
41 | #include <arch/trap/regwin.h> |
41 | #include <arch/trap/regwin.h> |
42 | #include <arch/trap/interrupt.h> |
42 | #include <arch/trap/interrupt.h> |
43 | #include <arch/trap/exception.h> |
43 | #include <arch/trap/exception.h> |
44 | #include <arch/trap/syscall.h> |
44 | #include <arch/trap/syscall.h> |
45 | #include <arch/trap/sun4v/mmu.h> |
45 | #include <arch/trap/sun4v/mmu.h> |
46 | #include <arch/mm/sun4v/mmu.h> |
46 | #include <arch/mm/sun4v/mmu.h> |
47 | #include <arch/mm/page.h> |
47 | #include <arch/mm/page.h> |
48 | #include <arch/stack.h> |
48 | #include <arch/stack.h> |
49 | #include <arch/sun4v/regdef.h> |
49 | #include <arch/sun4v/regdef.h> |
50 | 50 | ||
51 | #define TABLE_SIZE TRAP_TABLE_SIZE |
51 | #define TABLE_SIZE TRAP_TABLE_SIZE |
52 | #define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE |
52 | #define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE |
53 | 53 | ||
54 | /* |
54 | /* |
55 | * Kernel trap table. |
55 | * Kernel trap table. |
56 | */ |
56 | */ |
57 | .align TABLE_SIZE |
57 | .align TABLE_SIZE |
58 | .global trap_table |
58 | .global trap_table |
59 | trap_table: |
59 | trap_table: |
60 | 60 | ||
61 | /* TT = 0x08, TL = 0, instruction_access_exception */ |
61 | /* TT = 0x08, TL = 0, instruction_access_exception */ |
62 | .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE |
62 | .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE |
63 | .global instruction_access_exception_tl0 |
63 | .global instruction_access_exception_tl0 |
64 | instruction_access_exception_tl0: |
64 | instruction_access_exception_tl0: |
65 | /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
65 | /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
66 | PREEMPTIBLE_HANDLER instruction_access_exception*/ |
66 | PREEMPTIBLE_HANDLER instruction_access_exception*/ |
67 | 67 | ||
68 | /* TT = 0x0a, TL = 0, instruction_access_error */ |
68 | /* TT = 0x0a, TL = 0, instruction_access_error */ |
69 | .org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE |
69 | .org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE |
70 | .global instruction_access_error_tl0 |
70 | .global instruction_access_error_tl0 |
71 | instruction_access_error_tl0: |
71 | instruction_access_error_tl0: |
72 | PREEMPTIBLE_HANDLER instruction_access_error |
72 | PREEMPTIBLE_HANDLER instruction_access_error |
73 | 73 | ||
74 | /* TT = 0x10, TL = 0, illegal_instruction */ |
74 | /* TT = 0x10, TL = 0, illegal_instruction */ |
75 | .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE |
75 | .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE |
76 | .global illegal_instruction_tl0 |
76 | .global illegal_instruction_tl0 |
77 | illegal_instruction_tl0: |
77 | illegal_instruction_tl0: |
78 | PREEMPTIBLE_HANDLER illegal_instruction |
78 | PREEMPTIBLE_HANDLER illegal_instruction |
79 | 79 | ||
80 | /* TT = 0x11, TL = 0, privileged_opcode */ |
80 | /* TT = 0x11, TL = 0, privileged_opcode */ |
81 | .org trap_table + TT_PRIVILEGED_OPCODE*ENTRY_SIZE |
81 | .org trap_table + TT_PRIVILEGED_OPCODE*ENTRY_SIZE |
82 | .global privileged_opcode_tl0 |
82 | .global privileged_opcode_tl0 |
83 | privileged_opcode_tl0: |
83 | privileged_opcode_tl0: |
84 | PREEMPTIBLE_HANDLER privileged_opcode |
84 | PREEMPTIBLE_HANDLER privileged_opcode |
85 | 85 | ||
86 | /* TT = 0x12, TL = 0, unimplemented_LDD */ |
86 | /* TT = 0x12, TL = 0, unimplemented_LDD */ |
87 | .org trap_table + TT_UNIMPLEMENTED_LDD*ENTRY_SIZE |
87 | .org trap_table + TT_UNIMPLEMENTED_LDD*ENTRY_SIZE |
88 | .global unimplemented_LDD_tl0 |
88 | .global unimplemented_LDD_tl0 |
89 | unimplemented_LDD_tl0: |
89 | unimplemented_LDD_tl0: |
90 | PREEMPTIBLE_HANDLER unimplemented_LDD |
90 | PREEMPTIBLE_HANDLER unimplemented_LDD |
91 | 91 | ||
92 | /* TT = 0x13, TL = 0, unimplemented_STD */ |
92 | /* TT = 0x13, TL = 0, unimplemented_STD */ |
93 | .org trap_table + TT_UNIMPLEMENTED_STD*ENTRY_SIZE |
93 | .org trap_table + TT_UNIMPLEMENTED_STD*ENTRY_SIZE |
94 | .global unimplemented_STD_tl0 |
94 | .global unimplemented_STD_tl0 |
95 | unimplemented_STD_tl0: |
95 | unimplemented_STD_tl0: |
96 | PREEMPTIBLE_HANDLER unimplemented_STD |
96 | PREEMPTIBLE_HANDLER unimplemented_STD |
97 | 97 | ||
98 | /* TT = 0x20, TL = 0, fb_disabled handler */ |
98 | /* TT = 0x20, TL = 0, fb_disabled handler */ |
99 | .org trap_table + TT_FP_DISABLED*ENTRY_SIZE |
99 | .org trap_table + TT_FP_DISABLED*ENTRY_SIZE |
100 | .global fb_disabled_tl0 |
100 | .global fb_disabled_tl0 |
101 | fp_disabled_tl0: |
101 | fp_disabled_tl0: |
102 | PREEMPTIBLE_HANDLER fp_disabled |
102 | PREEMPTIBLE_HANDLER fp_disabled |
103 | 103 | ||
104 | /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */ |
104 | /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */ |
105 | .org trap_table + TT_FP_EXCEPTION_IEEE_754*ENTRY_SIZE |
105 | .org trap_table + TT_FP_EXCEPTION_IEEE_754*ENTRY_SIZE |
106 | .global fb_exception_ieee_754_tl0 |
106 | .global fb_exception_ieee_754_tl0 |
107 | fp_exception_ieee_754_tl0: |
107 | fp_exception_ieee_754_tl0: |
108 | PREEMPTIBLE_HANDLER fp_exception_ieee_754 |
108 | PREEMPTIBLE_HANDLER fp_exception_ieee_754 |
109 | 109 | ||
110 | /* TT = 0x22, TL = 0, fb_exception_other handler */ |
110 | /* TT = 0x22, TL = 0, fb_exception_other handler */ |
111 | .org trap_table + TT_FP_EXCEPTION_OTHER*ENTRY_SIZE |
111 | .org trap_table + TT_FP_EXCEPTION_OTHER*ENTRY_SIZE |
112 | .global fb_exception_other_tl0 |
112 | .global fb_exception_other_tl0 |
113 | fp_exception_other_tl0: |
113 | fp_exception_other_tl0: |
114 | PREEMPTIBLE_HANDLER fp_exception_other |
114 | PREEMPTIBLE_HANDLER fp_exception_other |
115 | 115 | ||
116 | /* TT = 0x23, TL = 0, tag_overflow */ |
116 | /* TT = 0x23, TL = 0, tag_overflow */ |
117 | .org trap_table + TT_TAG_OVERFLOW*ENTRY_SIZE |
117 | .org trap_table + TT_TAG_OVERFLOW*ENTRY_SIZE |
118 | .global tag_overflow_tl0 |
118 | .global tag_overflow_tl0 |
119 | tag_overflow_tl0: |
119 | tag_overflow_tl0: |
120 | PREEMPTIBLE_HANDLER tag_overflow |
120 | PREEMPTIBLE_HANDLER tag_overflow |
121 | 121 | ||
122 | /* TT = 0x24, TL = 0, clean_window handler */ |
122 | /* TT = 0x24, TL = 0, clean_window handler */ |
123 | .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE |
123 | .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE |
124 | .global clean_window_tl0 |
124 | .global clean_window_tl0 |
125 | clean_window_tl0: |
125 | clean_window_tl0: |
126 | CLEAN_WINDOW_HANDLER |
126 | CLEAN_WINDOW_HANDLER |
127 | 127 | ||
128 | /* TT = 0x28, TL = 0, division_by_zero */ |
128 | /* TT = 0x28, TL = 0, division_by_zero */ |
129 | .org trap_table + TT_DIVISION_BY_ZERO*ENTRY_SIZE |
129 | .org trap_table + TT_DIVISION_BY_ZERO*ENTRY_SIZE |
130 | .global division_by_zero_tl0 |
130 | .global division_by_zero_tl0 |
131 | division_by_zero_tl0: |
131 | division_by_zero_tl0: |
132 | PREEMPTIBLE_HANDLER division_by_zero |
132 | PREEMPTIBLE_HANDLER division_by_zero |
133 | 133 | ||
134 | /* TT = 0x30, TL = 0, data_access_exception */ |
134 | /* TT = 0x30, TL = 0, data_access_exception */ |
135 | .org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE |
135 | .org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE |
136 | .global data_access_exception_tl0 |
136 | .global data_access_exception_tl0 |
137 | data_access_exception_tl0: |
137 | data_access_exception_tl0: |
138 | /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
138 | /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
139 | PREEMPTIBLE_HANDLER data_access_exception*/ |
139 | PREEMPTIBLE_HANDLER data_access_exception*/ |
140 | 140 | ||
141 | /* TT = 0x32, TL = 0, data_access_error */ |
141 | /* TT = 0x32, TL = 0, data_access_error */ |
142 | .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE |
142 | .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE |
143 | .global data_access_error_tl0 |
143 | .global data_access_error_tl0 |
144 | data_access_error_tl0: |
144 | data_access_error_tl0: |
145 | PREEMPTIBLE_HANDLER data_access_error |
145 | PREEMPTIBLE_HANDLER data_access_error |
146 | 146 | ||
147 | /* TT = 0x34, TL = 0, mem_address_not_aligned */ |
147 | /* TT = 0x34, TL = 0, mem_address_not_aligned */ |
148 | .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
148 | .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
149 | .global mem_address_not_aligned_tl0 |
149 | .global mem_address_not_aligned_tl0 |
150 | mem_address_not_aligned_tl0: |
150 | mem_address_not_aligned_tl0: |
151 | PREEMPTIBLE_HANDLER mem_address_not_aligned |
151 | PREEMPTIBLE_HANDLER mem_address_not_aligned |
152 | 152 | ||
153 | /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */ |
153 | /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */ |
154 | .org trap_table + TT_LDDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
154 | .org trap_table + TT_LDDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
155 | .global LDDF_mem_address_not_aligned_tl0 |
155 | .global LDDF_mem_address_not_aligned_tl0 |
156 | LDDF_mem_address_not_aligned_tl0: |
156 | LDDF_mem_address_not_aligned_tl0: |
157 | PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned |
157 | PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned |
158 | 158 | ||
159 | /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */ |
159 | /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */ |
160 | .org trap_table + TT_STDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
160 | .org trap_table + TT_STDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
161 | .global STDF_mem_address_not_aligned_tl0 |
161 | .global STDF_mem_address_not_aligned_tl0 |
162 | STDF_mem_address_not_aligned_tl0: |
162 | STDF_mem_address_not_aligned_tl0: |
163 | PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned |
163 | PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned |
164 | 164 | ||
165 | /* TT = 0x37, TL = 0, privileged_action */ |
165 | /* TT = 0x37, TL = 0, privileged_action */ |
166 | .org trap_table + TT_PRIVILEGED_ACTION*ENTRY_SIZE |
166 | .org trap_table + TT_PRIVILEGED_ACTION*ENTRY_SIZE |
167 | .global privileged_action_tl0 |
167 | .global privileged_action_tl0 |
168 | privileged_action_tl0: |
168 | privileged_action_tl0: |
169 | PREEMPTIBLE_HANDLER privileged_action |
169 | PREEMPTIBLE_HANDLER privileged_action |
170 | 170 | ||
171 | /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */ |
171 | /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */ |
172 | .org trap_table + TT_LDQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
172 | .org trap_table + TT_LDQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
173 | .global LDQF_mem_address_not_aligned_tl0 |
173 | .global LDQF_mem_address_not_aligned_tl0 |
174 | LDQF_mem_address_not_aligned_tl0: |
174 | LDQF_mem_address_not_aligned_tl0: |
175 | PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned |
175 | PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned |
176 | 176 | ||
177 | /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */ |
177 | /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */ |
178 | .org trap_table + TT_STQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
178 | .org trap_table + TT_STQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE |
179 | .global STQF_mem_address_not_aligned_tl0 |
179 | .global STQF_mem_address_not_aligned_tl0 |
180 | STQF_mem_address_not_aligned_tl0: |
180 | STQF_mem_address_not_aligned_tl0: |
181 | PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned |
181 | PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned |
182 | 182 | ||
183 | /* TT = 0x41, TL = 0, interrupt_level_1 handler */ |
183 | /* TT = 0x41, TL = 0, interrupt_level_1 handler */ |
184 | .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE |
184 | .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE |
185 | .global interrupt_level_1_handler_tl0 |
185 | .global interrupt_level_1_handler_tl0 |
186 | interrupt_level_1_handler_tl0: |
186 | interrupt_level_1_handler_tl0: |
187 | INTERRUPT_LEVEL_N_HANDLER 1 |
187 | INTERRUPT_LEVEL_N_HANDLER 1 |
188 | 188 | ||
189 | /* TT = 0x42, TL = 0, interrupt_level_2 handler */ |
189 | /* TT = 0x42, TL = 0, interrupt_level_2 handler */ |
190 | .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE |
190 | .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE |
191 | .global interrupt_level_2_handler_tl0 |
191 | .global interrupt_level_2_handler_tl0 |
192 | interrupt_level_2_handler_tl0: |
192 | interrupt_level_2_handler_tl0: |
193 | INTERRUPT_LEVEL_N_HANDLER 2 |
193 | INTERRUPT_LEVEL_N_HANDLER 2 |
194 | 194 | ||
195 | /* TT = 0x43, TL = 0, interrupt_level_3 handler */ |
195 | /* TT = 0x43, TL = 0, interrupt_level_3 handler */ |
196 | .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE |
196 | .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE |
197 | .global interrupt_level_3_handler_tl0 |
197 | .global interrupt_level_3_handler_tl0 |
198 | interrupt_level_3_handler_tl0: |
198 | interrupt_level_3_handler_tl0: |
199 | INTERRUPT_LEVEL_N_HANDLER 3 |
199 | INTERRUPT_LEVEL_N_HANDLER 3 |
200 | 200 | ||
201 | /* TT = 0x44, TL = 0, interrupt_level_4 handler */ |
201 | /* TT = 0x44, TL = 0, interrupt_level_4 handler */ |
202 | .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE |
202 | .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE |
203 | .global interrupt_level_4_handler_tl0 |
203 | .global interrupt_level_4_handler_tl0 |
204 | interrupt_level_4_handler_tl0: |
204 | interrupt_level_4_handler_tl0: |
205 | INTERRUPT_LEVEL_N_HANDLER 4 |
205 | INTERRUPT_LEVEL_N_HANDLER 4 |
206 | 206 | ||
207 | /* TT = 0x45, TL = 0, interrupt_level_5 handler */ |
207 | /* TT = 0x45, TL = 0, interrupt_level_5 handler */ |
208 | .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE |
208 | .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE |
209 | .global interrupt_level_5_handler_tl0 |
209 | .global interrupt_level_5_handler_tl0 |
210 | interrupt_level_5_handler_tl0: |
210 | interrupt_level_5_handler_tl0: |
211 | INTERRUPT_LEVEL_N_HANDLER 5 |
211 | INTERRUPT_LEVEL_N_HANDLER 5 |
212 | 212 | ||
213 | /* TT = 0x46, TL = 0, interrupt_level_6 handler */ |
213 | /* TT = 0x46, TL = 0, interrupt_level_6 handler */ |
214 | .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE |
214 | .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE |
215 | .global interrupt_level_6_handler_tl0 |
215 | .global interrupt_level_6_handler_tl0 |
216 | interrupt_level_6_handler_tl0: |
216 | interrupt_level_6_handler_tl0: |
217 | INTERRUPT_LEVEL_N_HANDLER 6 |
217 | INTERRUPT_LEVEL_N_HANDLER 6 |
218 | 218 | ||
219 | /* TT = 0x47, TL = 0, interrupt_level_7 handler */ |
219 | /* TT = 0x47, TL = 0, interrupt_level_7 handler */ |
220 | .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE |
220 | .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE |
221 | .global interrupt_level_7_handler_tl0 |
221 | .global interrupt_level_7_handler_tl0 |
222 | interrupt_level_7_handler_tl0: |
222 | interrupt_level_7_handler_tl0: |
223 | INTERRUPT_LEVEL_N_HANDLER 7 |
223 | INTERRUPT_LEVEL_N_HANDLER 7 |
224 | 224 | ||
225 | /* TT = 0x48, TL = 0, interrupt_level_8 handler */ |
225 | /* TT = 0x48, TL = 0, interrupt_level_8 handler */ |
226 | .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE |
226 | .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE |
227 | .global interrupt_level_8_handler_tl0 |
227 | .global interrupt_level_8_handler_tl0 |
228 | interrupt_level_8_handler_tl0: |
228 | interrupt_level_8_handler_tl0: |
229 | INTERRUPT_LEVEL_N_HANDLER 8 |
229 | INTERRUPT_LEVEL_N_HANDLER 8 |
230 | 230 | ||
231 | /* TT = 0x49, TL = 0, interrupt_level_9 handler */ |
231 | /* TT = 0x49, TL = 0, interrupt_level_9 handler */ |
232 | .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE |
232 | .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE |
233 | .global interrupt_level_9_handler_tl0 |
233 | .global interrupt_level_9_handler_tl0 |
234 | interrupt_level_9_handler_tl0: |
234 | interrupt_level_9_handler_tl0: |
235 | INTERRUPT_LEVEL_N_HANDLER 9 |
235 | INTERRUPT_LEVEL_N_HANDLER 9 |
236 | 236 | ||
237 | /* TT = 0x4a, TL = 0, interrupt_level_10 handler */ |
237 | /* TT = 0x4a, TL = 0, interrupt_level_10 handler */ |
238 | .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE |
238 | .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE |
239 | .global interrupt_level_10_handler_tl0 |
239 | .global interrupt_level_10_handler_tl0 |
240 | interrupt_level_10_handler_tl0: |
240 | interrupt_level_10_handler_tl0: |
241 | INTERRUPT_LEVEL_N_HANDLER 10 |
241 | INTERRUPT_LEVEL_N_HANDLER 10 |
242 | 242 | ||
243 | /* TT = 0x4b, TL = 0, interrupt_level_11 handler */ |
243 | /* TT = 0x4b, TL = 0, interrupt_level_11 handler */ |
244 | .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE |
244 | .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE |
245 | .global interrupt_level_11_handler_tl0 |
245 | .global interrupt_level_11_handler_tl0 |
246 | interrupt_level_11_handler_tl0: |
246 | interrupt_level_11_handler_tl0: |
247 | INTERRUPT_LEVEL_N_HANDLER 11 |
247 | INTERRUPT_LEVEL_N_HANDLER 11 |
248 | 248 | ||
249 | /* TT = 0x4c, TL = 0, interrupt_level_12 handler */ |
249 | /* TT = 0x4c, TL = 0, interrupt_level_12 handler */ |
250 | .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE |
250 | .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE |
251 | .global interrupt_level_12_handler_tl0 |
251 | .global interrupt_level_12_handler_tl0 |
252 | interrupt_level_12_handler_tl0: |
252 | interrupt_level_12_handler_tl0: |
253 | INTERRUPT_LEVEL_N_HANDLER 12 |
253 | INTERRUPT_LEVEL_N_HANDLER 12 |
254 | 254 | ||
255 | /* TT = 0x4d, TL = 0, interrupt_level_13 handler */ |
255 | /* TT = 0x4d, TL = 0, interrupt_level_13 handler */ |
256 | .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE |
256 | .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE |
257 | .global interrupt_level_13_handler_tl0 |
257 | .global interrupt_level_13_handler_tl0 |
258 | interrupt_level_13_handler_tl0: |
258 | interrupt_level_13_handler_tl0: |
259 | INTERRUPT_LEVEL_N_HANDLER 13 |
259 | INTERRUPT_LEVEL_N_HANDLER 13 |
260 | 260 | ||
261 | /* TT = 0x4e, TL = 0, interrupt_level_14 handler */ |
261 | /* TT = 0x4e, TL = 0, interrupt_level_14 handler */ |
262 | .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE |
262 | .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE |
263 | .global interrupt_level_14_handler_tl0 |
263 | .global interrupt_level_14_handler_tl0 |
264 | interrupt_level_14_handler_tl0: |
264 | interrupt_level_14_handler_tl0: |
265 | INTERRUPT_LEVEL_N_HANDLER 14 |
265 | INTERRUPT_LEVEL_N_HANDLER 14 |
266 | 266 | ||
267 | /* TT = 0x4f, TL = 0, interrupt_level_15 handler */ |
267 | /* TT = 0x4f, TL = 0, interrupt_level_15 handler */ |
268 | .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE |
268 | .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE |
269 | .global interrupt_level_15_handler_tl0 |
269 | .global interrupt_level_15_handler_tl0 |
270 | interrupt_level_15_handler_tl0: |
270 | interrupt_level_15_handler_tl0: |
271 | INTERRUPT_LEVEL_N_HANDLER 15 |
271 | INTERRUPT_LEVEL_N_HANDLER 15 |
272 | 272 | ||
273 | /* TT = 0x60, TL = 0, interrupt_vector_trap handler */ |
273 | /* TT = 0x60, TL = 0, interrupt_vector_trap handler */ |
274 | .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE |
274 | .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE |
275 | .global interrupt_vector_trap_handler_tl0 |
275 | .global interrupt_vector_trap_handler_tl0 |
276 | interrupt_vector_trap_handler_tl0: |
276 | interrupt_vector_trap_handler_tl0: |
277 | INTERRUPT_VECTOR_TRAP_HANDLER |
277 | INTERRUPT_VECTOR_TRAP_HANDLER |
278 | 278 | ||
279 | /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */ |
279 | /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */ |
280 | .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE |
280 | .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE |
281 | .global fast_instruction_access_mmu_miss_handler_tl0 |
281 | .global fast_instruction_access_mmu_miss_handler_tl0 |
282 | fast_instruction_access_mmu_miss_handler_tl0: |
282 | fast_instruction_access_mmu_miss_handler_tl0: |
283 | /*FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER*/ |
283 | /*FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER*/ |
284 | 284 | ||
285 | /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */ |
285 | /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */ |
286 | .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE |
286 | .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE |
287 | .global fast_data_access_mmu_miss_handler_tl0 |
287 | .global fast_data_access_mmu_miss_handler_tl0 |
288 | fast_data_access_mmu_miss_handler_tl0: |
288 | fast_data_access_mmu_miss_handler_tl0: |
289 | FAST_DATA_ACCESS_MMU_MISS_HANDLER 0 |
289 | FAST_DATA_ACCESS_MMU_MISS_HANDLER 0 |
290 | 290 | ||
291 | /* TT = 0x6c, TL = 0, fast_data_access_protection */ |
291 | /* TT = 0x6c, TL = 0, fast_data_access_protection */ |
292 | .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE |
292 | .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE |
293 | .global fast_data_access_protection_handler_tl0 |
293 | .global fast_data_access_protection_handler_tl0 |
294 | fast_data_access_protection_handler_tl0: |
294 | fast_data_access_protection_handler_tl0: |
295 | /*FAST_DATA_ACCESS_PROTECTION_HANDLER 0*/ |
295 | /*FAST_DATA_ACCESS_PROTECTION_HANDLER 0*/ |
296 | 296 | ||
297 | /* TT = 0x80, TL = 0, spill_0_normal handler */ |
297 | /* TT = 0x80, TL = 0, spill_0_normal handler */ |
298 | .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE |
298 | .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE |
299 | .global spill_0_normal_tl0 |
299 | .global spill_0_normal_tl0 |
300 | spill_0_normal_tl0: |
300 | spill_0_normal_tl0: |
301 | SPILL_NORMAL_HANDLER_KERNEL |
301 | SPILL_NORMAL_HANDLER_KERNEL |
302 | 302 | ||
303 | /* TT = 0x84, TL = 0, spill_1_normal handler */ |
303 | /* TT = 0x84, TL = 0, spill_1_normal handler */ |
304 | .org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE |
304 | .org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE |
305 | .global spill_1_normal_tl0 |
305 | .global spill_1_normal_tl0 |
306 | spill_1_normal_tl0: |
306 | spill_1_normal_tl0: |
307 | SPILL_NORMAL_HANDLER_USERSPACE |
307 | SPILL_NORMAL_HANDLER_USERSPACE |
308 | 308 | ||
309 | /* TT = 0x88, TL = 0, spill_2_normal handler */ |
309 | /* TT = 0x88, TL = 0, spill_2_normal handler */ |
310 | .org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE |
310 | .org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE |
311 | .global spill_2_normal_tl0 |
311 | .global spill_2_normal_tl0 |
312 | spill_2_normal_tl0: |
312 | spill_2_normal_tl0: |
313 | SPILL_TO_USPACE_WINDOW_BUFFER |
313 | SPILL_TO_USPACE_WINDOW_BUFFER |
314 | 314 | ||
315 | /* TT = 0xa0, TL = 0, spill_0_other handler */ |
315 | /* TT = 0xa0, TL = 0, spill_0_other handler */ |
316 | .org trap_table + TT_SPILL_0_OTHER*ENTRY_SIZE |
316 | .org trap_table + TT_SPILL_0_OTHER*ENTRY_SIZE |
317 | .global spill_0_other_tl0 |
317 | .global spill_0_other_tl0 |
318 | spill_0_other_tl0: |
318 | spill_0_other_tl0: |
319 | SPILL_TO_USPACE_WINDOW_BUFFER |
319 | SPILL_TO_USPACE_WINDOW_BUFFER |
320 | 320 | ||
321 | /* TT = 0xc0, TL = 0, fill_0_normal handler */ |
321 | /* TT = 0xc0, TL = 0, fill_0_normal handler */ |
322 | .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE |
322 | .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE |
323 | .global fill_0_normal_tl0 |
323 | .global fill_0_normal_tl0 |
324 | fill_0_normal_tl0: |
324 | fill_0_normal_tl0: |
325 | FILL_NORMAL_HANDLER_KERNEL |
325 | FILL_NORMAL_HANDLER_KERNEL |
326 | 326 | ||
327 | /* TT = 0xc4, TL = 0, fill_1_normal handler */ |
327 | /* TT = 0xc4, TL = 0, fill_1_normal handler */ |
328 | .org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE |
328 | .org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE |
329 | .global fill_1_normal_tl0 |
329 | .global fill_1_normal_tl0 |
330 | fill_1_normal_tl0: |
330 | fill_1_normal_tl0: |
331 | FILL_NORMAL_HANDLER_USERSPACE |
331 | FILL_NORMAL_HANDLER_USERSPACE |
332 | 332 | ||
333 | /* TT = 0x100 - 0x17f, TL = 0, trap_instruction_0 - trap_instruction_7f */ |
333 | /* TT = 0x100 - 0x17f, TL = 0, trap_instruction_0 - trap_instruction_7f */ |
334 | .irp cur, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\ |
334 | .irp cur, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\ |
335 | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\ |
335 | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\ |
336 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\ |
336 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\ |
337 | 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,\ |
337 | 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,\ |
338 | 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,\ |
338 | 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,\ |
339 | 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\ |
339 | 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\ |
340 | 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,\ |
340 | 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,\ |
341 | 127 |
341 | 127 |
342 | .org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE |
342 | .org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE |
343 | .global trap_instruction_\cur\()_tl0 |
343 | .global trap_instruction_\cur\()_tl0 |
344 | trap_instruction_\cur\()_tl0: |
344 | trap_instruction_\cur\()_tl0: |
345 | ba trap_instruction_handler |
345 | ba trap_instruction_handler |
346 | mov \cur, %g2 |
346 | mov \cur, %g2 |
347 | .endr |
347 | .endr |
348 | 348 | ||
349 | /* |
349 | /* |
350 | * Handlers for TL>0. |
350 | * Handlers for TL>0. |
351 | */ |
351 | */ |
352 | 352 | ||
353 | /* TT = 0x08, TL > 0, instruction_access_exception */ |
353 | /* TT = 0x08, TL > 0, instruction_access_exception */ |
354 | .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE |
354 | .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE |
355 | .global instruction_access_exception_tl1 |
355 | .global instruction_access_exception_tl1 |
356 | instruction_access_exception_tl1: |
356 | instruction_access_exception_tl1: |
357 | /*wrpr %g0, 1, %tl |
357 | /*wrpr %g0, 1, %tl |
358 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
358 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
359 | PREEMPTIBLE_HANDLER instruction_access_exception*/ |
359 | PREEMPTIBLE_HANDLER instruction_access_exception*/ |
360 | 360 | ||
361 | /* TT = 0x0a, TL > 0, instruction_access_error */ |
361 | /* TT = 0x0a, TL > 0, instruction_access_error */ |
362 | .org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE |
362 | .org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE |
363 | .global instruction_access_error_tl1 |
363 | .global instruction_access_error_tl1 |
364 | instruction_access_error_tl1: |
364 | instruction_access_error_tl1: |
365 | wrpr %g0, 1, %tl |
365 | wrpr %g0, 1, %tl |
366 | PREEMPTIBLE_HANDLER instruction_access_error |
366 | PREEMPTIBLE_HANDLER instruction_access_error |
367 | 367 | ||
368 | /* TT = 0x10, TL > 0, illegal_instruction */ |
368 | /* TT = 0x10, TL > 0, illegal_instruction */ |
369 | .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE |
369 | .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE |
370 | .global illegal_instruction_tl1 |
370 | .global illegal_instruction_tl1 |
371 | illegal_instruction_tl1: |
371 | illegal_instruction_tl1: |
372 | wrpr %g0, 1, %tl |
372 | wrpr %g0, 1, %tl |
373 | PREEMPTIBLE_HANDLER illegal_instruction |
373 | PREEMPTIBLE_HANDLER illegal_instruction |
374 | 374 | ||
375 | /* TT = 0x24, TL > 0, clean_window handler */ |
375 | /* TT = 0x24, TL > 0, clean_window handler */ |
376 | .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE |
376 | .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE |
377 | .global clean_window_tl1 |
377 | .global clean_window_tl1 |
378 | clean_window_tl1: |
378 | clean_window_tl1: |
379 | CLEAN_WINDOW_HANDLER |
379 | CLEAN_WINDOW_HANDLER |
380 | 380 | ||
381 | /* TT = 0x28, TL > 0, division_by_zero */ |
381 | /* TT = 0x28, TL > 0, division_by_zero */ |
382 | .org trap_table + (TT_DIVISION_BY_ZERO+512)*ENTRY_SIZE |
382 | .org trap_table + (TT_DIVISION_BY_ZERO+512)*ENTRY_SIZE |
383 | .global division_by_zero_tl1 |
383 | .global division_by_zero_tl1 |
384 | division_by_zero_tl1: |
384 | division_by_zero_tl1: |
385 | wrpr %g0, 1, %tl |
385 | wrpr %g0, 1, %tl |
386 | PREEMPTIBLE_HANDLER division_by_zero |
386 | PREEMPTIBLE_HANDLER division_by_zero |
387 | 387 | ||
388 | /* TT = 0x30, TL > 0, data_access_exception */ |
388 | /* TT = 0x30, TL > 0, data_access_exception */ |
389 | .org trap_table + (TT_DATA_ACCESS_EXCEPTION+512)*ENTRY_SIZE |
389 | .org trap_table + (TT_DATA_ACCESS_EXCEPTION+512)*ENTRY_SIZE |
390 | .global data_access_exception_tl1 |
390 | .global data_access_exception_tl1 |
391 | data_access_exception_tl1: |
391 | data_access_exception_tl1: |
392 | /*wrpr %g0, 1, %tl |
392 | /*wrpr %g0, 1, %tl |
393 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
393 | wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
394 | PREEMPTIBLE_HANDLER data_access_exception*/ |
394 | PREEMPTIBLE_HANDLER data_access_exception*/ |
395 | 395 | ||
396 | /* TT = 0x32, TL > 0, data_access_error */ |
396 | /* TT = 0x32, TL > 0, data_access_error */ |
397 | .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE |
397 | .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE |
398 | .global data_access_error_tl1 |
398 | .global data_access_error_tl1 |
399 | data_access_error_tl1: |
399 | data_access_error_tl1: |
400 | wrpr %g0, 1, %tl |
400 | wrpr %g0, 1, %tl |
401 | PREEMPTIBLE_HANDLER data_access_error |
401 | PREEMPTIBLE_HANDLER data_access_error |
402 | 402 | ||
403 | /* TT = 0x34, TL > 0, mem_address_not_aligned */ |
403 | /* TT = 0x34, TL > 0, mem_address_not_aligned */ |
404 | .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE |
404 | .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE |
405 | .global mem_address_not_aligned_tl1 |
405 | .global mem_address_not_aligned_tl1 |
406 | mem_address_not_aligned_tl1: |
406 | mem_address_not_aligned_tl1: |
407 | wrpr %g0, 1, %tl |
407 | wrpr %g0, 1, %tl |
408 | PREEMPTIBLE_HANDLER mem_address_not_aligned |
408 | PREEMPTIBLE_HANDLER mem_address_not_aligned |
409 | 409 | ||
410 | /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */ |
410 | /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */ |
411 | .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
411 | .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
412 | .global fast_data_access_mmu_miss_handler_tl1 |
412 | .global fast_data_access_mmu_miss_handler_tl1 |
413 | fast_data_access_mmu_miss_handler_tl1: |
413 | fast_data_access_mmu_miss_handler_tl1: |
414 | FAST_DATA_ACCESS_MMU_MISS_HANDLER 1 |
414 | FAST_DATA_ACCESS_MMU_MISS_HANDLER 1 |
415 | 415 | ||
416 | /* TT = 0x6c, TL > 0, fast_data_access_protection */ |
416 | /* TT = 0x6c, TL > 0, fast_data_access_protection */ |
417 | .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE |
417 | .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE |
418 | .global fast_data_access_protection_handler_tl1 |
418 | .global fast_data_access_protection_handler_tl1 |
419 | fast_data_access_protection_handler_tl1: |
419 | fast_data_access_protection_handler_tl1: |
420 | /*FAST_DATA_ACCESS_PROTECTION_HANDLER 1*/ |
420 | /*FAST_DATA_ACCESS_PROTECTION_HANDLER 1*/ |
421 | 421 | ||
422 | /* TT = 0x80, TL > 0, spill_0_normal handler */ |
422 | /* TT = 0x80, TL > 0, spill_0_normal handler */ |
423 | .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE |
423 | .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE |
424 | .global spill_0_normal_tl1 |
424 | .global spill_0_normal_tl1 |
425 | spill_0_normal_tl1: |
425 | spill_0_normal_tl1: |
426 | SPILL_NORMAL_HANDLER_KERNEL |
426 | SPILL_NORMAL_HANDLER_KERNEL |
427 | 427 | ||
428 | /* TT = 0x88, TL > 0, spill_2_normal handler */ |
428 | /* TT = 0x88, TL > 0, spill_2_normal handler */ |
429 | .org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE |
429 | .org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE |
430 | .global spill_2_normal_tl1 |
430 | .global spill_2_normal_tl1 |
431 | spill_2_normal_tl1: |
431 | spill_2_normal_tl1: |
432 | SPILL_TO_USPACE_WINDOW_BUFFER |
432 | SPILL_TO_USPACE_WINDOW_BUFFER |
433 | 433 | ||
434 | /* TT = 0xa0, TL > 0, spill_0_other handler */ |
434 | /* TT = 0xa0, TL > 0, spill_0_other handler */ |
435 | .org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE |
435 | .org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE |
436 | .global spill_0_other_tl1 |
436 | .global spill_0_other_tl1 |
437 | spill_0_other_tl1: |
437 | spill_0_other_tl1: |
438 | SPILL_TO_USPACE_WINDOW_BUFFER |
438 | SPILL_TO_USPACE_WINDOW_BUFFER |
439 | 439 | ||
440 | /* TT = 0xc0, TL > 0, fill_0_normal handler */ |
440 | /* TT = 0xc0, TL > 0, fill_0_normal handler */ |
441 | .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE |
441 | .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE |
442 | .global fill_0_normal_tl1 |
442 | .global fill_0_normal_tl1 |
443 | fill_0_normal_tl1: |
443 | fill_0_normal_tl1: |
444 | FILL_NORMAL_HANDLER_KERNEL |
444 | FILL_NORMAL_HANDLER_KERNEL |
445 | 445 | ||
446 | .align TABLE_SIZE |
446 | .align TABLE_SIZE |
447 | 447 | ||
448 | 448 | ||
449 | /* |
449 | /* |
450 | * Spills the window at CWP + 2 to the kernel stack. This macro is to be |
450 | * Spills the window at CWP + 2 to the kernel stack. This macro is to be |
451 | * used before doing SAVE when the spill trap is undesirable. |
451 | * used before doing SAVE when the spill trap is undesirable. |
- | 452 | * |
|
- | 453 | * Parameters: |
|
- | 454 | * tmpreg1 global register to be used for scratching purposes |
|
- | 455 | * tmpreg2 global register to be used for scratching purposes |
|
452 | */ |
456 | */ |
453 | .macro INLINE_SPILL |
457 | .macro INLINE_SPILL tmpreg1, tmpreg2 |
454 | ! CWP := CWP + 2 |
458 | ! CWP := CWP + 2 |
455 | rdpr %cwp, %g3 |
459 | rdpr %cwp, \tmpreg2 |
456 | add %g3, 2, %g3 |
460 | add \tmpreg2, 2, \tmpreg1 |
457 | and %g3, NWINDOWS - 1, %g3 ! modulo NWINDOWS |
461 | and \tmpreg1, NWINDOWS - 1, \tmpreg1 ! modulo NWINDOWS |
458 | wrpr %g3, %cwp |
462 | wrpr \tmpreg1, %cwp |
459 | 463 | ||
460 | ! spill to kernel stack |
464 | ! spill to kernel stack |
461 | stx %l0, [%sp + STACK_BIAS + L0_OFFSET] |
465 | stx %l0, [%sp + STACK_BIAS + L0_OFFSET] |
462 | stx %l1, [%sp + STACK_BIAS + L1_OFFSET] |
466 | stx %l1, [%sp + STACK_BIAS + L1_OFFSET] |
463 | stx %l2, [%sp + STACK_BIAS + L2_OFFSET] |
467 | stx %l2, [%sp + STACK_BIAS + L2_OFFSET] |
464 | stx %l3, [%sp + STACK_BIAS + L3_OFFSET] |
468 | stx %l3, [%sp + STACK_BIAS + L3_OFFSET] |
465 | stx %l4, [%sp + STACK_BIAS + L4_OFFSET] |
469 | stx %l4, [%sp + STACK_BIAS + L4_OFFSET] |
466 | stx %l5, [%sp + STACK_BIAS + L5_OFFSET] |
470 | stx %l5, [%sp + STACK_BIAS + L5_OFFSET] |
467 | stx %l6, [%sp + STACK_BIAS + L6_OFFSET] |
471 | stx %l6, [%sp + STACK_BIAS + L6_OFFSET] |
468 | stx %l7, [%sp + STACK_BIAS + L7_OFFSET] |
472 | stx %l7, [%sp + STACK_BIAS + L7_OFFSET] |
469 | stx %i0, [%sp + STACK_BIAS + I0_OFFSET] |
473 | stx %i0, [%sp + STACK_BIAS + I0_OFFSET] |
470 | stx %i1, [%sp + STACK_BIAS + I1_OFFSET] |
474 | stx %i1, [%sp + STACK_BIAS + I1_OFFSET] |
471 | stx %i2, [%sp + STACK_BIAS + I2_OFFSET] |
475 | stx %i2, [%sp + STACK_BIAS + I2_OFFSET] |
472 | stx %i3, [%sp + STACK_BIAS + I3_OFFSET] |
476 | stx %i3, [%sp + STACK_BIAS + I3_OFFSET] |
473 | stx %i4, [%sp + STACK_BIAS + I4_OFFSET] |
477 | stx %i4, [%sp + STACK_BIAS + I4_OFFSET] |
474 | stx %i5, [%sp + STACK_BIAS + I5_OFFSET] |
478 | stx %i5, [%sp + STACK_BIAS + I5_OFFSET] |
475 | stx %i6, [%sp + STACK_BIAS + I6_OFFSET] |
479 | stx %i6, [%sp + STACK_BIAS + I6_OFFSET] |
476 | stx %i7, [%sp + STACK_BIAS + I7_OFFSET] |
480 | stx %i7, [%sp + STACK_BIAS + I7_OFFSET] |
477 | 481 | ||
478 | ! CWP := CWP - 2 |
482 | ! CWP := CWP - 2 |
479 | add %g3, NWINDOWS - 2, %g3 |
- | |
480 | and %g3, NWINDOWS - 1, %g3 ! modulo NWINDOWS |
- | |
481 | wrpr %g3, %cwp |
483 | wrpr \tmpreg2, %cwp |
482 | 484 | ||
483 | saved |
485 | saved |
484 | .endm |
486 | .endm |
485 | 487 | ||
486 | /* |
488 | /* |
487 | * Fill the window at CWP - 1 from the kernel stack. This macro is to be |
489 | * Fill the window at CWP - 1 from the kernel stack. This macro is to be |
488 | * used before doing RESTORE when the fill trap is undesirable. |
490 | * used before doing RESTORE when the fill trap is undesirable. |
- | 491 | * |
|
- | 492 | * Parameters: |
|
- | 493 | * tmpreg1 global register to be used for scratching purposes |
|
- | 494 | * tmpreg2 global register to be used for scratching purposes |
|
489 | */ |
495 | */ |
490 | .macro INLINE_FILL |
496 | .macro INLINE_FILL tmpreg1, tmpreg2 |
491 | ! CWP := CWP - 1 |
497 | ! CWP := CWP - 1 |
492 | rdpr %cwp, %g3 |
498 | rdpr %cwp, \tmpreg2 |
493 | add %g3, NWINDOWS - 1, %g3 |
499 | add \tmpreg2, NWINDOWS - 1, \tmpreg1 |
494 | and %g3, NWINDOWS - 1, %g3 |
500 | and \tmpreg1, NWINDOWS - 1, \tmpreg1 |
495 | wrpr %g3, %cwp |
501 | wrpr \tmpreg1, %cwp |
496 | 502 | ||
497 | ! fill |
503 | ! fill from kernel stack |
498 | ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 |
504 | ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 |
499 | ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 |
505 | ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 |
500 | ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 |
506 | ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 |
501 | ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 |
507 | ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 |
502 | ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 |
508 | ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 |
503 | ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 |
509 | ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 |
504 | ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 |
510 | ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 |
505 | ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 |
511 | ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 |
506 | ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 |
512 | ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 |
507 | ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 |
513 | ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 |
508 | ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 |
514 | ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 |
509 | ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 |
515 | ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 |
510 | ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 |
516 | ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 |
511 | ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 |
517 | ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 |
512 | ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 |
518 | ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 |
513 | ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 |
519 | ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 |
514 | 520 | ||
515 | ! CWP := CWP + 1 |
521 | ! CWP := CWP + 1 |
516 | add %g3, 1, %g3 |
- | |
517 | and %g3, NWINDOWS - 1, %g3 |
- | |
518 | wrpr %g3, %cwp |
522 | wrpr \tmpreg2, %cwp |
519 | 523 | ||
520 | restored |
524 | restored |
521 | .endm |
525 | .endm |
522 | 526 | ||
523 | /* |
527 | /* |
524 | * Preemptible trap handler for handling traps from kernel. |
528 | * Preemptible trap handler for handling traps from kernel. |
525 | */ |
529 | */ |
526 | .macro PREEMPTIBLE_HANDLER_KERNEL |
530 | .macro PREEMPTIBLE_HANDLER_KERNEL |
527 | 531 | ||
528 | /* |
532 | /* |
529 | * ASSERT(%tl == 1) |
533 | * ASSERT(%tl == 1) |
530 | */ |
534 | */ |
531 | rdpr %tl, %g3 |
535 | rdpr %tl, %g3 |
532 | cmp %g3, 1 |
536 | cmp %g3, 1 |
533 | be 1f |
537 | be 1f |
534 | nop |
538 | nop |
535 | 0: ba 0b ! this is for debugging, if we ever get here |
539 | 0: ba 0b ! this is for debugging, if we ever get here |
536 | nop ! it will be easy to find |
540 | nop ! it will be easy to find |
537 | 541 | ||
538 | /* prevent unnecessary CLEANWIN exceptions */ |
542 | /* prevent unnecessary CLEANWIN exceptions */ |
539 | wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate |
543 | wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate |
540 | 1: |
544 | 1: |
541 | /* |
545 | /* |
542 | * Prevent SAVE instruction from causing a spill exception. If the |
546 | * Prevent SAVE instruction from causing a spill exception. If the |
543 | * CANSAVE register is zero, explicitly spill the current register |
547 | * CANSAVE register is zero, explicitly spill register window |
544 | * window. |
548 | * at CWP + 2. |
545 | */ |
549 | */ |
546 | 550 | ||
547 | rdpr %cansave, %g3 |
551 | rdpr %cansave, %g3 |
548 | brnz %g3, 2f |
552 | brnz %g3, 2f |
549 | nop |
553 | nop |
550 | INLINE_SPILL |
554 | INLINE_SPILL %g3, %g4 |
551 | 555 | ||
552 | 2: |
556 | 2: |
553 | /* ask for new register window */ |
557 | /* ask for new register window */ |
554 | save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp |
558 | save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp |
555 | 559 | ||
556 | /* copy higher level routine's address and its argument */ |
560 | /* copy higher level routine's address and its argument */ |
557 | mov %g1, %l0 |
561 | mov %g1, %l0 |
558 | mov %g2, %o0 |
562 | mov %g2, %o0 |
559 | 563 | ||
560 | /* |
564 | /* |
561 | * Save TSTATE, TPC and TNPC aside. |
565 | * Save TSTATE, TPC and TNPC aside. |
562 | */ |
566 | */ |
563 | rdpr %tstate, %g1 |
567 | rdpr %tstate, %g1 |
564 | rdpr %tpc, %g2 |
568 | rdpr %tpc, %g2 |
565 | rdpr %tnpc, %g3 |
569 | rdpr %tnpc, %g3 |
566 | 570 | ||
567 | stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE] |
571 | stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE] |
568 | stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC] |
572 | stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC] |
569 | stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC] |
573 | stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC] |
570 | 574 | ||
571 | /* |
575 | /* |
572 | * Save the Y register. |
576 | * Save the Y register. |
573 | * This register is deprecated according to SPARC V9 specification |
577 | * This register is deprecated according to SPARC V9 specification |
574 | * and is only present for backward compatibility with previous |
578 | * and is only present for backward compatibility with previous |
575 | * versions of the SPARC architecture. |
579 | * versions of the SPARC architecture. |
576 | * Surprisingly, gcc makes use of this register without a notice. |
580 | * Surprisingly, gcc makes use of this register without a notice. |
577 | */ |
581 | */ |
578 | rd %y, %g4 |
582 | rd %y, %g4 |
579 | stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y] |
583 | stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y] |
580 | 584 | ||
581 | /* switch to TL = 0, explicitly enable FPU */ |
585 | /* switch to TL = 0, explicitly enable FPU */ |
582 | wrpr %g0, 0, %tl |
586 | wrpr %g0, 0, %tl |
- | 587 | wrpr %g0, 0, %gl |
|
583 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate |
588 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate |
584 | 589 | ||
585 | /* g1 -> l1, ..., g7 -> l7 */ |
590 | /* g1 -> l1, ..., g7 -> l7 */ |
586 | SAVE_GLOBALS |
591 | SAVE_GLOBALS |
587 | 592 | ||
588 | /* call higher-level service routine, pass istate as its 2nd parameter */ |
593 | /* call higher-level service routine, pass istate as its 2nd parameter */ |
589 | call %l0 |
594 | call %l0 |
590 | add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1 |
595 | add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1 |
591 | 596 | ||
592 | /* l1 -> g1, ..., l7 -> g7 */ |
597 | /* l1 -> g1, ..., l7 -> g7 */ |
593 | RESTORE_GLOBALS |
598 | RESTORE_GLOBALS |
594 | 599 | ||
595 | /* we must prserve the PEF bit */ |
600 | /* we must prserve the PEF bit */ |
596 | rdpr %pstate, %l1 |
601 | rdpr %pstate, %l1 |
597 | 602 | ||
598 | /* TL := 1, GL := 1 */ |
603 | /* TL := 1, GL := 1 */ |
599 | wrpr %g0, PSTATE_PRIV_BIT, %pstate |
604 | wrpr %g0, PSTATE_PRIV_BIT, %pstate |
600 | wrpr %g0, 1, %tl |
605 | wrpr %g0, 1, %tl |
601 | wrpr %g0, 1, %gl |
606 | wrpr %g0, 1, %gl |
602 | 607 | ||
603 | /* Read TSTATE, TPC and TNPC from saved copy. */ |
608 | /* Read TSTATE, TPC and TNPC from saved copy. */ |
604 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1 |
609 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1 |
605 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2 |
610 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2 |
606 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3 |
611 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3 |
607 | 612 | ||
608 | /* Copy PSTATE.PEF to the in-register copy of TSTATE. */ |
613 | /* Copy PSTATE.PEF to the in-register copy of TSTATE. */ |
609 | and %l1, PSTATE_PEF_BIT, %l1 |
614 | and %l1, PSTATE_PEF_BIT, %l1 |
610 | sllx %l1, TSTATE_PSTATE_SHIFT, %l1 |
615 | sllx %l1, TSTATE_PSTATE_SHIFT, %l1 |
611 | sethi %hi(TSTATE_PEF_BIT), %g4 ! reset the PEF bit to 0 ... |
616 | sethi %hi(TSTATE_PEF_BIT), %g4 ! reset the PEF bit to 0 ... |
612 | andn %g1, %g4, %g1 |
617 | andn %g1, %g4, %g1 |
613 | or %g1, %l1, %g1 ! ... "or" it with saved PEF |
618 | or %g1, %l1, %g1 ! ... "or" it with saved PEF |
614 | 619 | ||
615 | /* Restore TSTATE, TPC and TNPC from saved copies. */ |
620 | /* Restore TSTATE, TPC and TNPC from saved copies. */ |
616 | wrpr %g1, 0, %tstate |
621 | wrpr %g1, 0, %tstate |
617 | wrpr %g2, 0, %tpc |
622 | wrpr %g2, 0, %tpc |
618 | wrpr %g3, 0, %tnpc |
623 | wrpr %g3, 0, %tnpc |
619 | 624 | ||
620 | /* Restore Y. */ |
625 | /* Restore Y. */ |
621 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4 |
626 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4 |
622 | wr %g4, %y |
627 | wr %g4, %y |
623 | 628 | ||
624 | /* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */ |
629 | /* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */ |
625 | and %g1, TSTATE_CWP_MASK, %l0 |
630 | and %g1, TSTATE_CWP_MASK, %l0 |
626 | inc %l0 |
631 | inc %l0 |
627 | and %l0, NWINDOWS - 1, %l0 ! %l0 mod NWINDOWS |
632 | and %l0, NWINDOWS - 1, %l0 ! %l0 mod NWINDOWS |
628 | rdpr %cwp, %l1 |
633 | rdpr %cwp, %l1 |
629 | cmp %l0, %l1 |
634 | cmp %l0, %l1 |
630 | bz 4f ! CWP is ok |
635 | bz 4f ! CWP is ok |
631 | nop |
636 | nop |
632 | 637 | ||
633 | 3: |
638 | 3: |
634 | /* |
639 | /* |
635 | * Fix CWP. |
640 | * Fix CWP. |
636 | * In order to recapitulate, the input registers in the current |
641 | * In order to recapitulate, the input registers in the current |
637 | * window are the output registers of the window to which we want |
642 | * window are the output registers of the window to which we want |
638 | * to restore. Because the fill trap fills only input and local |
643 | * to restore. Because the fill trap fills only input and local |
639 | * registers of a window, we need to preserve those output |
644 | * registers of a window, we need to preserve those output |
640 | * registers manually. |
645 | * registers manually. |
641 | */ |
646 | */ |
642 | mov %sp, %g2 |
647 | mov %sp, %g2 |
643 | stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0] |
648 | stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0] |
644 | stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1] |
649 | stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1] |
645 | stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2] |
650 | stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2] |
646 | stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3] |
651 | stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3] |
647 | stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4] |
652 | stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4] |
648 | stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5] |
653 | stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5] |
649 | stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6] |
654 | stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6] |
650 | stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7] |
655 | stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7] |
651 | wrpr %l0, 0, %cwp |
656 | wrpr %l0, 0, %cwp |
652 | mov %g2, %sp |
657 | mov %g2, %sp |
653 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0 |
658 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0 |
654 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1 |
659 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1 |
655 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2 |
660 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2 |
656 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3 |
661 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3 |
657 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4 |
662 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4 |
658 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5 |
663 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5 |
659 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6 |
664 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6 |
660 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7 |
665 | ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7 |
661 | 666 | ||
662 | 4: |
667 | 4: |
663 | /* |
668 | /* |
664 | * Prevent RESTORE instruction from causing a spill exception. If the |
669 | * Prevent RESTORE instruction from causing a fill exception. If the |
665 | * CANRESTORE register is zero, explicitly spill the current register |
670 | * CANRESTORE register is zero, explicitly fill register window |
666 | * window. |
671 | * at CWP - 1. |
667 | */ |
672 | */ |
668 | rdpr %canrestore, %g1 |
673 | rdpr %canrestore, %g1 |
669 | brnz %g1, 5f |
674 | brnz %g1, 5f |
670 | nop |
675 | nop |
671 | INLINE_FILL |
676 | INLINE_FILL %g3, %g4 |
672 | 677 | ||
673 | 5: |
678 | 5: |
674 | restore |
679 | restore |
675 | 680 | ||
676 | retry |
681 | retry |
677 | .endm |
682 | .endm |
678 | 683 | ||
679 | 684 | ||
680 | #define NOT(x) ((x) == 0) |
685 | #define NOT(x) ((x) == 0) |
681 | 686 | ||
682 | /* Preemptible trap handler for TL=1. |
687 | /* Preemptible trap handler for TL=1. |
683 | * |
688 | * |
684 | * This trap handler makes arrangements to make calling of scheduler() from |
689 | * This trap handler makes arrangements to make calling of scheduler() from |
685 | * within a trap context possible. It is called from several other trap |
690 | * within a trap context possible. It is called from several other trap |
686 | * handlers. |
691 | * handlers. |
687 | */ |
692 | */ |
688 | .macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall |
693 | .macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall |
689 | PREEMPTIBLE_HANDLER_KERNEL |
694 | PREEMPTIBLE_HANDLER_KERNEL |
690 | .endm |
695 | .endm |
691 | 696 | ||
692 | .global preemptible_handler |
697 | .global preemptible_handler |
693 | preemptible_handler: |
698 | preemptible_handler: |
694 | PREEMPTIBLE_HANDLER_TEMPLATE 0 |
699 | PREEMPTIBLE_HANDLER_TEMPLATE 0 |
695 | 700 | ||
696 | .global trap_instruction_handler |
701 | .global trap_instruction_handler |
697 | trap_instruction_handler: |
702 | trap_instruction_handler: |
698 | PREEMPTIBLE_HANDLER_TEMPLATE 1 |
703 | PREEMPTIBLE_HANDLER_TEMPLATE 1 |
699 | 704 |