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1 | # |
1 | # |
2 | # Copyright (c) 2005 Jakub Jermar |
2 | # Copyright (c) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/arch.h> |
29 | #include <arch/arch.h> |
30 | #include <arch/sun4u/arch.h> |
30 | #include <arch/sun4u/arch.h> |
31 | #include <arch/cpu.h> |
31 | #include <arch/sun4u/cpu.h> |
32 | #include <arch/sun4u/regdef.h> |
32 | #include <arch/sun4u/regdef.h> |
33 | #include <arch/boot/boot.h> |
33 | #include <arch/boot/boot.h> |
34 | #include <arch/stack.h> |
34 | #include <arch/stack.h> |
35 | 35 | ||
- | 36 | #include <arch/mm/pagesize.h> |
|
36 | #include <arch/mm/sun4u/mmu.h> |
37 | #include <arch/mm/sun4u/mmu.h> |
37 | #include <arch/mm/tlb.h> |
- | |
38 | #include <arch/mm/sun4u/tlb.h> |
38 | #include <arch/mm/sun4u/tlb.h> |
39 | #include <arch/mm/sun4u/tte.h> |
39 | #include <arch/mm/sun4u/tte.h> |
40 | 40 | ||
41 | #ifdef CONFIG_SMP |
41 | #ifdef CONFIG_SMP |
42 | #include <arch/context_offset.h> |
42 | #include <arch/context_offset.h> |
43 | #endif |
43 | #endif |
44 | 44 | ||
45 | .register %g2, #scratch |
45 | .register %g2, #scratch |
46 | .register %g3, #scratch |
46 | .register %g3, #scratch |
47 | 47 | ||
48 | .section K_TEXT_START, "ax" |
48 | .section K_TEXT_START, "ax" |
49 | 49 | ||
50 | #define BSP_FLAG 1 |
50 | #define BSP_FLAG 1 |
51 | 51 | ||
52 | /* |
52 | /* |
53 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
53 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
54 | * a given processor. |
54 | * a given processor. |
55 | */ |
55 | */ |
56 | #if defined (US) |
56 | #if defined (US) |
57 | #define PHYSMEM_ADDR_SIZE 41 |
57 | #define PHYSMEM_ADDR_SIZE 41 |
58 | #elif defined (US3) |
58 | #elif defined (US3) |
59 | #define PHYSMEM_ADDR_SIZE 43 |
59 | #define PHYSMEM_ADDR_SIZE 43 |
60 | #endif |
60 | #endif |
61 | 61 | ||
62 | /* |
62 | /* |
63 | * Here is where the kernel is passed control from the boot loader. |
63 | * Here is where the kernel is passed control from the boot loader. |
64 | * |
64 | * |
65 | * The registers are expected to be in this state: |
65 | * The registers are expected to be in this state: |
66 | * - %o0 starting address of physical memory + bootstrap processor flag |
66 | * - %o0 starting address of physical memory + bootstrap processor flag |
67 | * bits 63...1: physical memory starting address / 2 |
67 | * bits 63...1: physical memory starting address / 2 |
68 | * bit 0: non-zero on BSP processor, zero on AP processors |
68 | * bit 0: non-zero on BSP processor, zero on AP processors |
69 | * - %o1 bootinfo structure address (BSP only) |
69 | * - %o1 bootinfo structure address (BSP only) |
70 | * - %o2 bootinfo structure size (BSP only) |
70 | * - %o2 bootinfo structure size (BSP only) |
71 | * |
71 | * |
72 | * Moreover, we depend on boot having established the following environment: |
72 | * Moreover, we depend on boot having established the following environment: |
73 | * - TLBs are on |
73 | * - TLBs are on |
74 | * - identity mapping for the kernel image |
74 | * - identity mapping for the kernel image |
75 | */ |
75 | */ |
76 | 76 | ||
77 | .global kernel_image_start |
77 | .global kernel_image_start |
78 | kernel_image_start: |
78 | kernel_image_start: |
79 | mov BSP_FLAG, %l0 |
79 | mov BSP_FLAG, %l0 |
80 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
80 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
81 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
81 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
82 | 82 | ||
83 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
83 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
84 | srlx %l6, 13, %l5 |
84 | srlx %l6, 13, %l5 |
85 | 85 | ||
86 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
86 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
87 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
87 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
88 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
88 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
89 | 89 | ||
90 | /* |
90 | /* |
91 | * Setup basic runtime environment. |
91 | * Setup basic runtime environment. |
92 | */ |
92 | */ |
93 | 93 | ||
94 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
94 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
95 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
95 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
96 | ! never need again |
96 | ! never need again |
97 | wrpr %g0, 0, %otherwin ! make sure the window state is |
97 | wrpr %g0, 0, %otherwin ! make sure the window state is |
98 | ! consistent |
98 | ! consistent |
99 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
99 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
100 | ! traps for kernel |
100 | ! traps for kernel |
101 | 101 | ||
102 | wrpr %g0, 0, %wstate ! use default spill/fill trap |
102 | wrpr %g0, 0, %wstate ! use default spill/fill trap |
103 | 103 | ||
104 | wrpr %g0, 0, %tl ! TL = 0, primary context |
104 | wrpr %g0, 0, %tl ! TL = 0, primary context |
105 | ! register is used |
105 | ! register is used |
106 | 106 | ||
107 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
107 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
108 | ! 32-bit address masking |
108 | ! 32-bit address masking |
109 | 109 | ||
110 | wrpr %g0, 0, %pil ! intialize %pil |
110 | wrpr %g0, 0, %pil ! intialize %pil |
111 | 111 | ||
112 | /* |
112 | /* |
113 | * Switch to kernel trap table. |
113 | * Switch to kernel trap table. |
114 | */ |
114 | */ |
115 | sethi %hi(trap_table), %g1 |
115 | sethi %hi(trap_table), %g1 |
116 | wrpr %g1, %lo(trap_table), %tba |
116 | wrpr %g1, %lo(trap_table), %tba |
117 | 117 | ||
118 | /* |
118 | /* |
119 | * Take over the DMMU by installing locked TTE entry identically |
119 | * Take over the DMMU by installing locked TTE entry identically |
120 | * mapping the first 4M of memory. |
120 | * mapping the first 4M of memory. |
121 | * |
121 | * |
122 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
122 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
123 | * that, the old DTLB contents can be demapped pretty straightforwardly |
123 | * that, the old DTLB contents can be demapped pretty straightforwardly |
124 | * and without causing any traps. |
124 | * and without causing any traps. |
125 | */ |
125 | */ |
126 | 126 | ||
127 | wr %g0, ASI_DMMU, %asi |
127 | wr %g0, ASI_DMMU, %asi |
128 | 128 | ||
129 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
129 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
130 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
130 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
131 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
131 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
132 | 132 | ||
133 | ! demap context 0 |
133 | ! demap context 0 |
134 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
134 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
135 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
135 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
136 | membar #Sync |
136 | membar #Sync |
137 | 137 | ||
138 | #define SET_TLB_TAG(r1, context) \ |
138 | #define SET_TLB_TAG(r1, context) \ |
139 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
139 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
140 | 140 | ||
141 | ! write DTLB tag |
141 | ! write DTLB tag |
142 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
142 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
143 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
143 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
144 | membar #Sync |
144 | membar #Sync |
145 | 145 | ||
146 | #ifdef CONFIG_VIRT_IDX_DCACHE |
146 | #ifdef CONFIG_VIRT_IDX_DCACHE |
147 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
147 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
148 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
148 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
149 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
149 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
150 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
150 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
151 | 151 | ||
152 | #define SET_TLB_DATA(r1, r2, imm) \ |
152 | #define SET_TLB_DATA(r1, r2, imm) \ |
153 | set TTE_LOW_DATA(imm), %r1; \ |
153 | set TTE_LOW_DATA(imm), %r1; \ |
154 | or %r1, %l5, %r1; \ |
154 | or %r1, %l5, %r1; \ |
155 | mov PAGESIZE_4M, %r2; \ |
155 | mov PAGESIZE_4M, %r2; \ |
156 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
156 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
157 | or %r1, %r2, %r1; \ |
157 | or %r1, %r2, %r1; \ |
158 | mov 1, %r2; \ |
158 | mov 1, %r2; \ |
159 | sllx %r2, TTE_V_SHIFT, %r2; \ |
159 | sllx %r2, TTE_V_SHIFT, %r2; \ |
160 | or %r1, %r2, %r1; |
160 | or %r1, %r2, %r1; |
161 | 161 | ||
162 | ! write DTLB data and install the kernel mapping |
162 | ! write DTLB data and install the kernel mapping |
163 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
163 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
164 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
164 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
165 | membar #Sync |
165 | membar #Sync |
166 | 166 | ||
167 | /* |
167 | /* |
168 | * Because we cannot use global mappings (because we want to have |
168 | * Because we cannot use global mappings (because we want to have |
169 | * separate 64-bit address spaces for both the kernel and the |
169 | * separate 64-bit address spaces for both the kernel and the |
170 | * userspace), we prepare the identity mapping also in context 1. This |
170 | * userspace), we prepare the identity mapping also in context 1. This |
171 | * step is required by the code installing the ITLB mapping. |
171 | * step is required by the code installing the ITLB mapping. |
172 | */ |
172 | */ |
173 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
173 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
174 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
174 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
175 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
175 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
176 | membar #Sync |
176 | membar #Sync |
177 | 177 | ||
178 | ! write DTLB data and install the kernel mapping in context 1 |
178 | ! write DTLB data and install the kernel mapping in context 1 |
179 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
179 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
180 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
180 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
181 | membar #Sync |
181 | membar #Sync |
182 | 182 | ||
183 | /* |
183 | /* |
184 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
184 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
185 | * as easily as the DMMU, because the IMMU is mapping the code it |
185 | * as easily as the DMMU, because the IMMU is mapping the code it |
186 | * executes. |
186 | * executes. |
187 | * |
187 | * |
188 | * [ Note that brave experiments with disabling the IMMU and using the |
188 | * [ Note that brave experiments with disabling the IMMU and using the |
189 | * DMMU approach failed after a dozen of desparate days with only little |
189 | * DMMU approach failed after a dozen of desparate days with only little |
190 | * success. ] |
190 | * success. ] |
191 | * |
191 | * |
192 | * The approach used here is inspired from OpenBSD. First, the kernel |
192 | * The approach used here is inspired from OpenBSD. First, the kernel |
193 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
193 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
194 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
194 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
195 | * afterwards and replaced with the kernel permanent mapping. Finally, |
195 | * afterwards and replaced with the kernel permanent mapping. Finally, |
196 | * the kernel switches back to context 0 and demaps context 1. |
196 | * the kernel switches back to context 0 and demaps context 1. |
197 | * |
197 | * |
198 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
198 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
199 | * is OK because we always use operands with addresses already mapped by |
199 | * is OK because we always use operands with addresses already mapped by |
200 | * the taken over DTLB. |
200 | * the taken over DTLB. |
201 | */ |
201 | */ |
202 | 202 | ||
203 | set kernel_image_start, %g5 |
203 | set kernel_image_start, %g5 |
204 | 204 | ||
205 | ! write ITLB tag of context 1 |
205 | ! write ITLB tag of context 1 |
206 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
206 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
207 | mov VA_DMMU_TAG_ACCESS, %g2 |
207 | mov VA_DMMU_TAG_ACCESS, %g2 |
208 | stxa %g1, [%g2] ASI_IMMU |
208 | stxa %g1, [%g2] ASI_IMMU |
209 | flush %g5 |
209 | flush %g5 |
210 | 210 | ||
211 | ! write ITLB data and install the temporary mapping in context 1 |
211 | ! write ITLB data and install the temporary mapping in context 1 |
212 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
212 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
213 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
213 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
214 | flush %g5 |
214 | flush %g5 |
215 | 215 | ||
216 | ! switch to context 1 |
216 | ! switch to context 1 |
217 | mov MEM_CONTEXT_TEMP, %g1 |
217 | mov MEM_CONTEXT_TEMP, %g1 |
218 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
218 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
219 | flush %g5 |
219 | flush %g5 |
220 | 220 | ||
221 | ! demap context 0 |
221 | ! demap context 0 |
222 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
222 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
223 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
223 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
224 | flush %g5 |
224 | flush %g5 |
225 | 225 | ||
226 | ! write ITLB tag of context 0 |
226 | ! write ITLB tag of context 0 |
227 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
227 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
228 | mov VA_DMMU_TAG_ACCESS, %g2 |
228 | mov VA_DMMU_TAG_ACCESS, %g2 |
229 | stxa %g1, [%g2] ASI_IMMU |
229 | stxa %g1, [%g2] ASI_IMMU |
230 | flush %g5 |
230 | flush %g5 |
231 | 231 | ||
232 | ! write ITLB data and install the permanent kernel mapping in context 0 |
232 | ! write ITLB data and install the permanent kernel mapping in context 0 |
233 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
233 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
234 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
234 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
235 | flush %g5 |
235 | flush %g5 |
236 | 236 | ||
237 | ! enter nucleus - using context 0 |
237 | ! enter nucleus - using context 0 |
238 | wrpr %g0, 1, %tl |
238 | wrpr %g0, 1, %tl |
239 | 239 | ||
240 | ! demap context 1 |
240 | ! demap context 1 |
241 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
241 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
242 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
242 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
243 | flush %g5 |
243 | flush %g5 |
244 | 244 | ||
245 | ! set context 0 in the primary context register |
245 | ! set context 0 in the primary context register |
246 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
246 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
247 | flush %g5 |
247 | flush %g5 |
248 | 248 | ||
249 | ! leave nucleus - using primary context, i.e. context 0 |
249 | ! leave nucleus - using primary context, i.e. context 0 |
250 | wrpr %g0, 0, %tl |
250 | wrpr %g0, 0, %tl |
251 | 251 | ||
252 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
252 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
253 | nop |
253 | nop |
254 | 254 | ||
255 | /* |
255 | /* |
256 | * Save physmem_base for use by the mm subsystem. |
256 | * Save physmem_base for use by the mm subsystem. |
257 | * %l6 contains starting physical address |
257 | * %l6 contains starting physical address |
258 | */ |
258 | */ |
259 | sethi %hi(physmem_base), %l4 |
259 | sethi %hi(physmem_base), %l4 |
260 | stx %l6, [%l4 + %lo(physmem_base)] |
260 | stx %l6, [%l4 + %lo(physmem_base)] |
261 | 261 | ||
262 | /* |
262 | /* |
263 | * Precompute kernel 8K TLB data template. |
263 | * Precompute kernel 8K TLB data template. |
264 | * %l5 contains starting physical address |
264 | * %l5 contains starting physical address |
265 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
265 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
266 | */ |
266 | */ |
267 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
267 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
268 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
268 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
269 | or %l3, %l5, %l3 |
269 | or %l3, %l5, %l3 |
270 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
270 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
271 | 271 | ||
272 | /* |
272 | /* |
273 | * Flush D-Cache. |
273 | * Flush D-Cache. |
274 | */ |
274 | */ |
275 | call dcache_flush |
275 | call dcache_flush |
276 | nop |
276 | nop |
277 | 277 | ||
278 | /* |
278 | /* |
279 | * So far, we have not touched the stack. |
279 | * So far, we have not touched the stack. |
280 | * It is a good idea to set the kernel stack to a known state now. |
280 | * It is a good idea to set the kernel stack to a known state now. |
281 | */ |
281 | */ |
282 | sethi %hi(temporary_boot_stack), %sp |
282 | sethi %hi(temporary_boot_stack), %sp |
283 | or %sp, %lo(temporary_boot_stack), %sp |
283 | or %sp, %lo(temporary_boot_stack), %sp |
284 | sub %sp, STACK_BIAS, %sp |
284 | sub %sp, STACK_BIAS, %sp |
285 | 285 | ||
286 | sethi 0x42142, %g0 |
286 | sethi 0x42142, %g0 |
287 | sethi %hi(bootinfo), %o0 |
287 | sethi %hi(bootinfo), %o0 |
288 | call memcpy ! copy bootinfo |
288 | call memcpy ! copy bootinfo |
289 | or %o0, %lo(bootinfo), %o0 |
289 | or %o0, %lo(bootinfo), %o0 |
290 | 290 | ||
291 | call arch_pre_main |
291 | call arch_pre_main |
292 | nop |
292 | nop |
293 | 293 | ||
294 | call main_bsp |
294 | call main_bsp |
295 | nop |
295 | nop |
296 | 296 | ||
297 | /* Not reached. */ |
297 | /* Not reached. */ |
298 | 298 | ||
299 | 0: |
299 | 0: |
300 | ba 0b |
300 | ba 0b |
301 | nop |
301 | nop |
302 | 302 | ||
303 | 303 | ||
304 | 1: |
304 | 1: |
305 | #ifdef CONFIG_SMP |
305 | #ifdef CONFIG_SMP |
306 | /* |
306 | /* |
307 | * Determine the width of the MID and save its mask to %g3. The width |
307 | * Determine the width of the MID and save its mask to %g3. The width |
308 | * is |
308 | * is |
309 | * * 5 for US and US-IIIi, |
309 | * * 5 for US and US-IIIi, |
310 | * * 10 for US3 except US-IIIi. |
310 | * * 10 for US3 except US-IIIi. |
311 | */ |
311 | */ |
312 | #if defined(US) |
312 | #if defined(US) |
313 | mov 0x1f, %g3 |
313 | mov 0x1f, %g3 |
314 | #elif defined(US3) |
314 | #elif defined(US3) |
315 | mov 0x3ff, %g3 |
315 | mov 0x3ff, %g3 |
316 | rdpr %ver, %g2 |
316 | rdpr %ver, %g2 |
317 | sllx %g2, 16, %g2 |
317 | sllx %g2, 16, %g2 |
318 | srlx %g2, 48, %g2 |
318 | srlx %g2, 48, %g2 |
319 | cmp %g2, IMPL_ULTRASPARCIII_I |
319 | cmp %g2, IMPL_ULTRASPARCIII_I |
320 | move %xcc, 0x1f, %g3 |
320 | move %xcc, 0x1f, %g3 |
321 | #endif |
321 | #endif |
322 | 322 | ||
323 | /* |
323 | /* |
324 | * Read MID from the processor. |
324 | * Read MID from the processor. |
325 | */ |
325 | */ |
326 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
326 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
327 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
327 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
328 | and %g1, %g3, %g1 |
328 | and %g1, %g3, %g1 |
329 | 329 | ||
330 | /* |
330 | /* |
331 | * Active loop for APs until the BSP picks them up. A processor cannot |
331 | * Active loop for APs until the BSP picks them up. A processor cannot |
332 | * leave the loop until the global variable 'waking_up_mid' equals its |
332 | * leave the loop until the global variable 'waking_up_mid' equals its |
333 | * MID. |
333 | * MID. |
334 | */ |
334 | */ |
335 | set waking_up_mid, %g2 |
335 | set waking_up_mid, %g2 |
336 | 2: |
336 | 2: |
337 | ldx [%g2], %g3 |
337 | ldx [%g2], %g3 |
338 | cmp %g3, %g1 |
338 | cmp %g3, %g1 |
339 | bne 2b |
339 | bne 2b |
340 | nop |
340 | nop |
341 | 341 | ||
342 | /* |
342 | /* |
343 | * Configure stack for the AP. |
343 | * Configure stack for the AP. |
344 | * The AP is expected to use the stack saved |
344 | * The AP is expected to use the stack saved |
345 | * in the ctx global variable. |
345 | * in the ctx global variable. |
346 | */ |
346 | */ |
347 | set ctx, %g1 |
347 | set ctx, %g1 |
348 | add %g1, OFFSET_SP, %g1 |
348 | add %g1, OFFSET_SP, %g1 |
349 | ldx [%g1], %o6 |
349 | ldx [%g1], %o6 |
350 | 350 | ||
351 | call main_ap |
351 | call main_ap |
352 | nop |
352 | nop |
353 | 353 | ||
354 | /* Not reached. */ |
354 | /* Not reached. */ |
355 | #endif |
355 | #endif |
356 | 356 | ||
357 | 0: |
357 | 0: |
358 | ba 0b |
358 | ba 0b |
359 | nop |
359 | nop |
360 | 360 | ||
361 | 361 | ||
362 | .section K_DATA_START, "aw", @progbits |
362 | .section K_DATA_START, "aw", @progbits |
363 | 363 | ||
364 | /* |
364 | /* |
365 | * Create small stack to be used by the bootstrap processor. It is going to be |
365 | * Create small stack to be used by the bootstrap processor. It is going to be |
366 | * used only for a very limited period of time, but we switch to it anyway, |
366 | * used only for a very limited period of time, but we switch to it anyway, |
367 | * just to be sure we are properly initialized. |
367 | * just to be sure we are properly initialized. |
368 | */ |
368 | */ |
369 | 369 | ||
370 | #define INITIAL_STACK_SIZE 1024 |
370 | #define INITIAL_STACK_SIZE 1024 |
371 | 371 | ||
372 | .align STACK_ALIGNMENT |
372 | .align STACK_ALIGNMENT |
373 | .space INITIAL_STACK_SIZE |
373 | .space INITIAL_STACK_SIZE |
374 | .align STACK_ALIGNMENT |
374 | .align STACK_ALIGNMENT |
375 | temporary_boot_stack: |
375 | temporary_boot_stack: |
376 | .space STACK_WINDOW_SAVE_AREA_SIZE |
376 | .space STACK_WINDOW_SAVE_AREA_SIZE |
377 | 377 | ||
378 | 378 | ||
379 | .data |
379 | .data |
380 | 380 | ||
381 | .align 8 |
381 | .align 8 |
382 | .global physmem_base ! copy of the physical memory base address |
382 | .global physmem_base ! copy of the physical memory base address |
383 | physmem_base: |
383 | physmem_base: |
384 | .quad 0 |
384 | .quad 0 |
385 | 385 | ||
386 | /* |
386 | /* |
387 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
387 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
388 | * is further modified to reflect the starting address of physical memory. |
388 | * is further modified to reflect the starting address of physical memory. |
389 | */ |
389 | */ |
390 | .global kernel_8k_tlb_data_template |
390 | .global kernel_8k_tlb_data_template |
391 | kernel_8k_tlb_data_template: |
391 | kernel_8k_tlb_data_template: |
392 | #ifdef CONFIG_VIRT_IDX_DCACHE |
392 | #ifdef CONFIG_VIRT_IDX_DCACHE |
393 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
393 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
394 | TTE_CV | TTE_P | TTE_W) |
394 | TTE_CV | TTE_P | TTE_W) |
395 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
395 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
396 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
396 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
397 | TTE_P | TTE_W) |
397 | TTE_P | TTE_W) |
398 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
398 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
399 | 399 | ||
400 | 400 |