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1 | # |
1 | # |
2 | # Copyright (C) 2005 Jakub Jermar |
2 | # Copyright (C) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/arch.h> |
29 | #include <arch/arch.h> |
30 | #include <arch/regdef.h> |
30 | #include <arch/regdef.h> |
31 | #include <arch/boot/boot.h> |
31 | #include <arch/boot/boot.h> |
32 | #include <arch/stack.h> |
32 | #include <arch/stack.h> |
33 | 33 | ||
34 | #include <arch/mm/mmu.h> |
34 | #include <arch/mm/mmu.h> |
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tte.h> |
36 | #include <arch/mm/tte.h> |
37 | 37 | ||
38 | #ifdef CONFIG_SMP |
38 | #ifdef CONFIG_SMP |
39 | #include <arch/context_offset.h> |
39 | #include <arch/context_offset.h> |
40 | #endif |
40 | #endif |
41 | 41 | ||
42 | .register %g2, #scratch |
42 | .register %g2, #scratch |
43 | .register %g3, #scratch |
43 | .register %g3, #scratch |
44 | 44 | ||
45 | .section K_TEXT_START, "ax" |
45 | .section K_TEXT_START, "ax" |
46 | 46 | ||
47 | #define BSP_FLAG 1 |
47 | #define BSP_FLAG 1 |
48 | 48 | ||
49 | /* |
49 | /* |
50 | * Here is where the kernel is passed control from the boot loader. |
50 | * Here is where the kernel is passed control from the boot loader. |
51 | * |
51 | * |
52 | * The registers are expected to be in this state: |
52 | * The registers are expected to be in this state: |
53 | * - %o0 starting address of physical memory + bootstrap processor flag |
53 | * - %o0 starting address of physical memory + bootstrap processor flag |
54 | * bits 63...1: physical memory starting address / 2 |
54 | * bits 63...1: physical memory starting address / 2 |
55 | * bit 0: non-zero on BSP processor, zero on AP processors |
55 | * bit 0: non-zero on BSP processor, zero on AP processors |
56 | * - %o1 bootinfo structure address (BSP only) |
56 | * - %o1 bootinfo structure address (BSP only) |
57 | * - %o2 bootinfo structure size (BSP only) |
57 | * - %o2 bootinfo structure size (BSP only) |
58 | * |
58 | * |
59 | * Moreover, we depend on boot having established the following environment: |
59 | * Moreover, we depend on boot having established the following environment: |
60 | * - TLBs are on |
60 | * - TLBs are on |
61 | * - identity mapping for the kernel image |
61 | * - identity mapping for the kernel image |
62 | */ |
62 | */ |
63 | 63 | ||
64 | .global kernel_image_start |
64 | .global kernel_image_start |
65 | kernel_image_start: |
65 | kernel_image_start: |
66 | mov BSP_FLAG, %l0 |
66 | mov BSP_FLAG, %l0 |
67 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
67 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
68 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
68 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
69 | 69 | ||
70 | sethi %hi(physmem_base), %l5 |
- | |
71 | stx %l6, [%l5 + %lo(physmem_base)] |
- | |
72 | - | ||
73 | /* |
- | |
74 | * Get bits 40:13 of physmem_base. |
70 | ! Get bits 40:13 of physmem_base. |
75 | */ |
- | |
76 | sethi %hi(mask_40_13), %l4 |
71 | srlx %l6, 13, %l5 |
77 | sethi %hi(physmem_base_40_13), %l3 |
- | |
78 | ldx [%l4 + %lo(mask_40_13)], %l4 |
72 | sllx %l5, 13 + (63 - 40), %l5 |
79 | and %l6, %l4, %l5 ! l5 <= physmem_base[40:13] |
73 | srlx %l5, 63 - 40, %l5 ! l5 <= physmem_base[40:13] |
80 | stx %l5, [%l3 + %lo(physmem_base_40_13)] |
- | |
81 | - | ||
82 | /* |
- | |
83 | * Prepare kernel 8K TLB data template. |
- | |
84 | */ |
- | |
85 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
- | |
86 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
- | |
87 | or %l3, %l5, %l3 |
- | |
88 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
- | |
89 | 74 | ||
90 | /* |
75 | /* |
91 | * Setup basic runtime environment. |
76 | * Setup basic runtime environment. |
92 | */ |
77 | */ |
93 | 78 | ||
94 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
79 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
95 | wrpr %g0, 0, %canrestore ! get rid of windows we will never need again |
80 | wrpr %g0, 0, %canrestore ! get rid of windows we will never need again |
96 | wrpr %g0, 0, %otherwin ! make sure the window state is consistent |
81 | wrpr %g0, 0, %otherwin ! make sure the window state is consistent |
97 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel |
82 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel |
98 | 83 | ||
99 | wrpr %g0, 0, %tl ! TL = 0, primary context register is used |
84 | wrpr %g0, 0, %tl ! TL = 0, primary context register is used |
100 | 85 | ||
101 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
86 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
102 | 87 | ||
103 | wrpr %g0, 0, %pil ! intialize %pil |
88 | wrpr %g0, 0, %pil ! intialize %pil |
104 | 89 | ||
105 | /* |
90 | /* |
106 | * Switch to kernel trap table. |
91 | * Switch to kernel trap table. |
107 | */ |
92 | */ |
108 | sethi %hi(trap_table), %g1 |
93 | sethi %hi(trap_table), %g1 |
109 | wrpr %g1, %lo(trap_table), %tba |
94 | wrpr %g1, %lo(trap_table), %tba |
110 | 95 | ||
111 | /* |
96 | /* |
112 | * Take over the DMMU by installing global locked |
97 | * Take over the DMMU by installing global locked |
113 | * TTE entry identically mapping the first 4M |
98 | * TTE entry identically mapping the first 4M |
114 | * of memory. |
99 | * of memory. |
115 | * |
100 | * |
116 | * In case of DMMU, no FLUSH instructions need to be |
101 | * In case of DMMU, no FLUSH instructions need to be |
117 | * issued. Because of that, the old DTLB contents can |
102 | * issued. Because of that, the old DTLB contents can |
118 | * be demapped pretty straightforwardly and without |
103 | * be demapped pretty straightforwardly and without |
119 | * causing any traps. |
104 | * causing any traps. |
120 | */ |
105 | */ |
121 | 106 | ||
122 | wr %g0, ASI_DMMU, %asi |
107 | wr %g0, ASI_DMMU, %asi |
123 | 108 | ||
124 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
109 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
125 | set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1 |
110 | set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1 |
126 | 111 | ||
127 | ! demap context 0 |
112 | ! demap context 0 |
128 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
113 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
129 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
114 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
130 | membar #Sync |
115 | membar #Sync |
131 | 116 | ||
132 | #define SET_TLB_TAG(r1, context) \ |
117 | #define SET_TLB_TAG(r1, context) \ |
133 | set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
118 | set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
134 | 119 | ||
135 | ! write DTLB tag |
120 | ! write DTLB tag |
136 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
121 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
137 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
122 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
138 | membar #Sync |
123 | membar #Sync |
139 | 124 | ||
140 | #define SET_TLB_DATA(r1, r2, imm) \ |
125 | #define SET_TLB_DATA(r1, r2, imm) \ |
141 | set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \ |
126 | set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \ |
142 | or %r1, %l5, %r1; \ |
127 | or %r1, %l5, %r1; \ |
143 | mov PAGESIZE_4M, %r2; \ |
128 | mov PAGESIZE_4M, %r2; \ |
144 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
129 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
145 | or %r1, %r2, %r1; \ |
130 | or %r1, %r2, %r1; \ |
146 | mov 1, %r2; \ |
131 | mov 1, %r2; \ |
147 | sllx %r2, TTE_V_SHIFT, %r2; \ |
132 | sllx %r2, TTE_V_SHIFT, %r2; \ |
148 | or %r1, %r2, %r1; |
133 | or %r1, %r2, %r1; |
149 | 134 | ||
150 | ! write DTLB data and install the kernel mapping |
135 | ! write DTLB data and install the kernel mapping |
151 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
136 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
152 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
137 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
153 | membar #Sync |
138 | membar #Sync |
154 | 139 | ||
155 | /* |
140 | /* |
156 | * Because we cannot use global mappings (because we want to |
141 | * Because we cannot use global mappings (because we want to |
157 | * have separate 64-bit address spaces for both the kernel |
142 | * have separate 64-bit address spaces for both the kernel |
158 | * and the userspace), we prepare the identity mapping also in |
143 | * and the userspace), we prepare the identity mapping also in |
159 | * context 1. This step is required by the |
144 | * context 1. This step is required by the |
160 | * code installing the ITLB mapping. |
145 | * code installing the ITLB mapping. |
161 | */ |
146 | */ |
162 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
147 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
163 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
148 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
164 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
149 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
165 | membar #Sync |
150 | membar #Sync |
166 | 151 | ||
167 | ! write DTLB data and install the kernel mapping in context 1 |
152 | ! write DTLB data and install the kernel mapping in context 1 |
168 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
153 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
169 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
154 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
170 | membar #Sync |
155 | membar #Sync |
171 | 156 | ||
172 | /* |
157 | /* |
173 | * Now is time to take over the IMMU. |
158 | * Now is time to take over the IMMU. |
174 | * Unfortunatelly, it cannot be done as easily as the DMMU, |
159 | * Unfortunatelly, it cannot be done as easily as the DMMU, |
175 | * because the IMMU is mapping the code it executes. |
160 | * because the IMMU is mapping the code it executes. |
176 | * |
161 | * |
177 | * [ Note that brave experiments with disabling the IMMU |
162 | * [ Note that brave experiments with disabling the IMMU |
178 | * and using the DMMU approach failed after a dozen |
163 | * and using the DMMU approach failed after a dozen |
179 | * of desparate days with only little success. ] |
164 | * of desparate days with only little success. ] |
180 | * |
165 | * |
181 | * The approach used here is inspired from OpenBSD. |
166 | * The approach used here is inspired from OpenBSD. |
182 | * First, the kernel creates IMMU mapping for itself |
167 | * First, the kernel creates IMMU mapping for itself |
183 | * in context 1 (MEM_CONTEXT_TEMP) and switches to |
168 | * in context 1 (MEM_CONTEXT_TEMP) and switches to |
184 | * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
169 | * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
185 | * afterwards and replaced with the kernel permanent |
170 | * afterwards and replaced with the kernel permanent |
186 | * mapping. Finally, the kernel switches back to |
171 | * mapping. Finally, the kernel switches back to |
187 | * context 0 and demaps context 1. |
172 | * context 0 and demaps context 1. |
188 | * |
173 | * |
189 | * Moreover, the IMMU requires use of the FLUSH instructions. |
174 | * Moreover, the IMMU requires use of the FLUSH instructions. |
190 | * But that is OK because we always use operands with |
175 | * But that is OK because we always use operands with |
191 | * addresses already mapped by the taken over DTLB. |
176 | * addresses already mapped by the taken over DTLB. |
192 | */ |
177 | */ |
193 | 178 | ||
194 | set kernel_image_start, %g5 |
179 | set kernel_image_start, %g5 |
195 | 180 | ||
196 | ! write ITLB tag of context 1 |
181 | ! write ITLB tag of context 1 |
197 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
182 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
198 | mov VA_DMMU_TAG_ACCESS, %g2 |
183 | mov VA_DMMU_TAG_ACCESS, %g2 |
199 | stxa %g1, [%g2] ASI_IMMU |
184 | stxa %g1, [%g2] ASI_IMMU |
200 | flush %g5 |
185 | flush %g5 |
201 | 186 | ||
202 | ! write ITLB data and install the temporary mapping in context 1 |
187 | ! write ITLB data and install the temporary mapping in context 1 |
203 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
188 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
204 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
189 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
205 | flush %g5 |
190 | flush %g5 |
206 | 191 | ||
207 | ! switch to context 1 |
192 | ! switch to context 1 |
208 | mov MEM_CONTEXT_TEMP, %g1 |
193 | mov MEM_CONTEXT_TEMP, %g1 |
209 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
194 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
210 | flush %g5 |
195 | flush %g5 |
211 | 196 | ||
212 | ! demap context 0 |
197 | ! demap context 0 |
213 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
198 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
214 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
199 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
215 | flush %g5 |
200 | flush %g5 |
216 | 201 | ||
217 | ! write ITLB tag of context 0 |
202 | ! write ITLB tag of context 0 |
218 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
203 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
219 | mov VA_DMMU_TAG_ACCESS, %g2 |
204 | mov VA_DMMU_TAG_ACCESS, %g2 |
220 | stxa %g1, [%g2] ASI_IMMU |
205 | stxa %g1, [%g2] ASI_IMMU |
221 | flush %g5 |
206 | flush %g5 |
222 | 207 | ||
223 | ! write ITLB data and install the permanent kernel mapping in context 0 |
208 | ! write ITLB data and install the permanent kernel mapping in context 0 |
224 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
209 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
225 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
210 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
226 | flush %g5 |
211 | flush %g5 |
227 | 212 | ||
228 | ! enter nucleus - using context 0 |
213 | ! enter nucleus - using context 0 |
229 | wrpr %g0, 1, %tl |
214 | wrpr %g0, 1, %tl |
230 | 215 | ||
231 | ! demap context 1 |
216 | ! demap context 1 |
232 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
217 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
233 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
218 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
234 | flush %g5 |
219 | flush %g5 |
235 | 220 | ||
236 | ! set context 0 in the primary context register |
221 | ! set context 0 in the primary context register |
237 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
222 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
238 | flush %g5 |
223 | flush %g5 |
239 | 224 | ||
240 | ! leave nucleus - using primary context, i.e. context 0 |
225 | ! leave nucleus - using primary context, i.e. context 0 |
241 | wrpr %g0, 0, %tl |
226 | wrpr %g0, 0, %tl |
242 | 227 | ||
243 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
228 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
244 | nop |
229 | nop |
245 | 230 | ||
246 | /* |
231 | /* |
- | 232 | * Save physmem_base for use by the mm subsystem. |
|
- | 233 | * %l6 contains starting physical address |
|
- | 234 | */ |
|
- | 235 | sethi %hi(physmem_base), %l4 |
|
- | 236 | stx %l6, [%l4 + %lo(physmem_base)] |
|
- | 237 | ||
- | 238 | /* |
|
- | 239 | * Precompute kernel 8K TLB data template. |
|
- | 240 | * %l5 contains starting physical address bits [40:13] |
|
- | 241 | */ |
|
- | 242 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
|
- | 243 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
|
- | 244 | or %l3, %l5, %l3 |
|
- | 245 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
|
- | 246 | ||
- | 247 | /* |
|
247 | * So far, we have not touched the stack. |
248 | * So far, we have not touched the stack. |
248 | * It is a good idea to set the kernel stack to a known state now. |
249 | * It is a good idea to set the kernel stack to a known state now. |
249 | */ |
250 | */ |
250 | sethi %hi(temporary_boot_stack), %sp |
251 | sethi %hi(temporary_boot_stack), %sp |
251 | or %sp, %lo(temporary_boot_stack), %sp |
252 | or %sp, %lo(temporary_boot_stack), %sp |
252 | sub %sp, STACK_BIAS, %sp |
253 | sub %sp, STACK_BIAS, %sp |
253 | 254 | ||
254 | sethi %hi(bootinfo), %o0 |
255 | sethi %hi(bootinfo), %o0 |
255 | call memcpy ! copy bootinfo |
256 | call memcpy ! copy bootinfo |
256 | or %o0, %lo(bootinfo), %o0 |
257 | or %o0, %lo(bootinfo), %o0 |
257 | 258 | ||
258 | call arch_pre_main |
259 | call arch_pre_main |
259 | nop |
260 | nop |
260 | 261 | ||
261 | call main_bsp |
262 | call main_bsp |
262 | nop |
263 | nop |
263 | 264 | ||
264 | /* Not reached. */ |
265 | /* Not reached. */ |
265 | 266 | ||
266 | 0: |
267 | 0: |
267 | ba 0b |
268 | ba 0b |
268 | nop |
269 | nop |
269 | 270 | ||
270 | 271 | ||
271 | /* |
272 | /* |
272 | * Read MID from the processor. |
273 | * Read MID from the processor. |
273 | */ |
274 | */ |
274 | 1: |
275 | 1: |
275 | ldxa [%g0] ASI_UPA_CONFIG, %g1 |
276 | ldxa [%g0] ASI_UPA_CONFIG, %g1 |
276 | srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 |
277 | srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 |
277 | and %g1, UPA_CONFIG_MID_MASK, %g1 |
278 | and %g1, UPA_CONFIG_MID_MASK, %g1 |
278 | 279 | ||
279 | #ifdef CONFIG_SMP |
280 | #ifdef CONFIG_SMP |
280 | /* |
281 | /* |
281 | * Active loop for APs until the BSP picks them up. |
282 | * Active loop for APs until the BSP picks them up. |
282 | * A processor cannot leave the loop until the |
283 | * A processor cannot leave the loop until the |
283 | * global variable 'waking_up_mid' equals its |
284 | * global variable 'waking_up_mid' equals its |
284 | * MID. |
285 | * MID. |
285 | */ |
286 | */ |
286 | set waking_up_mid, %g2 |
287 | set waking_up_mid, %g2 |
287 | 2: |
288 | 2: |
288 | ldx [%g2], %g3 |
289 | ldx [%g2], %g3 |
289 | cmp %g3, %g1 |
290 | cmp %g3, %g1 |
290 | bne 2b |
291 | bne 2b |
291 | nop |
292 | nop |
292 | 293 | ||
293 | /* |
294 | /* |
294 | * Configure stack for the AP. |
295 | * Configure stack for the AP. |
295 | * The AP is expected to use the stack saved |
296 | * The AP is expected to use the stack saved |
296 | * in the ctx global variable. |
297 | * in the ctx global variable. |
297 | */ |
298 | */ |
298 | set ctx, %g1 |
299 | set ctx, %g1 |
299 | add %g1, OFFSET_SP, %g1 |
300 | add %g1, OFFSET_SP, %g1 |
300 | ldx [%g1], %o6 |
301 | ldx [%g1], %o6 |
301 | 302 | ||
302 | call main_ap |
303 | call main_ap |
303 | nop |
304 | nop |
304 | 305 | ||
305 | /* Not reached. */ |
306 | /* Not reached. */ |
306 | #endif |
307 | #endif |
307 | 308 | ||
308 | 0: |
309 | 0: |
309 | ba 0b |
310 | ba 0b |
310 | nop |
311 | nop |
311 | 312 | ||
312 | 313 | ||
313 | .section K_DATA_START, "aw", @progbits |
314 | .section K_DATA_START, "aw", @progbits |
314 | 315 | ||
315 | /* |
316 | /* |
316 | * Create small stack to be used by the bootstrap processor. |
317 | * Create small stack to be used by the bootstrap processor. |
317 | * It is going to be used only for a very limited period of |
318 | * It is going to be used only for a very limited period of |
318 | * time, but we switch to it anyway, just to be sure we are |
319 | * time, but we switch to it anyway, just to be sure we are |
319 | * properly initialized. |
320 | * properly initialized. |
320 | * |
321 | * |
321 | * What is important is that this piece of memory is covered |
322 | * What is important is that this piece of memory is covered |
322 | * by the 4M DTLB locked entry and therefore there will be |
323 | * by the 4M DTLB locked entry and therefore there will be |
323 | * no surprises like deadly combinations of spill trap and |
324 | * no surprises like deadly combinations of spill trap and |
324 | * and TLB miss on the stack address. |
325 | * and TLB miss on the stack address. |
325 | */ |
326 | */ |
326 | 327 | ||
327 | #define INITIAL_STACK_SIZE 1024 |
328 | #define INITIAL_STACK_SIZE 1024 |
328 | 329 | ||
329 | .align STACK_ALIGNMENT |
330 | .align STACK_ALIGNMENT |
330 | .space INITIAL_STACK_SIZE |
331 | .space INITIAL_STACK_SIZE |
331 | .align STACK_ALIGNMENT |
332 | .align STACK_ALIGNMENT |
332 | temporary_boot_stack: |
333 | temporary_boot_stack: |
333 | .space STACK_WINDOW_SAVE_AREA_SIZE |
334 | .space STACK_WINDOW_SAVE_AREA_SIZE |
334 | 335 | ||
335 | 336 | ||
336 | .data |
337 | .data |
337 | 338 | ||
338 | .align 8 |
339 | .align 8 |
339 | .global physmem_base ! copy of the physical memory base address |
340 | .global physmem_base ! copy of the physical memory base address |
340 | physmem_base: |
341 | physmem_base: |
341 | .quad 0 |
342 | .quad 0 |
342 | 343 | ||
343 | .global physmem_base_40_13 |
- | |
344 | physmem_base_40_13: ! physmem_base & mask_40_13 |
- | |
345 | .quad 0 |
- | |
346 | - | ||
347 | .global mask_40_13 |
- | |
348 | mask_40_13: ! constant with bits 40:13 set |
- | |
349 | .quad (((1 << 41) - 1) & ~((1 << 13) - 1)) |
- | |
350 | - | ||
351 | /* |
344 | /* |
352 | * This variable is used by the fast_data_MMU_miss trap handler. |
345 | * This variable is used by the fast_data_MMU_miss trap handler. |
353 | * It is initialized to reflect the starting address of physical |
346 | * In runtime, it is further modified to reflect the starting address of |
354 | * memory. |
347 | * physical memory. |
355 | */ |
348 | */ |
356 | .global kernel_8k_tlb_data_template |
349 | .global kernel_8k_tlb_data_template |
357 | kernel_8k_tlb_data_template: |
350 | kernel_8k_tlb_data_template: |
358 | .quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W) |
351 | .quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W) |
359 | - | ||
360 | 352 |