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/*
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/*
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 * Copyright (C) 2005 Jakub Jermar
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64
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/** @addtogroup sparc64
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include <arch.h>
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#include <arch.h>
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#include <debug.h>
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#include <debug.h>
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#include <arch/trap/trap.h>
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#include <arch/trap/trap.h>
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#include <arch/console.h>
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#include <arch/console.h>
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#include <arch/drivers/tick.h>
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#include <arch/drivers/tick.h>
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#include <proc/thread.h>
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#include <proc/thread.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <arch/boot/boot.h>
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#include <arch/boot/boot.h>
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#include <arch/arch.h>
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#include <arch/mm/tlb.h>
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#include <mm/asid.h>
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bootinfo_t bootinfo;
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bootinfo_t bootinfo;
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void arch_pre_mm_init(void)
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void arch_pre_mm_init(void)
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{
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{
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    trap_init();
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    trap_init();
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    tick_init();
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    tick_init();
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}
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}
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void arch_post_mm_init(void)
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void arch_post_mm_init(void)
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{
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{
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    standalone_sparc64_console_init();
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    standalone_sparc64_console_init();
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}
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}
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void arch_pre_smp_init(void)
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void arch_pre_smp_init(void)
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{
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{
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}
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}
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void arch_post_smp_init(void)
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void arch_post_smp_init(void)
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{
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{
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    thread_t *t;
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    thread_t *t;
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    /*
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    /*
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         * Create thread that polls keyboard.
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         * Create thread that polls keyboard.
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         */
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         */
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    t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll");
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    t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll");
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    if (!t)
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    if (!t)
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        panic("cannot create kkbdpoll\n");
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        panic("cannot create kkbdpoll\n");
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    thread_ready(t);
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    thread_ready(t);
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}
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}
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void calibrate_delay_loop(void)
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void calibrate_delay_loop(void)
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{
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{
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}
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}
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/** Acquire console back for kernel
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/** Acquire console back for kernel
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 *
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 *
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 */
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 */
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void arch_grab_console(void)
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void arch_grab_console(void)
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{
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{
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}
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}
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/** Return console to userspace
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/** Return console to userspace
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 *
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 *
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 */
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 */
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void arch_release_console(void)
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void arch_release_console(void)
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{
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{
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}
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}
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/** Take over TLB and trap table.
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 *
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 * Initialize ITLB and DTLB and switch to kernel
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 * trap table.
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 *
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 * The goal of this function is to disable MMU
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 * so that both TLBs can be purged and new
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 * kernel 4M locked entry can be installed.
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 * After TLB is initialized, MMU is enabled
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 * again.
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 *
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 * Switching MMU off imposes the requirement for
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 * the kernel to run in identity mapped environment.
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 *
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 * @param base Base address that will be hardwired in both TLBs.
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 */
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void take_over_tlb_and_tt(uintptr_t base)
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{
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    tlb_tag_access_reg_t tag;
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    tlb_data_t data;
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    frame_address_t fr;
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    page_address_t pg;
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    fr.address = base;
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    pg.address = base;
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    immu_disable();
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    dmmu_disable();
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    /*
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     * Demap everything, especially OpenFirmware.
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     */
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    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    /*
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     * We do identity mapping of 4M-page at 4M.
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     */
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    tag.value = ASID_KERNEL;
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    tag.vpn = pg.vpn;
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    itlb_tag_access_write(tag.value);
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    dtlb_tag_access_write(tag.value);
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    data.value = 0;
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    data.v = true;
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    data.size = PAGESIZE_4M;
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    data.pfn = fr.pfn;
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    data.l = true;
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    data.cp = 1;
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    data.cv = 1;
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    data.p = true;
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    data.w = true;
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    data.g = true;
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    itlb_data_in_write(data.value);
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    dtlb_data_in_write(data.value);
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    /*
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     * Register window traps can occur before MMU is enabled again.
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     * This ensures that any such traps will be handled from
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     * kernel identity mapped trap handler.
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     */
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    trap_switch_trap_table();
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    tlb_invalidate_all();
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    dmmu_enable();
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    immu_enable();
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}
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/** @}
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/** @}
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 */
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 */
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