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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/as.h> |
35 | #include <arch/mm/as.h> |
- | 36 | #include <arch/mm/pagesize.h> |
|
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/mm/sun4u/tlb.h> |
37 | #include <arch/mm/sun4u/tlb.h> |
38 | #include <arch/mm/sun4u/tlb.h> |
38 | #include <genarch/mm/page_ht.h> |
39 | #include <genarch/mm/page_ht.h> |
39 | #include <genarch/mm/asid_fifo.h> |
40 | #include <genarch/mm/asid_fifo.h> |
40 | #include <debug.h> |
41 | #include <debug.h> |
41 | #include <config.h> |
42 | #include <config.h> |
42 | 43 | ||
43 | #ifdef CONFIG_TSB |
44 | #ifdef CONFIG_TSB |
44 | #include <arch/mm/tsb.h> |
45 | #include <arch/mm/tsb.h> |
45 | #include <arch/memstr.h> |
46 | #include <arch/memstr.h> |
46 | #include <arch/asm.h> |
47 | #include <arch/asm.h> |
47 | #include <mm/frame.h> |
48 | #include <mm/frame.h> |
48 | #include <bitops.h> |
49 | #include <bitops.h> |
49 | #include <macros.h> |
50 | #include <macros.h> |
50 | #endif /* CONFIG_TSB */ |
51 | #endif /* CONFIG_TSB */ |
51 | 52 | ||
52 | /** Architecture dependent address space init. */ |
53 | /** Architecture dependent address space init. */ |
53 | void as_arch_init(void) |
54 | void as_arch_init(void) |
54 | { |
55 | { |
55 | if (config.cpu_active == 1) { |
56 | if (config.cpu_active == 1) { |
56 | as_operations = &as_ht_operations; |
57 | as_operations = &as_ht_operations; |
57 | asid_fifo_init(); |
58 | asid_fifo_init(); |
58 | } |
59 | } |
59 | } |
60 | } |
60 | 61 | ||
61 | int as_constructor_arch(as_t *as, int flags) |
62 | int as_constructor_arch(as_t *as, int flags) |
62 | { |
63 | { |
63 | #ifdef CONFIG_TSB |
64 | #ifdef CONFIG_TSB |
64 | /* |
65 | /* |
65 | * The order must be calculated with respect to the emulated |
66 | * The order must be calculated with respect to the emulated |
66 | * 16K page size. |
67 | * 16K page size. |
67 | */ |
68 | */ |
68 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
69 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
69 | sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
70 | sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
70 | 71 | ||
71 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
72 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
72 | 73 | ||
73 | if (!tsb) |
74 | if (!tsb) |
74 | return -1; |
75 | return -1; |
75 | 76 | ||
76 | as->arch.itsb = (tsb_entry_t *) tsb; |
77 | as->arch.itsb = (tsb_entry_t *) tsb; |
77 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
78 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
78 | sizeof(tsb_entry_t)); |
79 | sizeof(tsb_entry_t)); |
79 | 80 | ||
80 | memsetb(as->arch.itsb, |
81 | memsetb(as->arch.itsb, |
81 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
82 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
82 | #endif |
83 | #endif |
83 | return 0; |
84 | return 0; |
84 | } |
85 | } |
85 | 86 | ||
86 | int as_destructor_arch(as_t *as) |
87 | int as_destructor_arch(as_t *as) |
87 | { |
88 | { |
88 | #ifdef CONFIG_TSB |
89 | #ifdef CONFIG_TSB |
89 | /* |
90 | /* |
90 | * The count must be calculated with respect to the emualted 16K page |
91 | * The count must be calculated with respect to the emualted 16K page |
91 | * size. |
92 | * size. |
92 | */ |
93 | */ |
93 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
94 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
94 | sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
95 | sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
95 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
96 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
96 | return cnt; |
97 | return cnt; |
97 | #else |
98 | #else |
98 | return 0; |
99 | return 0; |
99 | #endif |
100 | #endif |
100 | } |
101 | } |
101 | 102 | ||
102 | int as_create_arch(as_t *as, int flags) |
103 | int as_create_arch(as_t *as, int flags) |
103 | { |
104 | { |
104 | #ifdef CONFIG_TSB |
105 | #ifdef CONFIG_TSB |
105 | tsb_invalidate(as, 0, (count_t) -1); |
106 | tsb_invalidate(as, 0, (count_t) -1); |
106 | #endif |
107 | #endif |
107 | return 0; |
108 | return 0; |
108 | } |
109 | } |
109 | 110 | ||
110 | /** Perform sparc64-specific tasks when an address space becomes active on the |
111 | /** Perform sparc64-specific tasks when an address space becomes active on the |
111 | * processor. |
112 | * processor. |
112 | * |
113 | * |
113 | * Install ASID and map TSBs. |
114 | * Install ASID and map TSBs. |
114 | * |
115 | * |
115 | * @param as Address space. |
116 | * @param as Address space. |
116 | */ |
117 | */ |
117 | void as_install_arch(as_t *as) |
118 | void as_install_arch(as_t *as) |
118 | { |
119 | { |
119 | tlb_context_reg_t ctx; |
120 | tlb_context_reg_t ctx; |
120 | 121 | ||
121 | /* |
122 | /* |
122 | * Note that we don't and may not lock the address space. That's ok |
123 | * Note that we don't and may not lock the address space. That's ok |
123 | * since we only read members that are currently read-only. |
124 | * since we only read members that are currently read-only. |
124 | * |
125 | * |
125 | * Moreover, the as->asid is protected by asidlock, which is being held. |
126 | * Moreover, the as->asid is protected by asidlock, which is being held. |
126 | */ |
127 | */ |
127 | 128 | ||
128 | /* |
129 | /* |
129 | * Write ASID to secondary context register. The primary context |
130 | * Write ASID to secondary context register. The primary context |
130 | * register has to be set from TL>0 so it will be filled from the |
131 | * register has to be set from TL>0 so it will be filled from the |
131 | * secondary context register from the TL=1 code just before switch to |
132 | * secondary context register from the TL=1 code just before switch to |
132 | * userspace. |
133 | * userspace. |
133 | */ |
134 | */ |
134 | ctx.v = 0; |
135 | ctx.v = 0; |
135 | ctx.context = as->asid; |
136 | ctx.context = as->asid; |
136 | mmu_secondary_context_write(ctx.v); |
137 | mmu_secondary_context_write(ctx.v); |
137 | 138 | ||
138 | #ifdef CONFIG_TSB |
139 | #ifdef CONFIG_TSB |
139 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
140 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
140 | 141 | ||
141 | ASSERT(as->arch.itsb && as->arch.dtsb); |
142 | ASSERT(as->arch.itsb && as->arch.dtsb); |
142 | 143 | ||
143 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
144 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
144 | 145 | ||
145 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
146 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
146 | /* |
147 | /* |
147 | * TSBs were allocated from memory not covered |
148 | * TSBs were allocated from memory not covered |
148 | * by the locked 4M kernel DTLB entry. We need |
149 | * by the locked 4M kernel DTLB entry. We need |
149 | * to map both TSBs explicitly. |
150 | * to map both TSBs explicitly. |
150 | */ |
151 | */ |
151 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
152 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
152 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
153 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
153 | } |
154 | } |
154 | 155 | ||
155 | /* |
156 | /* |
156 | * Setup TSB Base registers. |
157 | * Setup TSB Base registers. |
157 | */ |
158 | */ |
158 | tsb_base_reg_t tsb_base; |
159 | tsb_base_reg_t tsb_base; |
159 | 160 | ||
160 | tsb_base.value = 0; |
161 | tsb_base.value = 0; |
161 | tsb_base.size = TSB_SIZE; |
162 | tsb_base.size = TSB_SIZE; |
162 | tsb_base.split = 0; |
163 | tsb_base.split = 0; |
163 | 164 | ||
164 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
165 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
165 | itsb_base_write(tsb_base.value); |
166 | itsb_base_write(tsb_base.value); |
166 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
167 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
167 | dtsb_base_write(tsb_base.value); |
168 | dtsb_base_write(tsb_base.value); |
168 | 169 | ||
169 | #if defined (US3) |
170 | #if defined (US3) |
170 | /* |
171 | /* |
171 | * Clear the extension registers. |
172 | * Clear the extension registers. |
172 | * In HelenOS, primary and secondary context registers contain |
173 | * In HelenOS, primary and secondary context registers contain |
173 | * equal values and kernel misses (context 0, ie. the nucleus context) |
174 | * equal values and kernel misses (context 0, ie. the nucleus context) |
174 | * are excluded from the TSB miss handler, so it makes no sense |
175 | * are excluded from the TSB miss handler, so it makes no sense |
175 | * to have separate TSBs for primary, secondary and nucleus contexts. |
176 | * to have separate TSBs for primary, secondary and nucleus contexts. |
176 | * Clearing the extension registers will ensure that the value of the |
177 | * Clearing the extension registers will ensure that the value of the |
177 | * TSB Base register will be used as an address of TSB, making the code |
178 | * TSB Base register will be used as an address of TSB, making the code |
178 | * compatible with the US port. |
179 | * compatible with the US port. |
179 | */ |
180 | */ |
180 | itsb_primary_extension_write(0); |
181 | itsb_primary_extension_write(0); |
181 | itsb_nucleus_extension_write(0); |
182 | itsb_nucleus_extension_write(0); |
182 | dtsb_primary_extension_write(0); |
183 | dtsb_primary_extension_write(0); |
183 | dtsb_secondary_extension_write(0); |
184 | dtsb_secondary_extension_write(0); |
184 | dtsb_nucleus_extension_write(0); |
185 | dtsb_nucleus_extension_write(0); |
185 | #endif |
186 | #endif |
186 | #endif |
187 | #endif |
187 | } |
188 | } |
188 | 189 | ||
189 | /** Perform sparc64-specific tasks when an address space is removed from the |
190 | /** Perform sparc64-specific tasks when an address space is removed from the |
190 | * processor. |
191 | * processor. |
191 | * |
192 | * |
192 | * Demap TSBs. |
193 | * Demap TSBs. |
193 | * |
194 | * |
194 | * @param as Address space. |
195 | * @param as Address space. |
195 | */ |
196 | */ |
196 | void as_deinstall_arch(as_t *as) |
197 | void as_deinstall_arch(as_t *as) |
197 | { |
198 | { |
198 | 199 | ||
199 | /* |
200 | /* |
200 | * Note that we don't and may not lock the address space. That's ok |
201 | * Note that we don't and may not lock the address space. That's ok |
201 | * since we only read members that are currently read-only. |
202 | * since we only read members that are currently read-only. |
202 | * |
203 | * |
203 | * Moreover, the as->asid is protected by asidlock, which is being held. |
204 | * Moreover, the as->asid is protected by asidlock, which is being held. |
204 | */ |
205 | */ |
205 | 206 | ||
206 | #ifdef CONFIG_TSB |
207 | #ifdef CONFIG_TSB |
207 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
208 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
208 | 209 | ||
209 | ASSERT(as->arch.itsb && as->arch.dtsb); |
210 | ASSERT(as->arch.itsb && as->arch.dtsb); |
210 | 211 | ||
211 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
212 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
212 | 213 | ||
213 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
214 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
214 | /* |
215 | /* |
215 | * TSBs were allocated from memory not covered |
216 | * TSBs were allocated from memory not covered |
216 | * by the locked 4M kernel DTLB entry. We need |
217 | * by the locked 4M kernel DTLB entry. We need |
217 | * to demap the entry installed by as_install_arch(). |
218 | * to demap the entry installed by as_install_arch(). |
218 | */ |
219 | */ |
219 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
220 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
220 | } |
221 | } |
221 | #endif |
222 | #endif |
222 | } |
223 | } |
223 | 224 | ||
224 | /** @} |
225 | /** @} |
225 | */ |
226 | */ |
226 | 227 |