WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_TLB_H_
#define KERN_sparc64_TLB_H_
 
#if defined (US)
#define ITLB_ENTRY_COUNT        64
#define DTLB_ENTRY_COUNT        64
#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
#endif
 
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES     16
#endif
 
#define MEM_CONTEXT_KERNEL      0
#define MEM_CONTEXT_TEMP        1
 
/** Page sizes. */
#define PAGESIZE_8K 0
#define PAGESIZE_64K    1
#define PAGESIZE_512K   2
#define PAGESIZE_4M 3
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       22  /* 4M */
 
/* TLB Demap Operation types. */
#define TLB_DEMAP_PAGE      0
#define TLB_DEMAP_CONTEXT   1
#if defined (US3)
#define TLB_DEMAP_ALL       2
#endif
 
#define TLB_DEMAP_TYPE_SHIFT    6
 
/* TLB Demap Operation Context register encodings. */
#define TLB_DEMAP_PRIMARY   0
#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS   2
 
/* There are more TLBs in one MMU in US3, their codes are defined here. */
#if defined (US3)
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
#define TLB_DSMALL  0
#define TLB_DBIG_0  2
#define TLB_DBIG_1  3
   
/* I-MMU: one small (16-entry) TLB and one big TLB */
#define TLB_ISMALL  0
#define TLB_IBIG    2
#endif
 
#define TLB_DEMAP_CONTEXT_SHIFT 4
 
/* TLB Tag Access shifts */
#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
#define TLB_TAG_ACCESS_VPN_SHIFT    13
 
#ifndef __ASM__
 
#include <arch/mm/tte.h>
#include <arch/mm/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
union tlb_context_reg {
    uint64_t v;
    struct {
        unsigned long : 51;
        unsigned context : 13;      /**< Context/ASID. */
    } __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
 
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
 
#if defined (US)
 
union tlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 55;
        unsigned tlb_entry : 6;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
typedef union tlb_data_access_addr itlb_data_access_addr_t;
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
 
#elif defined (US3)
 
/*
 * In US3, I-MMU and D-MMU have different formats of the data
 * access register virtual address. In the corresponding
 * structures the member variable for the entry number is
 * called "local_tlb_entry" - it contrast with the "tlb_entry"
 * for the US data access register VA structure. The rationale
 * behind this is to prevent careless mistakes in the code
 * caused by setting only the entry number and not the TLB
 * number in the US3 code (when taking the code from US).
 */
 
union dtlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 4;
        unsigned local_tlb_entry : 9;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
 
union itlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 45;
        unsigned : 1;
        unsigned tlb_number : 2;
        unsigned : 6;
        unsigned local_tlb_entry : 7;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union itlb_data_access_addr itlb_data_access_addr_t;
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
 
#endif
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
    // TODO have a look at how non-8kB pages will be treated
    uint64_t value;
    struct {
        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
        unsigned context : 13;  /**< Context identifier. */
    } __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
    uint64_t value;
    struct {
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
#if defined (US)
        unsigned : 6;       /**< Ignored. */
        unsigned type : 1;  /**< The type of demap operation. */
#elif defined (US3)
        unsigned : 5;       /**< Ignored. */
        unsigned type: 2;   /**< The type of demap operation. */
#endif
        unsigned context : 2;   /**< Context register selection. */
        unsigned : 4;       /**< Zero. */
    } __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
    uint64_t value;
    struct {
#if defined (US)
        unsigned long : 40; /**< Implementation dependent. */
        unsigned asi : 8;   /**< ASI. */
        unsigned : 2;
        unsigned ft : 7;    /**< Fault type. */
#elif defined (US3)
        unsigned long : 39; /**< Implementation dependent. */
        unsigned nf : 1;    /**< Non-faulting load. */
        unsigned asi : 8;   /**< ASI. */
        unsigned tm : 1;    /**< I-TLB miss. */
        unsigned : 3;       /**< Reserved. */
        unsigned ft : 5;    /**< Fault type. */
#endif
        unsigned e : 1;     /**< Side-effect bit. */
        unsigned ct : 2;    /**< Context Register selection. */
        unsigned pr : 1;    /**< Privilege bit. */
        unsigned w : 1;     /**< Write bit. */
        unsigned ow : 1;    /**< Overwrite bit. */
        unsigned fv : 1;    /**< Fault Valid bit. */
    } __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
 * Functions for determining the number of entries in TLBs. They either return
 * a constant value or a value based on the CPU autodetection.
 */
 
/**
 * Determine the number od entries in the DMMU's small TLB.
 */
static inline uint16_t tlb_dsmall_size(void)
{
    return 16;
}
 
/**
 * Determine the number od entries in each DMMU's big TLB.
 */
static inline uint16_t tlb_dbig_size(void)
{
    return 512;
}
 
/**
 * Determine the number od entries in the IMMU's small TLB.
 */
static inline uint16_t tlb_ismall_size(void)
{
    return 16;
}
 
/**
 * Determine the number od entries in the IMMU's big TLB.
 */
static inline uint16_t tlb_ibig_size(void)
{
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
        return 512;
    else
        return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
 *
 * @return Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified IMMU TLB Data Access Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 *
 * @param entry TLB Entry index.
 * @param value Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified DMMU TLB Data Access Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param entry TLB Entry index.
 * @param value Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
 *
 * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry TLB Entry index.
 *
 * @return Current value of specified IMMU TLB Data Access Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry TLB Entry index.
 * @param value Value to be written.
 */
static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
 * @param entry TLB Entry index.
 *
 * @return Current value of specified DMMU TLB Data Access Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry TLB Entry index.
 * @param value Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_number = tlb;
    reg.local_tlb_entry = entry;
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry TLB Entry index.
 *
 * @return Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
    itlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry TLB Entry index.
 *
 * @return Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
    dtlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_number = tlb;
    tag.local_tlb_entry = entry;
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
 
 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 * @param type
 *  Selects between context and page demap
 *  (and entire MMU demap on US-III).
 * @param context_encoding Specifies which Context register has Context ID for
 *  demap.
 * @param page Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
                             * address within the
                             * ASI */
    flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
 *
 * @param type
 *  Selects between context and page demap
 *  (and entire MMU demap on US-III).
 * @param context_encoding Specifies which Context register has Context ID for
 *   demap.
 * @param page Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;
    pg.address = page;
   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
                             * address within the
                             * ASI */
    membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
 
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 
extern void dump_sfsr_and_sfar(void);
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
 */
 

Rev 3493	Rev 3591
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_TLB_H_	35	#ifndef KERN_sparc64_TLB_H_
36	#define KERN_sparc64_TLB_H_	36	#define KERN_sparc64_TLB_H_
37		37
38	#if defined (US)	38	#if defined (US)
39	#define ITLB_ENTRY_COUNT 64	39	#define ITLB_ENTRY_COUNT 64
40	#define DTLB_ENTRY_COUNT 64	40	#define DTLB_ENTRY_COUNT 64
41	#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT	41	#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
42	#endif	42	#endif
43		43
44	/** DT16 is the only of the three DMMUs that can hold locked entries. */	44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
45	#if defined (US3)	45	#if defined (US3)
46	#define DTLB_MAX_LOCKED_ENTRIES 16	46	#define DTLB_MAX_LOCKED_ENTRIES 16
47	#endif	47	#endif
48		48
49	#define MEM_CONTEXT_KERNEL 0	49	#define MEM_CONTEXT_KERNEL 0
50	#define MEM_CONTEXT_TEMP 1	50	#define MEM_CONTEXT_TEMP 1
51		51
52	/** Page sizes. */	52	/** Page sizes. */
53	#define PAGESIZE_8K 0	53	#define PAGESIZE_8K 0
54	#define PAGESIZE_64K 1	54	#define PAGESIZE_64K 1
55	#define PAGESIZE_512K 2	55	#define PAGESIZE_512K 2
56	#define PAGESIZE_4M 3	56	#define PAGESIZE_4M 3
57		57
58	/** Bit width of the TLB-locked portion of kernel address space. */	58	/** Bit width of the TLB-locked portion of kernel address space. */
59	#define KERNEL_PAGE_WIDTH 22 /* 4M */	59	#define KERNEL_PAGE_WIDTH 22 /* 4M */
60		60
61	/* TLB Demap Operation types. */	61	/* TLB Demap Operation types. */
62	#define TLB_DEMAP_PAGE 0	62	#define TLB_DEMAP_PAGE 0
63	#define TLB_DEMAP_CONTEXT 1	63	#define TLB_DEMAP_CONTEXT 1
64	#if defined (US3)	64	#if defined (US3)
65	#define TLB_DEMAP_ALL 2	65	#define TLB_DEMAP_ALL 2
66	#endif	66	#endif
67		67
68	#define TLB_DEMAP_TYPE_SHIFT 6	68	#define TLB_DEMAP_TYPE_SHIFT 6
69		69
70	/* TLB Demap Operation Context register encodings. */	70	/* TLB Demap Operation Context register encodings. */
71	#define TLB_DEMAP_PRIMARY 0	71	#define TLB_DEMAP_PRIMARY 0
72	#define TLB_DEMAP_SECONDARY 1	72	#define TLB_DEMAP_SECONDARY 1
73	#define TLB_DEMAP_NUCLEUS 2	73	#define TLB_DEMAP_NUCLEUS 2
74		74
75	/* There are more TLBs in one MMU in US3, their codes are defined here. */	75	/* There are more TLBs in one MMU in US3, their codes are defined here. */
76	#if defined (US3)	76	#if defined (US3)
77	/* D-MMU: one 16-entry TLB and two 512-entry TLBs */	77	/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
78	#define TLB_DT16 0	78	#define TLB_DSMALL 0
79	#define TLB_DT512_0 2	79	#define TLB_DBIG_0 2
80	#define TLB_DT512_1 3	80	#define TLB_DBIG_1 3
81		81
82	/* I-MMU: one 16-entry TLB and one 128-entry TLB */	82	/* I-MMU: one small (16-entry) TLB and one big TLB */
83	#define TLB_IT16 0	83	#define TLB_ISMALL 0
84	#define TLB_IT128 2	84	#define TLB_IBIG 2
85	#endif	85	#endif
86		86
87	#define TLB_DEMAP_CONTEXT_SHIFT 4	87	#define TLB_DEMAP_CONTEXT_SHIFT 4
88		88
89	/* TLB Tag Access shifts */	89	/* TLB Tag Access shifts */
90	#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0	90	#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0
91	#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)	91	#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
92	#define TLB_TAG_ACCESS_VPN_SHIFT 13	92	#define TLB_TAG_ACCESS_VPN_SHIFT 13
93		93
94	#ifndef __ASM__	94	#ifndef __ASM__
95		95
96	#include <arch/mm/tte.h>	96	#include <arch/mm/tte.h>
97	#include <arch/mm/mmu.h>	97	#include <arch/mm/mmu.h>
98	#include <arch/mm/page.h>	98	#include <arch/mm/page.h>
99	#include <arch/asm.h>	99	#include <arch/asm.h>
100	#include <arch/barrier.h>	100	#include <arch/barrier.h>
101	#include <arch/types.h>	101	#include <arch/types.h>
-		102	#include <arch/register.h>
-		103	#include <arch/cpu.h>
102		104
103	union tlb_context_reg {	105	union tlb_context_reg {
104	uint64_t v;	106	uint64_t v;
105	struct {	107	struct {
106	unsigned long : 51;	108	unsigned long : 51;
107	unsigned context : 13; /*< Context/ASID. /	109	unsigned context : 13; /*< Context/ASID. /
108	} __attribute__ ((packed));	110	} __attribute__ ((packed));
109	};	111	};
110	typedef union tlb_context_reg tlb_context_reg_t;	112	typedef union tlb_context_reg tlb_context_reg_t;
111		113
112	/** I-/D-TLB Data In/Access Register type. */	114	/** I-/D-TLB Data In/Access Register type. */
113	typedef tte_data_t tlb_data_t;	115	typedef tte_data_t tlb_data_t;
114		116
115	/** I-/D-TLB Data Access Address in Alternate Space. */	117	/** I-/D-TLB Data Access Address in Alternate Space. */
116		118
117	#if defined (US)	119	#if defined (US)
118		120
119	union tlb_data_access_addr {	121	union tlb_data_access_addr {
120	uint64_t value;	122	uint64_t value;
121	struct {	123	struct {
122	uint64_t : 55;	124	uint64_t : 55;
123	unsigned tlb_entry : 6;	125	unsigned tlb_entry : 6;
124	unsigned : 3;	126	unsigned : 3;
125	} __attribute__ ((packed));	127	} __attribute__ ((packed));
126	};	128	};
127	typedef union tlb_data_access_addr dtlb_data_access_addr_t;	129	typedef union tlb_data_access_addr dtlb_data_access_addr_t;
128	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;	130	typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
129	typedef union tlb_data_access_addr itlb_data_access_addr_t;	131	typedef union tlb_data_access_addr itlb_data_access_addr_t;
130	typedef union tlb_data_access_addr itlb_tag_read_addr_t;	132	typedef union tlb_data_access_addr itlb_tag_read_addr_t;
131		133
132	#elif defined (US3)	134	#elif defined (US3)
133		135
134	/*	136	/*
135	* In US3, I-MMU and D-MMU have different formats of the data	137	* In US3, I-MMU and D-MMU have different formats of the data
136	* access register virtual address. In the corresponding	138	* access register virtual address. In the corresponding
137	* structures the member variable for the entry number is	139	* structures the member variable for the entry number is
138	* called "local_tlb_entry" - it contrast with the "tlb_entry"	140	* called "local_tlb_entry" - it contrast with the "tlb_entry"
139	* for the US data access register VA structure. The rationale	141	* for the US data access register VA structure. The rationale
140	* behind this is to prevent careless mistakes in the code	142	* behind this is to prevent careless mistakes in the code
141	* caused by setting only the entry number and not the TLB	143	* caused by setting only the entry number and not the TLB
142	* number in the US3 code (when taking the code from US).	144	* number in the US3 code (when taking the code from US).
143	*/	145	*/
144		146
145	union dtlb_data_access_addr {	147	union dtlb_data_access_addr {
146	uint64_t value;	148	uint64_t value;
147	struct {	149	struct {
148	uint64_t : 45;	150	uint64_t : 45;
149	unsigned : 1;	151	unsigned : 1;
150	unsigned tlb_number : 2;	152	unsigned tlb_number : 2;
151	unsigned : 4;	153	unsigned : 4;
152	unsigned local_tlb_entry : 9;	154	unsigned local_tlb_entry : 9;
153	unsigned : 3;	155	unsigned : 3;
154	} __attribute__ ((packed));	156	} __attribute__ ((packed));
155	};	157	};
156	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;	158	typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
157	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;	159	typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
158		160
159	union itlb_data_access_addr {	161	union itlb_data_access_addr {
160	uint64_t value;	162	uint64_t value;
161	struct {	163	struct {
162	uint64_t : 45;	164	uint64_t : 45;
163	unsigned : 1;	165	unsigned : 1;
164	unsigned tlb_number : 2;	166	unsigned tlb_number : 2;
165	unsigned : 6;	167	unsigned : 6;
166	unsigned local_tlb_entry : 7;	168	unsigned local_tlb_entry : 7;
167	unsigned : 3;	169	unsigned : 3;
168	} __attribute__ ((packed));	170	} __attribute__ ((packed));
169	};	171	};
170	typedef union itlb_data_access_addr itlb_data_access_addr_t;	172	typedef union itlb_data_access_addr itlb_data_access_addr_t;
171	typedef union itlb_data_access_addr itlb_tag_read_addr_t;	173	typedef union itlb_data_access_addr itlb_tag_read_addr_t;
172		174
173	#endif	175	#endif
174		176
175	/** I-/D-TLB Tag Read Register. */	177	/** I-/D-TLB Tag Read Register. */
176	union tlb_tag_read_reg {	178	union tlb_tag_read_reg {
177	// TODO have a look at how non-8kB pages will be treated	179	// TODO have a look at how non-8kB pages will be treated
178	uint64_t value;	180	uint64_t value;
179	struct {	181	struct {
180	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /	182	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /
181	unsigned context : 13; /*< Context identifier. /	183	unsigned context : 13; /*< Context identifier. /
182	} __attribute__ ((packed));	184	} __attribute__ ((packed));
183	};	185	};
184	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;	186	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
185	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;	187	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
186		188
187		189
188	/** TLB Demap Operation Address. */	190	/** TLB Demap Operation Address. */
189	union tlb_demap_addr {	191	union tlb_demap_addr {
190	uint64_t value;	192	uint64_t value;
191	struct {	193	struct {
192	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /	194	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /
193	#if defined (US)	195	#if defined (US)
194	unsigned : 6; /*< Ignored. /	196	unsigned : 6; /*< Ignored. /
195	unsigned type : 1; /*< The type of demap operation. /	197	unsigned type : 1; /*< The type of demap operation. /
196	#elif defined (US3)	198	#elif defined (US3)
197	unsigned : 5; /*< Ignored. /	199	unsigned : 5; /*< Ignored. /
198	unsigned type: 2; /*< The type of demap operation. /	200	unsigned type: 2; /*< The type of demap operation. /
199	#endif	201	#endif
200	unsigned context : 2; /*< Context register selection. /	202	unsigned context : 2; /*< Context register selection. /
201	unsigned : 4; /*< Zero. /	203	unsigned : 4; /*< Zero. /
202	} __attribute__ ((packed));	204	} __attribute__ ((packed));
203	};	205	};
204	typedef union tlb_demap_addr tlb_demap_addr_t;	206	typedef union tlb_demap_addr tlb_demap_addr_t;
205		207
206	/** TLB Synchronous Fault Status Register. */	208	/** TLB Synchronous Fault Status Register. */
207	union tlb_sfsr_reg {	209	union tlb_sfsr_reg {
208	uint64_t value;	210	uint64_t value;
209	struct {	211	struct {
210	#if defined (US)	212	#if defined (US)
211	unsigned long : 40; /*< Implementation dependent. /	213	unsigned long : 40; /*< Implementation dependent. /
212	unsigned asi : 8; /*< ASI. /	214	unsigned asi : 8; /*< ASI. /
213	unsigned : 2;	215	unsigned : 2;
214	unsigned ft : 7; /*< Fault type. /	216	unsigned ft : 7; /*< Fault type. /
215	#elif defined (US3)	217	#elif defined (US3)
216	unsigned long : 39; /*< Implementation dependent. /	218	unsigned long : 39; /*< Implementation dependent. /
217	unsigned nf : 1; /*< Non-faulting load. /	219	unsigned nf : 1; /*< Non-faulting load. /
218	unsigned asi : 8; /*< ASI. /	220	unsigned asi : 8; /*< ASI. /
219	unsigned tm : 1; /*< I-TLB miss. /	221	unsigned tm : 1; /*< I-TLB miss. /
220	unsigned : 3; /*< Reserved. /	222	unsigned : 3; /*< Reserved. /
221	unsigned ft : 5; /*< Fault type. /	223	unsigned ft : 5; /*< Fault type. /
222	#endif	224	#endif
223	unsigned e : 1; /*< Side-effect bit. /	225	unsigned e : 1; /*< Side-effect bit. /
224	unsigned ct : 2; /*< Context Register selection. /	226	unsigned ct : 2; /*< Context Register selection. /
225	unsigned pr : 1; /*< Privilege bit. /	227	unsigned pr : 1; /*< Privilege bit. /
226	unsigned w : 1; /*< Write bit. /	228	unsigned w : 1; /*< Write bit. /
227	unsigned ow : 1; /*< Overwrite bit. /	229	unsigned ow : 1; /*< Overwrite bit. /
228	unsigned fv : 1; /*< Fault Valid bit. /	230	unsigned fv : 1; /*< Fault Valid bit. /
229	} __attribute__ ((packed));	231	} __attribute__ ((packed));
230	};	232	};
231	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;	233	typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
232		234
-		235	#if defined (US3)
-		236
-		237	/*
-		238	* Functions for determining the number of entries in TLBs. They either return
-		239	* a constant value or a value based on the CPU autodetection.
-		240	*/
-		241
-		242	/**
-		243	* Determine the number od entries in the DMMU's small TLB.
-		244	*/
-		245	static inline uint16_t tlb_dsmall_size(void)
-		246	{
-		247	return 16;
-		248	}
-		249
-		250	/**
-		251	* Determine the number od entries in each DMMU's big TLB.
-		252	*/
-		253	static inline uint16_t tlb_dbig_size(void)
-		254	{
-		255	return 512;
-		256	}
-		257
-		258	/**
-		259	* Determine the number od entries in the IMMU's small TLB.
-		260	*/
-		261	static inline uint16_t tlb_ismall_size(void)
-		262	{
-		263	return 16;
-		264	}
-		265
-		266	/**
-		267	* Determine the number od entries in the IMMU's big TLB.
-		268	*/
-		269	static inline uint16_t tlb_ibig_size(void)
-		270	{
-		271	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
-		272	return 512;
-		273	else
-		274	return 128;
-		275	}
-		276
-		277	#endif
-		278
233	/** Read MMU Primary Context Register.	279	/** Read MMU Primary Context Register.
234	*	280	*
235	* @return Current value of Primary Context Register.	281	* @return Current value of Primary Context Register.
236	*/	282	*/
237	static inline uint64_t mmu_primary_context_read(void)	283	static inline uint64_t mmu_primary_context_read(void)
238	{	284	{
239	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);	285	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
240	}	286	}
241		287
242	/** Write MMU Primary Context Register.	288	/** Write MMU Primary Context Register.
243	*	289	*
244	* @param v New value of Primary Context Register.	290	* @param v New value of Primary Context Register.
245	*/	291	*/
246	static inline void mmu_primary_context_write(uint64_t v)	292	static inline void mmu_primary_context_write(uint64_t v)
247	{	293	{
248	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	294	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
249	flush_pipeline();	295	flush_pipeline();
250	}	296	}
251		297
252	/** Read MMU Secondary Context Register.	298	/** Read MMU Secondary Context Register.
253	*	299	*
254	* @return Current value of Secondary Context Register.	300	* @return Current value of Secondary Context Register.
255	*/	301	*/
256	static inline uint64_t mmu_secondary_context_read(void)	302	static inline uint64_t mmu_secondary_context_read(void)
257	{	303	{
258	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);	304	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
259	}	305	}
260		306
261	/** Write MMU Primary Context Register.	307	/** Write MMU Primary Context Register.
262	*	308	*
263	* @param v New value of Primary Context Register.	309	* @param v New value of Primary Context Register.
264	*/	310	*/
265	static inline void mmu_secondary_context_write(uint64_t v)	311	static inline void mmu_secondary_context_write(uint64_t v)
266	{	312	{
267	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);	313	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
268	flush_pipeline();	314	flush_pipeline();
269	}	315	}
270		316
271	#if defined (US)	317	#if defined (US)
272		318
273	/** Read IMMU TLB Data Access Register.	319	/** Read IMMU TLB Data Access Register.
274	*	320	*
275	* @param entry TLB Entry index.	321	* @param entry TLB Entry index.
276	*	322	*
277	* @return Current value of specified IMMU TLB Data Access Register.	323	* @return Current value of specified IMMU TLB Data Access Register.
278	*/	324	*/
279	static inline uint64_t itlb_data_access_read(index_t entry)	325	static inline uint64_t itlb_data_access_read(index_t entry)
280	{	326	{
281	itlb_data_access_addr_t reg;	327	itlb_data_access_addr_t reg;
282		328
283	reg.value = 0;	329	reg.value = 0;
284	reg.tlb_entry = entry;	330	reg.tlb_entry = entry;
285	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	331	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
286	}	332	}
287		333
288	/** Write IMMU TLB Data Access Register.	334	/** Write IMMU TLB Data Access Register.
289	*	335	*
290	* @param entry TLB Entry index.	336	* @param entry TLB Entry index.
291	* @param value Value to be written.	337	* @param value Value to be written.
292	*/	338	*/
293	static inline void itlb_data_access_write(index_t entry, uint64_t value)	339	static inline void itlb_data_access_write(index_t entry, uint64_t value)
294	{	340	{
295	itlb_data_access_addr_t reg;	341	itlb_data_access_addr_t reg;
296		342
297	reg.value = 0;	343	reg.value = 0;
298	reg.tlb_entry = entry;	344	reg.tlb_entry = entry;
299	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	345	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
300	flush_pipeline();	346	flush_pipeline();
301	}	347	}
302		348
303	/** Read DMMU TLB Data Access Register.	349	/** Read DMMU TLB Data Access Register.
304	*	350	*
305	* @param entry TLB Entry index.	351	* @param entry TLB Entry index.
306	*	352	*
307	* @return Current value of specified DMMU TLB Data Access Register.	353	* @return Current value of specified DMMU TLB Data Access Register.
308	*/	354	*/
309	static inline uint64_t dtlb_data_access_read(index_t entry)	355	static inline uint64_t dtlb_data_access_read(index_t entry)
310	{	356	{
311	dtlb_data_access_addr_t reg;	357	dtlb_data_access_addr_t reg;
312		358
313	reg.value = 0;	359	reg.value = 0;
314	reg.tlb_entry = entry;	360	reg.tlb_entry = entry;
315	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	361	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
316	}	362	}
317		363
318	/** Write DMMU TLB Data Access Register.	364	/** Write DMMU TLB Data Access Register.
319	*	365	*
320	* @param entry TLB Entry index.	366	* @param entry TLB Entry index.
321	* @param value Value to be written.	367	* @param value Value to be written.
322	*/	368	*/
323	static inline void dtlb_data_access_write(index_t entry, uint64_t value)	369	static inline void dtlb_data_access_write(index_t entry, uint64_t value)
324	{	370	{
325	dtlb_data_access_addr_t reg;	371	dtlb_data_access_addr_t reg;
326		372
327	reg.value = 0;	373	reg.value = 0;
328	reg.tlb_entry = entry;	374	reg.tlb_entry = entry;
329	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	375	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
330	membar();	376	membar();
331	}	377	}
332		378
333	/** Read IMMU TLB Tag Read Register.	379	/** Read IMMU TLB Tag Read Register.
334	*	380	*
335	* @param entry TLB Entry index.	381	* @param entry TLB Entry index.
336	*	382	*
337	* @return Current value of specified IMMU TLB Tag Read Register.	383	* @return Current value of specified IMMU TLB Tag Read Register.
338	*/	384	*/
339	static inline uint64_t itlb_tag_read_read(index_t entry)	385	static inline uint64_t itlb_tag_read_read(index_t entry)
340	{	386	{
341	itlb_tag_read_addr_t tag;	387	itlb_tag_read_addr_t tag;
342		388
343	tag.value = 0;	389	tag.value = 0;
344	tag.tlb_entry = entry;	390	tag.tlb_entry = entry;
345	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	391	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
346	}	392	}
347		393
348	/** Read DMMU TLB Tag Read Register.	394	/** Read DMMU TLB Tag Read Register.
349	*	395	*
350	* @param entry TLB Entry index.	396	* @param entry TLB Entry index.
351	*	397	*
352	* @return Current value of specified DMMU TLB Tag Read Register.	398	* @return Current value of specified DMMU TLB Tag Read Register.
353	*/	399	*/
354	static inline uint64_t dtlb_tag_read_read(index_t entry)	400	static inline uint64_t dtlb_tag_read_read(index_t entry)
355	{	401	{
356	dtlb_tag_read_addr_t tag;	402	dtlb_tag_read_addr_t tag;
357		403
358	tag.value = 0;	404	tag.value = 0;
359	tag.tlb_entry = entry;	405	tag.tlb_entry = entry;
360	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);	406	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
361	}	407	}
362		408
363	#elif defined (US3)	409	#elif defined (US3)
364		410
365		411
366	/** Read IMMU TLB Data Access Register.	412	/** Read IMMU TLB Data Access Register.
367	*	413	*
368	* @param tlb TLB number (one of TLB_IT16 or TLB_IT128)	414	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
369	* @param entry TLB Entry index.	415	* @param entry TLB Entry index.
370	*	416	*
371	* @return Current value of specified IMMU TLB Data Access Register.	417	* @return Current value of specified IMMU TLB Data Access Register.
372	*/	418	*/
373	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)	419	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
374	{	420	{
375	itlb_data_access_addr_t reg;	421	itlb_data_access_addr_t reg;
376		422
377	reg.value = 0;	423	reg.value = 0;
378	reg.tlb_number = tlb;	424	reg.tlb_number = tlb;
379	reg.local_tlb_entry = entry;	425	reg.local_tlb_entry = entry;
380	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	426	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
381	}	427	}
382		428
383	/** Write IMMU TLB Data Access Register.	429	/** Write IMMU TLB Data Access Register.
384	* @param tlb TLB number (one of TLB_IT16 or TLB_IT128)	430	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
385	* @param entry TLB Entry index.	431	* @param entry TLB Entry index.
386	* @param value Value to be written.	432	* @param value Value to be written.
387	*/	433	*/
388	static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value)	434	static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value)
389	{	435	{
390	itlb_data_access_addr_t reg;	436	itlb_data_access_addr_t reg;
391		437
392	reg.value = 0;	438	reg.value = 0;
393	reg.tlb_number = tlb;	439	reg.tlb_number = tlb;
394	reg.local_tlb_entry = entry;	440	reg.local_tlb_entry = entry;
395	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);	441	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
396	flush_pipeline();	442	flush_pipeline();
397	}	443	}
398		444
399	/** Read DMMU TLB Data Access Register.	445	/** Read DMMU TLB Data Access Register.
400	*	446	*
401	* @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)	447	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
402	* @param entry TLB Entry index.	448	* @param entry TLB Entry index.
403	*	449	*
404	* @return Current value of specified DMMU TLB Data Access Register.	450	* @return Current value of specified DMMU TLB Data Access Register.
405	*/	451	*/
406	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)	452	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
407	{	453	{
408	dtlb_data_access_addr_t reg;	454	dtlb_data_access_addr_t reg;
409		455
410	reg.value = 0;	456	reg.value = 0;
411	reg.tlb_number = tlb;	457	reg.tlb_number = tlb;
412	reg.local_tlb_entry = entry;	458	reg.local_tlb_entry = entry;
413	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	459	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
414	}	460	}
415		461
416	/** Write DMMU TLB Data Access Register.	462	/** Write DMMU TLB Data Access Register.
417	*	463	*
418	* @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)	464	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
419	* @param entry TLB Entry index.	465	* @param entry TLB Entry index.
420	* @param value Value to be written.	466	* @param value Value to be written.
421	*/	467	*/
422	static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value)	468	static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value)
423	{	469	{
424	dtlb_data_access_addr_t reg;	470	dtlb_data_access_addr_t reg;
425		471
426	reg.value = 0;	472	reg.value = 0;
427	reg.tlb_number = tlb;	473	reg.tlb_number = tlb;
428	reg.local_tlb_entry = entry;	474	reg.local_tlb_entry = entry;
429	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);	475	asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
430	membar();	476	membar();
431	}	477	}
432		478
433	/** Read IMMU TLB Tag Read Register.	479	/** Read IMMU TLB Tag Read Register.
434	*	480	*
435	* @param tlb TLB number (one of TLB_IT16 or TLB_IT128)	481	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
436	* @param entry TLB Entry index.	482	* @param entry TLB Entry index.
437	*	483	*
438	* @return Current value of specified IMMU TLB Tag Read Register.	484	* @return Current value of specified IMMU TLB Tag Read Register.
439	*/	485	*/
440	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)	486	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
441	{	487	{
442	itlb_tag_read_addr_t tag;	488	itlb_tag_read_addr_t tag;
443		489
444	tag.value = 0;	490	tag.value = 0;
445	tag.tlb_number = tlb;	491	tag.tlb_number = tlb;
446	tag.local_tlb_entry = entry;	492	tag.local_tlb_entry = entry;
447	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	493	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
448	}	494	}
449		495
450	/** Read DMMU TLB Tag Read Register.	496	/** Read DMMU TLB Tag Read Register.
451	*	497	*
452	* @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)	498	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
453	* @param entry TLB Entry index.	499	* @param entry TLB Entry index.
454	*	500	*

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(root)/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h – Rev 3493 → 3591