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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_TLB_H_ |
35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
37 | 37 | ||
38 | #define ITLB_ENTRY_COUNT 64 |
38 | #define ITLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
40 | 40 | ||
41 | #define MEM_CONTEXT_KERNEL 0 |
41 | #define MEM_CONTEXT_KERNEL 0 |
42 | #define MEM_CONTEXT_TEMP 1 |
42 | #define MEM_CONTEXT_TEMP 1 |
43 | 43 | ||
44 | /** Page sizes. */ |
44 | /** Page sizes. */ |
45 | #define PAGESIZE_8K 0 |
45 | #define PAGESIZE_8K 0 |
46 | #define PAGESIZE_64K 1 |
46 | #define PAGESIZE_64K 1 |
47 | #define PAGESIZE_512K 2 |
47 | #define PAGESIZE_512K 2 |
48 | #define PAGESIZE_4M 3 |
48 | #define PAGESIZE_4M 3 |
49 | 49 | ||
50 | /** Bit width of the TLB-locked portion of kernel address space. */ |
50 | /** Bit width of the TLB-locked portion of kernel address space. */ |
51 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
51 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
52 | 52 | ||
53 | /* TLB Demap Operation types. */ |
53 | /* TLB Demap Operation types. */ |
54 | #define TLB_DEMAP_PAGE 0 |
54 | #define TLB_DEMAP_PAGE 0 |
55 | #define TLB_DEMAP_CONTEXT 1 |
55 | #define TLB_DEMAP_CONTEXT 1 |
56 | 56 | ||
57 | #define TLB_DEMAP_TYPE_SHIFT 6 |
57 | #define TLB_DEMAP_TYPE_SHIFT 6 |
58 | 58 | ||
59 | /* TLB Demap Operation Context register encodings. */ |
59 | /* TLB Demap Operation Context register encodings. */ |
60 | #define TLB_DEMAP_PRIMARY 0 |
60 | #define TLB_DEMAP_PRIMARY 0 |
61 | #define TLB_DEMAP_SECONDARY 1 |
61 | #define TLB_DEMAP_SECONDARY 1 |
62 | #define TLB_DEMAP_NUCLEUS 2 |
62 | #define TLB_DEMAP_NUCLEUS 2 |
63 | 63 | ||
- | 64 | /* there are more TLBs in one MMU in US3, their codes are defined here */ |
|
- | 65 | #if defined (US3) |
|
- | 66 | /* D-MMU: one 16-entry TLB and two 512-entry TLBs */ |
|
- | 67 | #define TLB_DT16 0 |
|
- | 68 | #define TLB_DT512_1 2 |
|
- | 69 | #define TLB_DT512_2 3 |
|
- | 70 | ||
- | 71 | /* I-MMU: one 16-entry TLB and one 128-entry TLB */ |
|
- | 72 | #define TLB_IT16 0 |
|
- | 73 | #define TLB_IT128 2 |
|
- | 74 | #endif |
|
- | 75 | ||
64 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
76 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
65 | 77 | ||
66 | /* TLB Tag Access shifts */ |
78 | /* TLB Tag Access shifts */ |
67 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
79 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
68 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
80 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
69 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
81 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
70 | 82 | ||
71 | #ifndef __ASM__ |
83 | #ifndef __ASM__ |
72 | 84 | ||
73 | #include <arch/mm/tte.h> |
85 | #include <arch/mm/tte.h> |
74 | #include <arch/mm/mmu.h> |
86 | #include <arch/mm/mmu.h> |
75 | #include <arch/mm/page.h> |
87 | #include <arch/mm/page.h> |
76 | #include <arch/asm.h> |
88 | #include <arch/asm.h> |
77 | #include <arch/barrier.h> |
89 | #include <arch/barrier.h> |
78 | #include <arch/types.h> |
90 | #include <arch/types.h> |
79 | 91 | ||
80 | union tlb_context_reg { |
92 | union tlb_context_reg { |
81 | uint64_t v; |
93 | uint64_t v; |
82 | struct { |
94 | struct { |
83 | unsigned long : 51; |
95 | unsigned long : 51; |
84 | unsigned context : 13; /**< Context/ASID. */ |
96 | unsigned context : 13; /**< Context/ASID. */ |
85 | } __attribute__ ((packed)); |
97 | } __attribute__ ((packed)); |
86 | }; |
98 | }; |
87 | typedef union tlb_context_reg tlb_context_reg_t; |
99 | typedef union tlb_context_reg tlb_context_reg_t; |
88 | 100 | ||
89 | /** I-/D-TLB Data In/Access Register type. */ |
101 | /** I-/D-TLB Data In/Access Register type. */ |
90 | typedef tte_data_t tlb_data_t; |
102 | typedef tte_data_t tlb_data_t; |
91 | 103 | ||
92 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
104 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
- | 105 | ||
- | 106 | #if defined (US) |
|
- | 107 | ||
93 | union tlb_data_access_addr { |
108 | union tlb_data_access_addr { |
94 | uint64_t value; |
109 | uint64_t value; |
95 | struct { |
110 | struct { |
96 | uint64_t : 55; |
111 | uint64_t : 55; |
97 | unsigned tlb_entry : 6; |
112 | unsigned tlb_entry : 6; |
98 | unsigned : 3; |
113 | unsigned : 3; |
99 | } __attribute__ ((packed)); |
114 | } __attribute__ ((packed)); |
100 | }; |
115 | }; |
101 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
116 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
- | 117 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
|
- | 118 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
|
102 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
119 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
- | 120 | ||
- | 121 | #elif defined (US3) |
|
- | 122 | ||
- | 123 | /* |
|
- | 124 | * In US3, I-MMU and D-MMU have different formats of the data |
|
- | 125 | * access register virtual address. In the corresponding |
|
- | 126 | * structures the member variable for the entry number is |
|
- | 127 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
|
- | 128 | * for the US data access register VA structure. The rationale |
|
- | 129 | * behind this is to prevent careless mistakes in the code |
|
- | 130 | * caused by setting only the entry number and not the TLB |
|
- | 131 | * number in the US3 code (when taking the code from US). |
|
- | 132 | */ |
|
- | 133 | ||
- | 134 | union dtlb_data_access_addr { |
|
- | 135 | uint64_t value; |
|
- | 136 | struct { |
|
- | 137 | uint64_t : 45; |
|
- | 138 | unsigned : 1; |
|
- | 139 | unsigned tlb_number : 2; |
|
- | 140 | unsigned : 4; |
|
- | 141 | unsigned local_tlb_entry : 9; |
|
- | 142 | unsigned : 3; |
|
- | 143 | } __attribute__ ((packed)); |
|
- | 144 | }; |
|
- | 145 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
|
- | 146 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
|
- | 147 | ||
- | 148 | union itlb_data_access_addr { |
|
- | 149 | uint64_t value; |
|
- | 150 | struct { |
|
- | 151 | uint64_t : 45; |
|
- | 152 | unsigned : 1; |
|
- | 153 | unsigned tlb_number : 2; |
|
- | 154 | unsigned : 6; |
|
- | 155 | unsigned local_tlb_entry : 7; |
|
- | 156 | unsigned : 3; |
|
- | 157 | } __attribute__ ((packed)); |
|
- | 158 | }; |
|
- | 159 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
|
- | 160 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
|
- | 161 | ||
- | 162 | #endif |
|
103 | 163 | ||
104 | /** I-/D-TLB Tag Read Register. */ |
164 | /** I-/D-TLB Tag Read Register. */ |
105 | union tlb_tag_read_reg { |
165 | union tlb_tag_read_reg { |
106 | uint64_t value; |
166 | uint64_t value; |
107 | struct { |
167 | struct { |
108 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
168 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
109 | unsigned context : 13; /**< Context identifier. */ |
169 | unsigned context : 13; /**< Context identifier. */ |
110 | } __attribute__ ((packed)); |
170 | } __attribute__ ((packed)); |
111 | }; |
171 | }; |
112 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
172 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
113 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
173 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
114 | 174 | ||
115 | 175 | ||
116 | /** TLB Demap Operation Address. */ |
176 | /** TLB Demap Operation Address. */ |
117 | union tlb_demap_addr { |
177 | union tlb_demap_addr { |
118 | uint64_t value; |
178 | uint64_t value; |
119 | struct { |
179 | struct { |
120 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
180 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
121 | unsigned : 6; /**< Ignored. */ |
181 | unsigned : 6; /**< Ignored. */ |
122 | unsigned type : 1; /**< The type of demap operation. */ |
182 | unsigned type : 1; /**< The type of demap operation. */ |
123 | unsigned context : 2; /**< Context register selection. */ |
183 | unsigned context : 2; /**< Context register selection. */ |
124 | unsigned : 4; /**< Zero. */ |
184 | unsigned : 4; /**< Zero. */ |
125 | } __attribute__ ((packed)); |
185 | } __attribute__ ((packed)); |
126 | }; |
186 | }; |
127 | typedef union tlb_demap_addr tlb_demap_addr_t; |
187 | typedef union tlb_demap_addr tlb_demap_addr_t; |
128 | 188 | ||
129 | /** TLB Synchronous Fault Status Register. */ |
189 | /** TLB Synchronous Fault Status Register. */ |
130 | union tlb_sfsr_reg { |
190 | union tlb_sfsr_reg { |
131 | uint64_t value; |
191 | uint64_t value; |
132 | struct { |
192 | struct { |
133 | unsigned long : 40; /**< Implementation dependent. */ |
193 | unsigned long : 40; /**< Implementation dependent. */ |
134 | unsigned asi : 8; /**< ASI. */ |
194 | unsigned asi : 8; /**< ASI. */ |
135 | unsigned : 2; |
195 | unsigned : 2; |
136 | unsigned ft : 7; /**< Fault type. */ |
196 | unsigned ft : 7; /**< Fault type. */ |
137 | unsigned e : 1; /**< Side-effect bit. */ |
197 | unsigned e : 1; /**< Side-effect bit. */ |
138 | unsigned ct : 2; /**< Context Register selection. */ |
198 | unsigned ct : 2; /**< Context Register selection. */ |
139 | unsigned pr : 1; /**< Privilege bit. */ |
199 | unsigned pr : 1; /**< Privilege bit. */ |
140 | unsigned w : 1; /**< Write bit. */ |
200 | unsigned w : 1; /**< Write bit. */ |
141 | unsigned ow : 1; /**< Overwrite bit. */ |
201 | unsigned ow : 1; /**< Overwrite bit. */ |
142 | unsigned fv : 1; /**< Fault Valid bit. */ |
202 | unsigned fv : 1; /**< Fault Valid bit. */ |
143 | } __attribute__ ((packed)); |
203 | } __attribute__ ((packed)); |
144 | }; |
204 | }; |
145 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
205 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
146 | 206 | ||
147 | /** Read MMU Primary Context Register. |
207 | /** Read MMU Primary Context Register. |
148 | * |
208 | * |
149 | * @return Current value of Primary Context Register. |
209 | * @return Current value of Primary Context Register. |
150 | */ |
210 | */ |
151 | static inline uint64_t mmu_primary_context_read(void) |
211 | static inline uint64_t mmu_primary_context_read(void) |
152 | { |
212 | { |
153 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
213 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
154 | } |
214 | } |
155 | 215 | ||
156 | /** Write MMU Primary Context Register. |
216 | /** Write MMU Primary Context Register. |
157 | * |
217 | * |
158 | * @param v New value of Primary Context Register. |
218 | * @param v New value of Primary Context Register. |
159 | */ |
219 | */ |
160 | static inline void mmu_primary_context_write(uint64_t v) |
220 | static inline void mmu_primary_context_write(uint64_t v) |
161 | { |
221 | { |
162 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
222 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
163 | flush_pipeline(); |
223 | flush_pipeline(); |
164 | } |
224 | } |
165 | 225 | ||
166 | /** Read MMU Secondary Context Register. |
226 | /** Read MMU Secondary Context Register. |
167 | * |
227 | * |
168 | * @return Current value of Secondary Context Register. |
228 | * @return Current value of Secondary Context Register. |
169 | */ |
229 | */ |
170 | static inline uint64_t mmu_secondary_context_read(void) |
230 | static inline uint64_t mmu_secondary_context_read(void) |
171 | { |
231 | { |
172 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
232 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
173 | } |
233 | } |
174 | 234 | ||
175 | /** Write MMU Primary Context Register. |
235 | /** Write MMU Primary Context Register. |
176 | * |
236 | * |
177 | * @param v New value of Primary Context Register. |
237 | * @param v New value of Primary Context Register. |
178 | */ |
238 | */ |
179 | static inline void mmu_secondary_context_write(uint64_t v) |
239 | static inline void mmu_secondary_context_write(uint64_t v) |
180 | { |
240 | { |
181 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
241 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
182 | flush_pipeline(); |
242 | flush_pipeline(); |
183 | } |
243 | } |
184 | 244 | ||
- | 245 | #if defined (US) |
|
- | 246 | ||
185 | /** Read IMMU TLB Data Access Register. |
247 | /** Read IMMU TLB Data Access Register. |
186 | * |
248 | * |
187 | * @param entry TLB Entry index. |
249 | * @param entry TLB Entry index. |
188 | * |
250 | * |
189 | * @return Current value of specified IMMU TLB Data Access Register. |
251 | * @return Current value of specified IMMU TLB Data Access Register. |
190 | */ |
252 | */ |
191 | static inline uint64_t itlb_data_access_read(index_t entry) |
253 | static inline uint64_t itlb_data_access_read(index_t entry) |
192 | { |
254 | { |
193 | tlb_data_access_addr_t reg; |
255 | itlb_data_access_addr_t reg; |
194 | 256 | ||
195 | reg.value = 0; |
257 | reg.value = 0; |
196 | reg.tlb_entry = entry; |
258 | reg.tlb_entry = entry; |
197 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
259 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
198 | } |
260 | } |
199 | 261 | ||
200 | /** Write IMMU TLB Data Access Register. |
262 | /** Write IMMU TLB Data Access Register. |
201 | * |
263 | * |
202 | * @param entry TLB Entry index. |
264 | * @param entry TLB Entry index. |
203 | * @param value Value to be written. |
265 | * @param value Value to be written. |
204 | */ |
266 | */ |
205 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
267 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
206 | { |
268 | { |
207 | tlb_data_access_addr_t reg; |
269 | itlb_data_access_addr_t reg; |
208 | 270 | ||
209 | reg.value = 0; |
271 | reg.value = 0; |
210 | reg.tlb_entry = entry; |
272 | reg.tlb_entry = entry; |
211 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
273 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
212 | flush_pipeline(); |
274 | flush_pipeline(); |
213 | } |
275 | } |
214 | 276 | ||
215 | /** Read DMMU TLB Data Access Register. |
277 | /** Read DMMU TLB Data Access Register. |
216 | * |
278 | * |
217 | * @param entry TLB Entry index. |
279 | * @param entry TLB Entry index. |
218 | * |
280 | * |
219 | * @return Current value of specified DMMU TLB Data Access Register. |
281 | * @return Current value of specified DMMU TLB Data Access Register. |
220 | */ |
282 | */ |
221 | static inline uint64_t dtlb_data_access_read(index_t entry) |
283 | static inline uint64_t dtlb_data_access_read(index_t entry) |
222 | { |
284 | { |
223 | tlb_data_access_addr_t reg; |
285 | dtlb_data_access_addr_t reg; |
224 | 286 | ||
225 | reg.value = 0; |
287 | reg.value = 0; |
226 | reg.tlb_entry = entry; |
288 | reg.tlb_entry = entry; |
227 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
289 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
228 | } |
290 | } |
229 | 291 | ||
230 | /** Write DMMU TLB Data Access Register. |
292 | /** Write DMMU TLB Data Access Register. |
231 | * |
293 | * |
232 | * @param entry TLB Entry index. |
294 | * @param entry TLB Entry index. |
233 | * @param value Value to be written. |
295 | * @param value Value to be written. |
234 | */ |
296 | */ |
235 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
297 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
236 | { |
298 | { |
237 | tlb_data_access_addr_t reg; |
299 | dtlb_data_access_addr_t reg; |
238 | 300 | ||
239 | reg.value = 0; |
301 | reg.value = 0; |
240 | reg.tlb_entry = entry; |
302 | reg.tlb_entry = entry; |
241 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
303 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
242 | membar(); |
304 | membar(); |
243 | } |
305 | } |
244 | 306 | ||
245 | /** Read IMMU TLB Tag Read Register. |
307 | /** Read IMMU TLB Tag Read Register. |
246 | * |
308 | * |
247 | * @param entry TLB Entry index. |
309 | * @param entry TLB Entry index. |
248 | * |
310 | * |
249 | * @return Current value of specified IMMU TLB Tag Read Register. |
311 | * @return Current value of specified IMMU TLB Tag Read Register. |
250 | */ |
312 | */ |
251 | static inline uint64_t itlb_tag_read_read(index_t entry) |
313 | static inline uint64_t itlb_tag_read_read(index_t entry) |
252 | { |
314 | { |
253 | tlb_tag_read_addr_t tag; |
315 | itlb_tag_read_addr_t tag; |
254 | 316 | ||
255 | tag.value = 0; |
317 | tag.value = 0; |
256 | tag.tlb_entry = entry; |
318 | tag.tlb_entry = entry; |
257 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
319 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
258 | } |
320 | } |
259 | 321 | ||
260 | /** Read DMMU TLB Tag Read Register. |
322 | /** Read DMMU TLB Tag Read Register. |
261 | * |
323 | * |
262 | * @param entry TLB Entry index. |
324 | * @param entry TLB Entry index. |
263 | * |
325 | * |
264 | * @return Current value of specified DMMU TLB Tag Read Register. |
326 | * @return Current value of specified DMMU TLB Tag Read Register. |
265 | */ |
327 | */ |
266 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
328 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
267 | { |
329 | { |
268 | tlb_tag_read_addr_t tag; |
330 | dtlb_tag_read_addr_t tag; |
269 | 331 | ||
270 | tag.value = 0; |
332 | tag.value = 0; |
271 | tag.tlb_entry = entry; |
333 | tag.tlb_entry = entry; |
272 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
334 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
273 | } |
335 | } |
274 | 336 | ||
- | 337 | #elif defined (US3) |
|
- | 338 | ||
- | 339 | ||
- | 340 | /** Read IMMU TLB Data Access Register. |
|
- | 341 | * |
|
- | 342 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
|
- | 343 | * @param entry TLB Entry index. |
|
- | 344 | * |
|
- | 345 | * @return Current value of specified IMMU TLB Data Access Register. |
|
- | 346 | */ |
|
- | 347 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
|
- | 348 | { |
|
- | 349 | itlb_data_access_addr_t reg; |
|
- | 350 | ||
- | 351 | reg.value = 0; |
|
- | 352 | reg.tlb_number = tlb; |
|
- | 353 | reg.local_tlb_entry = entry; |
|
- | 354 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
|
- | 355 | } |
|
- | 356 | ||
- | 357 | /** Write IMMU TLB Data Access Register. |
|
- | 358 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
|
- | 359 | * @param entry TLB Entry index. |
|
- | 360 | * @param value Value to be written. |
|
- | 361 | */ |
|
- | 362 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
|
- | 363 | { |
|
- | 364 | itlb_data_access_addr_t reg; |
|
- | 365 | ||
- | 366 | reg.value = 0; |
|
- | 367 | reg.tlb_number = tlb; |
|
- | 368 | reg.local_tlb_entry = entry; |
|
- | 369 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
|
- | 370 | flush_pipeline(); |
|
- | 371 | } |
|
- | 372 | ||
- | 373 | /** Read DMMU TLB Data Access Register. |
|
- | 374 | * |
|
- | 375 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
|
- | 376 | * @param entry TLB Entry index. |
|
- | 377 | * |
|
- | 378 | * @return Current value of specified DMMU TLB Data Access Register. |
|
- | 379 | */ |
|
- | 380 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
|
- | 381 | { |
|
- | 382 | dtlb_data_access_addr_t reg; |
|
- | 383 | ||
- | 384 | reg.value = 0; |
|
- | 385 | reg.tlb_number = tlb; |
|
- | 386 | reg.local_tlb_entry = entry; |
|
- | 387 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
|
- | 388 | } |
|
- | 389 | ||
- | 390 | /** Write DMMU TLB Data Access Register. |
|
- | 391 | * |
|
- | 392 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
|
- | 393 | * @param entry TLB Entry index. |
|
- | 394 | * @param value Value to be written. |
|
- | 395 | */ |
|
- | 396 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
|
- | 397 | { |
|
- | 398 | dtlb_data_access_addr_t reg; |
|
- | 399 | ||
- | 400 | reg.value = 0; |
|
- | 401 | reg.tlb_number = tlb; |
|
- | 402 | reg.local_tlb_entry = entry; |
|
- | 403 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
|
- | 404 | membar(); |
|
- | 405 | } |
|
- | 406 | ||
- | 407 | /** Read IMMU TLB Tag Read Register. |
|
- | 408 | * |
|
- | 409 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
|
- | 410 | * @param entry TLB Entry index. |
|
- | 411 | * |
|
- | 412 | * @return Current value of specified IMMU TLB Tag Read Register. |
|
- | 413 | */ |
|
- | 414 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
|
- | 415 | { |
|
- | 416 | itlb_tag_read_addr_t tag; |
|
- | 417 | ||
- | 418 | tag.value = 0; |
|
- | 419 | tag.tlb_number = tlb; |
|
- | 420 | tag.local_tlb_entry = entry; |
|
- | 421 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
|
- | 422 | } |
|
- | 423 | ||
- | 424 | /** Read DMMU TLB Tag Read Register. |
|
- | 425 | * |
|
- | 426 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
|
- | 427 | * @param entry TLB Entry index. |
|
- | 428 | * |
|
- | 429 | * @return Current value of specified DMMU TLB Tag Read Register. |
|
- | 430 | */ |
|
- | 431 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
|
- | 432 | { |
|
- | 433 | dtlb_tag_read_addr_t tag; |
|
- | 434 | ||
- | 435 | tag.value = 0; |
|
- | 436 | tag.tlb_number = tlb; |
|
- | 437 | tag.local_tlb_entry = entry; |
|
- | 438 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
|
- | 439 | } |
|
- | 440 | ||
- | 441 | #endif |
|
- | 442 | ||
- | 443 | ||
275 | /** Write IMMU TLB Tag Access Register. |
444 | /** Write IMMU TLB Tag Access Register. |
276 | * |
445 | * |
277 | * @param v Value to be written. |
446 | * @param v Value to be written. |
278 | */ |
447 | */ |
279 | static inline void itlb_tag_access_write(uint64_t v) |
448 | static inline void itlb_tag_access_write(uint64_t v) |
280 | { |
449 | { |
281 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
450 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
282 | flush_pipeline(); |
451 | flush_pipeline(); |
283 | } |
452 | } |
284 | 453 | ||
285 | /** Read IMMU TLB Tag Access Register. |
454 | /** Read IMMU TLB Tag Access Register. |
286 | * |
455 | * |
287 | * @return Current value of IMMU TLB Tag Access Register. |
456 | * @return Current value of IMMU TLB Tag Access Register. |
288 | */ |
457 | */ |
289 | static inline uint64_t itlb_tag_access_read(void) |
458 | static inline uint64_t itlb_tag_access_read(void) |
290 | { |
459 | { |
291 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
460 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
292 | } |
461 | } |
293 | 462 | ||
294 | /** Write DMMU TLB Tag Access Register. |
463 | /** Write DMMU TLB Tag Access Register. |
295 | * |
464 | * |
296 | * @param v Value to be written. |
465 | * @param v Value to be written. |
297 | */ |
466 | */ |
298 | static inline void dtlb_tag_access_write(uint64_t v) |
467 | static inline void dtlb_tag_access_write(uint64_t v) |
299 | { |
468 | { |
300 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
469 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
301 | membar(); |
470 | membar(); |
302 | } |
471 | } |
303 | 472 | ||
304 | /** Read DMMU TLB Tag Access Register. |
473 | /** Read DMMU TLB Tag Access Register. |
305 | * |
474 | * |
306 | * @return Current value of DMMU TLB Tag Access Register. |
475 | * @return Current value of DMMU TLB Tag Access Register. |
307 | */ |
476 | */ |
308 | static inline uint64_t dtlb_tag_access_read(void) |
477 | static inline uint64_t dtlb_tag_access_read(void) |
309 | { |
478 | { |
310 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
479 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
311 | } |
480 | } |
312 | 481 | ||
313 | 482 | ||
314 | /** Write IMMU TLB Data in Register. |
483 | /** Write IMMU TLB Data in Register. |
315 | * |
484 | * |
316 | * @param v Value to be written. |
485 | * @param v Value to be written. |
317 | */ |
486 | */ |
318 | static inline void itlb_data_in_write(uint64_t v) |
487 | static inline void itlb_data_in_write(uint64_t v) |
319 | { |
488 | { |
320 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
489 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
321 | flush_pipeline(); |
490 | flush_pipeline(); |
322 | } |
491 | } |
323 | 492 | ||
324 | /** Write DMMU TLB Data in Register. |
493 | /** Write DMMU TLB Data in Register. |
325 | * |
494 | * |
326 | * @param v Value to be written. |
495 | * @param v Value to be written. |
327 | */ |
496 | */ |
328 | static inline void dtlb_data_in_write(uint64_t v) |
497 | static inline void dtlb_data_in_write(uint64_t v) |
329 | { |
498 | { |
330 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
499 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
331 | membar(); |
500 | membar(); |
332 | } |
501 | } |
333 | 502 | ||
334 | /** Read ITLB Synchronous Fault Status Register. |
503 | /** Read ITLB Synchronous Fault Status Register. |
335 | * |
504 | * |
336 | * @return Current content of I-SFSR register. |
505 | * @return Current content of I-SFSR register. |
337 | */ |
506 | */ |
338 | static inline uint64_t itlb_sfsr_read(void) |
507 | static inline uint64_t itlb_sfsr_read(void) |
339 | { |
508 | { |
340 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
509 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
341 | } |
510 | } |
342 | 511 | ||
343 | /** Write ITLB Synchronous Fault Status Register. |
512 | /** Write ITLB Synchronous Fault Status Register. |
344 | * |
513 | * |
345 | * @param v New value of I-SFSR register. |
514 | * @param v New value of I-SFSR register. |
346 | */ |
515 | */ |
347 | static inline void itlb_sfsr_write(uint64_t v) |
516 | static inline void itlb_sfsr_write(uint64_t v) |
348 | { |
517 | { |
349 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
518 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
350 | flush_pipeline(); |
519 | flush_pipeline(); |
351 | } |
520 | } |
352 | 521 | ||
353 | /** Read DTLB Synchronous Fault Status Register. |
522 | /** Read DTLB Synchronous Fault Status Register. |
354 | * |
523 | * |
355 | * @return Current content of D-SFSR register. |
524 | * @return Current content of D-SFSR register. |
356 | */ |
525 | */ |
357 | static inline uint64_t dtlb_sfsr_read(void) |
526 | static inline uint64_t dtlb_sfsr_read(void) |
358 | { |
527 | { |
359 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
528 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
360 | } |
529 | } |
361 | 530 | ||
362 | /** Write DTLB Synchronous Fault Status Register. |
531 | /** Write DTLB Synchronous Fault Status Register. |
363 | * |
532 | * |
364 | * @param v New value of D-SFSR register. |
533 | * @param v New value of D-SFSR register. |
365 | */ |
534 | */ |
366 | static inline void dtlb_sfsr_write(uint64_t v) |
535 | static inline void dtlb_sfsr_write(uint64_t v) |
367 | { |
536 | { |
368 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
537 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
369 | membar(); |
538 | membar(); |
370 | } |
539 | } |
371 | 540 | ||
372 | /** Read DTLB Synchronous Fault Address Register. |
541 | /** Read DTLB Synchronous Fault Address Register. |
373 | * |
542 | * |
374 | * @return Current content of D-SFAR register. |
543 | * @return Current content of D-SFAR register. |
375 | */ |
544 | */ |
376 | static inline uint64_t dtlb_sfar_read(void) |
545 | static inline uint64_t dtlb_sfar_read(void) |
377 | { |
546 | { |
378 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
547 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
379 | } |
548 | } |
380 | 549 | ||
381 | /** Perform IMMU TLB Demap Operation. |
550 | /** Perform IMMU TLB Demap Operation. |
382 | * |
551 | * |
383 | * @param type Selects between context and page demap. |
552 | * @param type Selects between context and page demap. |
384 | * @param context_encoding Specifies which Context register has Context ID for |
553 | * @param context_encoding Specifies which Context register has Context ID for |
385 | * demap. |
554 | * demap. |
386 | * @param page Address which is on the page to be demapped. |
555 | * @param page Address which is on the page to be demapped. |
387 | */ |
556 | */ |
388 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
557 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
389 | { |
558 | { |
390 | tlb_demap_addr_t da; |
559 | tlb_demap_addr_t da; |
391 | page_address_t pg; |
560 | page_address_t pg; |
392 | 561 | ||
393 | da.value = 0; |
562 | da.value = 0; |
394 | pg.address = page; |
563 | pg.address = page; |
395 | 564 | ||
396 | da.type = type; |
565 | da.type = type; |
397 | da.context = context_encoding; |
566 | da.context = context_encoding; |
398 | da.vpn = pg.vpn; |
567 | da.vpn = pg.vpn; |
399 | 568 | ||
400 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
569 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
401 | * address within the |
570 | * address within the |
402 | * ASI */ |
571 | * ASI */ |
403 | flush_pipeline(); |
572 | flush_pipeline(); |
404 | } |
573 | } |
405 | 574 | ||
406 | /** Perform DMMU TLB Demap Operation. |
575 | /** Perform DMMU TLB Demap Operation. |
407 | * |
576 | * |
408 | * @param type Selects between context and page demap. |
577 | * @param type Selects between context and page demap. |
409 | * @param context_encoding Specifies which Context register has Context ID for |
578 | * @param context_encoding Specifies which Context register has Context ID for |
410 | * demap. |
579 | * demap. |
411 | * @param page Address which is on the page to be demapped. |
580 | * @param page Address which is on the page to be demapped. |
412 | */ |
581 | */ |
413 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
582 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
414 | { |
583 | { |
415 | tlb_demap_addr_t da; |
584 | tlb_demap_addr_t da; |
416 | page_address_t pg; |
585 | page_address_t pg; |
417 | 586 | ||
418 | da.value = 0; |
587 | da.value = 0; |
419 | pg.address = page; |
588 | pg.address = page; |
420 | 589 | ||
421 | da.type = type; |
590 | da.type = type; |
422 | da.context = context_encoding; |
591 | da.context = context_encoding; |
423 | da.vpn = pg.vpn; |
592 | da.vpn = pg.vpn; |
424 | 593 | ||
425 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
594 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
426 | * address within the |
595 | * address within the |
427 | * ASI */ |
596 | * ASI */ |
428 | membar(); |
597 | membar(); |
429 | } |
598 | } |
430 | 599 | ||
431 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
600 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
432 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
601 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
433 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
602 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
434 | 603 | ||
435 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
604 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
436 | 605 | ||
437 | extern void dump_sfsr_and_sfar(void); |
606 | extern void dump_sfsr_and_sfar(void); |
438 | 607 | ||
439 | #endif /* !def __ASM__ */ |
608 | #endif /* !def __ASM__ */ |
440 | 609 | ||
441 | #endif |
610 | #endif |
442 | 611 | ||
443 | /** @} |
612 | /** @} |
444 | */ |
613 | */ |
445 | 614 |