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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * Copyright (c) 2008 Pavel Rimsky |
3 | * Copyright (c) 2008 Pavel Rimsky |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup sparc64mm |
30 | /** @addtogroup sparc64mm |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #ifndef KERN_sparc64_sun4v_TLB_H_ |
36 | #ifndef KERN_sparc64_sun4v_TLB_H_ |
37 | #define KERN_sparc64_sun4v_TLB_H_ |
37 | #define KERN_sparc64_sun4v_TLB_H_ |
38 | 38 | ||
39 | #define MMU_FSA_ALIGNMENT 64 |
39 | #define MMU_FSA_ALIGNMENT 64 |
40 | #define MMU_FSA_SIZE 128 |
40 | #define MMU_FSA_SIZE 128 |
41 | 41 | ||
42 | #ifndef __ASM__ |
42 | #ifndef __ASM__ |
43 | 43 | ||
44 | #include <arch/mm/tte.h> |
44 | #include <arch/mm/tte.h> |
- | 45 | #include <print.h> |
|
45 | #include <arch/mm/mmu.h> |
46 | #include <arch/mm/mmu.h> |
46 | #include <arch/mm/page.h> |
47 | #include <arch/mm/page.h> |
47 | #include <arch/asm.h> |
48 | #include <arch/asm.h> |
48 | #include <arch/barrier.h> |
49 | #include <arch/barrier.h> |
49 | #include <arch/types.h> |
50 | #include <arch/types.h> |
50 | #include <arch/register.h> |
51 | #include <arch/register.h> |
51 | #include <arch/cpu.h> |
52 | #include <arch/cpu.h> |
52 | #include <arch/sun4v/hypercall.h> |
53 | #include <arch/sun4v/hypercall.h> |
53 | 54 | ||
54 | /** |
55 | /** |
55 | * Structure filled by hypervisor (or directly CPU, if implemented so) when |
56 | * Structure filled by hypervisor (or directly CPU, if implemented so) when |
56 | * a MMU fault occurs. The structure describes the exact condition which |
57 | * a MMU fault occurs. The structure describes the exact condition which |
57 | * has caused the fault. |
58 | * has caused the fault. |
58 | */ |
59 | */ |
59 | typedef struct mmu_fault_status_area { |
60 | typedef struct mmu_fault_status_area { |
60 | uint64_t ift; /**< Instruction fault type (IFT) */ |
61 | uint64_t ift; /**< Instruction fault type (IFT) */ |
61 | uint64_t ifa; /**< Instruction fault address (IFA) */ |
62 | uint64_t ifa; /**< Instruction fault address (IFA) */ |
62 | uint64_t ifc; /**< Instruction fault context (IFC) */ |
63 | uint64_t ifc; /**< Instruction fault context (IFC) */ |
63 | uint8_t reserved1[0x28]; |
64 | uint8_t reserved1[0x28]; |
64 | 65 | ||
65 | uint64_t dft; /**< Data fault type (DFT) */ |
66 | uint64_t dft; /**< Data fault type (DFT) */ |
66 | uint64_t dfa; /**< Data fault address (DFA) */ |
67 | uint64_t dfa; /**< Data fault address (DFA) */ |
67 | uint64_t dfc; /**< Data fault context (DFC) */ |
68 | uint64_t dfc; /**< Data fault context (DFC) */ |
68 | uint8_t reserved2[0x28]; |
69 | uint8_t reserved2[0x28]; |
69 | } __attribute__ ((packed)) mmu_fault_status_area_t; |
70 | } __attribute__ ((packed)) mmu_fault_status_area_t; |
70 | 71 | ||
71 | #define DTLB_MAX_LOCKED_ENTRIES 8 |
72 | #define DTLB_MAX_LOCKED_ENTRIES 8 |
72 | 73 | ||
73 | /** Bit width of the TLB-locked portion of kernel address space. */ |
74 | /** Bit width of the TLB-locked portion of kernel address space. */ |
74 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
75 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
75 | 76 | ||
76 | /* |
77 | /* |
77 | * Reading and writing context registers. |
78 | * Reading and writing context registers. |
78 | * |
79 | * |
79 | * Note that UltraSPARC Architecture-compatible processors do not require |
80 | * Note that UltraSPARC Architecture-compatible processors do not require |
80 | * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an |
81 | * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an |
81 | * MMU register for proper operation. |
82 | * MMU register for proper operation. |
82 | * |
83 | * |
83 | */ |
84 | */ |
84 | 85 | ||
85 | /** Read MMU Primary Context Register. |
86 | /** Read MMU Primary Context Register. |
86 | * |
87 | * |
87 | * @return Current value of Primary Context Register. |
88 | * @return Current value of Primary Context Register. |
88 | */ |
89 | */ |
89 | static inline uint64_t mmu_primary_context_read(void) |
90 | static inline uint64_t mmu_primary_context_read(void) |
90 | { |
91 | { |
91 | return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); |
92 | return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); |
92 | } |
93 | } |
93 | 94 | ||
94 | /** Write MMU Primary Context Register. |
95 | /** Write MMU Primary Context Register. |
95 | * |
96 | * |
96 | * @param v New value of Primary Context Register. |
97 | * @param v New value of Primary Context Register. |
97 | */ |
98 | */ |
98 | static inline void mmu_primary_context_write(uint64_t v) |
99 | static inline void mmu_primary_context_write(uint64_t v) |
99 | { |
100 | { |
100 | asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); |
101 | asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); |
101 | } |
102 | } |
102 | 103 | ||
103 | /** Read MMU Secondary Context Register. |
104 | /** Read MMU Secondary Context Register. |
104 | * |
105 | * |
105 | * @return Current value of Secondary Context Register. |
106 | * @return Current value of Secondary Context Register. |
106 | */ |
107 | */ |
107 | static inline uint64_t mmu_secondary_context_read(void) |
108 | static inline uint64_t mmu_secondary_context_read(void) |
108 | { |
109 | { |
109 | return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); |
110 | return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); |
110 | } |
111 | } |
111 | 112 | ||
112 | /** Write MMU Secondary Context Register. |
113 | /** Write MMU Secondary Context Register. |
113 | * |
114 | * |
114 | * @param v New value of Secondary Context Register. |
115 | * @param v New value of Secondary Context Register. |
115 | */ |
116 | */ |
116 | static inline void mmu_secondary_context_write(uint64_t v) |
117 | static inline void mmu_secondary_context_write(uint64_t v) |
117 | { |
118 | { |
118 | asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); |
119 | asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); |
119 | } |
120 | } |
120 | 121 | ||
121 | /** |
122 | /** |
122 | * Demaps all mappings in a context. |
123 | * Demaps all mappings in a context. |
123 | * |
124 | * |
124 | * @param context number of the context |
125 | * @param context number of the context |
125 | * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
126 | * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
126 | */ |
127 | */ |
127 | static inline void mmu_demap_ctx(int context, int mmu_flag) { |
128 | static inline void mmu_demap_ctx(int context, int mmu_flag) { |
128 | __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); |
129 | __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); |
129 | } |
130 | } |
130 | 131 | ||
131 | /** |
132 | /** |
132 | * Demaps given page. |
133 | * Demaps given page. |
133 | * |
134 | * |
134 | * @param vaddr VA of the page to be demapped |
135 | * @param vaddr VA of the page to be demapped |
135 | * @param context number of the context |
136 | * @param context number of the context |
136 | * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
137 | * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
137 | */ |
138 | */ |
138 | static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { |
139 | static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { |
139 | __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); |
140 | __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); |
140 | } |
141 | } |
141 | - | ||
142 | /** |
- | |
143 | * Installs a locked TLB entry in kernel address space. |
- | |
144 | * |
- | |
145 | * @param vaddr VA of the page to be demapped |
- | |
146 | * @param ra real address the page is mapped to |
- | |
147 | * @param cacheable should the page be cacheble? |
- | |
148 | * @param privileged should the mapping be privileged? |
- | |
149 | * @param executable should the memory mapped be executable? |
- | |
150 | * @param writable should the memory mapped be writable? |
- | |
151 | * @param size code of the page size |
- | |
152 | * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
- | |
153 | */ |
- | |
154 | static inline void mmu_map_perm_addr(uintptr_t vaddr, uintptr_t ra, |
- | |
155 | bool cacheable, bool privileged, bool executable, |
- | |
156 | bool writable, unsigned size, unsigned mmu_flags) { |
- | |
157 | - | ||
158 | tte_data_t data; |
- | |
159 | data.value = 0; |
- | |
160 | - | ||
161 | data.v = true; |
- | |
162 | data.ra = ra; |
- | |
163 | data.cp = data.cv = cacheable; |
- | |
164 | data.p = privileged; |
- | |
165 | data.x = executable; |
- | |
166 | data.w = writable; |
- | |
167 | data.size = size; |
- | |
168 | - | ||
169 | __hypercall_fast4(MMU_MAP_PERM_ADDR, vaddr, 0, data.value, mmu_flags); |
- | |
170 | } |
- | |
171 | 142 | ||
172 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
143 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
173 | extern void fast_data_access_mmu_miss(unative_t, istate_t *); |
144 | extern void fast_data_access_mmu_miss(unative_t, istate_t *); |
174 | extern void fast_data_access_protection(unative_t, istate_t *); |
145 | extern void fast_data_access_protection(unative_t, istate_t *); |
175 | 146 | ||
176 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
147 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
177 | 148 | ||
178 | extern void describe_dmmu_fault(void); |
149 | extern void describe_dmmu_fault(void); |
179 | 150 | ||
180 | #endif /* !def __ASM__ */ |
151 | #endif /* !def __ASM__ */ |
181 | 152 | ||
182 | #endif |
153 | #endif |
183 | 154 | ||
184 | /** @} |
155 | /** @} |
185 | */ |
156 | */ |
186 | 157 |