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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_Z8530_H_ |
35 | #ifndef KERN_sparc64_Z8530_H_ |
36 | #define KERN_sparc64_Z8530_H_ |
36 | #define KERN_sparc64_Z8530_H_ |
37 | 37 | ||
38 | #include <arch/types.h> |
38 | #include <arch/types.h> |
39 | #include <typedefs.h> |
39 | #include <typedefs.h> |
40 | #include <arch/drivers/kbd.h> |
40 | #include <arch/drivers/kbd.h> |
41 | 41 | ||
42 | #define Z8530_CHAN_A 4 |
42 | #define Z8530_CHAN_A 4 |
43 | #define Z8530_CHAN_B 0 |
43 | #define Z8530_CHAN_B 0 |
44 | 44 | ||
45 | #define WR0 0 |
45 | #define WR0 0 |
46 | #define WR1 1 |
46 | #define WR1 1 |
47 | #define WR2 2 |
47 | #define WR2 2 |
48 | #define WR3 3 |
48 | #define WR3 3 |
49 | #define WR4 4 |
49 | #define WR4 4 |
50 | #define WR5 5 |
50 | #define WR5 5 |
51 | #define WR6 6 |
51 | #define WR6 6 |
52 | #define WR7 7 |
52 | #define WR7 7 |
53 | #define WR8 8 |
53 | #define WR8 8 |
54 | #define WR9 9 |
54 | #define WR9 9 |
55 | #define WR10 10 |
55 | #define WR10 10 |
56 | #define WR11 11 |
56 | #define WR11 11 |
57 | #define WR12 12 |
57 | #define WR12 12 |
58 | #define WR13 13 |
58 | #define WR13 13 |
59 | #define WR14 14 |
59 | #define WR14 14 |
60 | #define WR15 15 |
60 | #define WR15 15 |
61 | 61 | ||
62 | #define RR0 0 |
62 | #define RR0 0 |
63 | #define RR1 1 |
63 | #define RR1 1 |
64 | #define RR2 2 |
64 | #define RR2 2 |
65 | #define RR3 3 |
65 | #define RR3 3 |
66 | #define RR8 8 |
66 | #define RR8 8 |
67 | #define RR10 10 |
67 | #define RR10 10 |
68 | #define RR12 12 |
68 | #define RR12 12 |
69 | #define RR13 13 |
69 | #define RR13 13 |
70 | #define RR14 14 |
70 | #define RR14 14 |
71 | #define RR15 15 |
71 | #define RR15 15 |
72 | 72 | ||
73 | /* Write Register 0 */ |
73 | /* Write Register 0 */ |
74 | #define WR0_TX_IP_RST (0x5<<3) /** Reset pending TX interrupt. */ |
74 | #define WR0_TX_IP_RST (0x5<<3) /** Reset pending TX interrupt. */ |
75 | #define WR0_ERR_RST (0x6<<3) |
75 | #define WR0_ERR_RST (0x6<<3) |
76 | 76 | ||
77 | /* Write Register 1 */ |
77 | /* Write Register 1 */ |
78 | #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
78 | #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
79 | #define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
79 | #define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
80 | #define WR1_IARCSC (0x2<<3) /** Interrupt on All Receive Characters or Special Conditions. */ |
80 | #define WR1_IARCSC (0x2<<3) /** Interrupt on All Receive Characters or Special Conditions. */ |
81 | #define WR1_RISC (0x3<<3) /** Receive Interrupt on Special Condition. */ |
81 | #define WR1_RISC (0x3<<3) /** Receive Interrupt on Special Condition. */ |
82 | #define WR1_PISC (0x1<<2) /** Parity Is Special Condition. */ |
82 | #define WR1_PISC (0x1<<2) /** Parity Is Special Condition. */ |
83 | 83 | ||
84 | /* Write Register 3 */ |
84 | /* Write Register 3 */ |
85 | #define WR3_RX_ENABLE (0x1<<0) /** Rx Enable. */ |
85 | #define WR3_RX_ENABLE (0x1<<0) /** Rx Enable. */ |
86 | #define WR3_RX8BITSCH (0x3<<6) /** 8-bits per character. */ |
86 | #define WR3_RX8BITSCH (0x3<<6) /** 8-bits per character. */ |
87 | 87 | ||
88 | /* Write Register 9 */ |
88 | /* Write Register 9 */ |
89 | #define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */ |
89 | #define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */ |
90 | 90 | ||
91 | /* Read Register 0 */ |
91 | /* Read Register 0 */ |
92 | #define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
92 | #define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
93 | 93 | ||
94 | /** Structure representing the z8530 device. */ |
94 | /** Structure representing the z8530 device. */ |
95 | typedef struct { |
95 | typedef struct { |
96 | devno_t devno; |
96 | devno_t devno; |
97 | volatile uint8_t *reg; /** Memory mapped registers of the z8530. */ |
97 | volatile uint8_t *reg; /** Memory mapped registers of the z8530. */ |
98 | } z8530_t; |
98 | } z8530_t; |
99 | 99 | ||
100 | static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val) |
100 | static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val) |
101 | { |
101 | { |
102 | /* |
102 | /* |
103 | * Registers 8-15 will automatically issue the Point High |
103 | * Registers 8-15 will automatically issue the Point High |
104 | * command as their bit 3 is 1. |
104 | * command as their bit 3 is 1. |
105 | */ |
105 | */ |
106 | dev->reg[WR0+chan] = reg; /* select register */ |
106 | dev->reg[WR0+chan] = reg; /* select register */ |
107 | dev->reg[WR0+chan] = val; /* write value */ |
107 | dev->reg[WR0+chan] = val; /* write value */ |
108 | } |
108 | } |
109 | 109 | ||
110 | static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val) |
110 | static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val) |
111 | { |
111 | { |
112 | z8530_write(dev, Z8530_CHAN_A, reg, val); |
112 | z8530_write(dev, Z8530_CHAN_A, reg, val); |
113 | } |
113 | } |
114 | static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val) |
114 | static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val) |
115 | { |
115 | { |
116 | z8530_write(dev, Z8530_CHAN_B, reg, val); |
116 | z8530_write(dev, Z8530_CHAN_B, reg, val); |
117 | } |
117 | } |
118 | 118 | ||
119 | static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg) |
119 | static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg) |
120 | { |
120 | { |
121 | /* |
121 | /* |
122 | * Registers 8-15 will automatically issue the Point High |
122 | * Registers 8-15 will automatically issue the Point High |
123 | * command as their bit 3 is 1. |
123 | * command as their bit 3 is 1. |
124 | */ |
124 | */ |
125 | dev->reg[WR0+chan] = reg; /* select register */ |
125 | dev->reg[WR0+chan] = reg; /* select register */ |
126 | return dev->reg[WR0+chan]; |
126 | return dev->reg[WR0+chan]; |
127 | } |
127 | } |
128 | 128 | ||
129 | static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg) |
129 | static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg) |
130 | { |
130 | { |
131 | return z8530_read(dev, Z8530_CHAN_A, reg); |
131 | return z8530_read(dev, Z8530_CHAN_A, reg); |
132 | } |
132 | } |
133 | static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg) |
133 | static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg) |
134 | { |
134 | { |
135 | return z8530_read(dev, Z8530_CHAN_B, reg); |
135 | return z8530_read(dev, Z8530_CHAN_B, reg); |
136 | } |
136 | } |
137 | 137 | ||
138 | #endif |
138 | #endif |
139 | 139 | ||
140 | /** @} |
140 | /** @} |
141 | */ |
141 | */ |
142 | 142 |