WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch/arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <align.h>
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
#include <arch/barrier.h>
 
static inline void outb(ioport_t port, uint8_t v)
{
    *((volatile uint8_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outw(ioport_t port, uint16_t v)
{
    *((volatile uint16_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outl(ioport_t port, uint32_t v)
{
    *((volatile uint32_t *)(port)) = v;
    memory_barrier();
}
 
static inline uint8_t inb(ioport_t port)
{
    uint8_t rv;
 
    rv = *((volatile uint8_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint16_t inw(ioport_t port)
{
    uint16_t rv;
 
    rv = *((volatile uint16_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint32_t inl(ioport_t port)
{
    uint32_t rv;
 
    rv = *((volatile uint32_t *)(port));
    memory_barrier();
 
    return rv;
}
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read STICK_compare Register.
 *
 * @return Value of STICK_compare register.
 */
static inline uint64_t stick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write STICK_compare Register.
 *
 * @param v New value of STICK_comapre register.
 */
static inline void stick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
 
 
 
 
 
 
 
 
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#if defined(SUN4U)
#include <arch/sun4u/asm.h>
#elif defined (SUN4V)
#include <arch/sun4v/asm.h>
#endif
 
#endif
 
/** @}
 */
 

Rev 3993	Rev 4130
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
38	#include <arch/arch.h>	38	#include <arch/arch.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <typedefs.h>	40	#include <typedefs.h>
41	#include <align.h>	41	#include <align.h>
42	#include <arch/register.h>	42	#include <arch/register.h>
43	#include <config.h>	43	#include <config.h>
44	#include <arch/stack.h>	44	#include <arch/stack.h>
45	#include <arch/barrier.h>	45	#include <arch/barrier.h>
46		46
47	static inline void outb(ioport_t port, uint8_t v)	47	static inline void outb(ioport_t port, uint8_t v)
48	{	48	{
49	((volatile uint8_t )(port)) = v;	49	((volatile uint8_t )(port)) = v;
50	memory_barrier();	50	memory_barrier();
51	}	51	}
52		52
53	static inline void outw(ioport_t port, uint16_t v)	53	static inline void outw(ioport_t port, uint16_t v)
54	{	54	{
55	((volatile uint16_t )(port)) = v;	55	((volatile uint16_t )(port)) = v;
56	memory_barrier();	56	memory_barrier();
57	}	57	}
58		58
59	static inline void outl(ioport_t port, uint32_t v)	59	static inline void outl(ioport_t port, uint32_t v)
60	{	60	{
61	((volatile uint32_t )(port)) = v;	61	((volatile uint32_t )(port)) = v;
62	memory_barrier();	62	memory_barrier();
63	}	63	}
64		64
65	static inline uint8_t inb(ioport_t port)	65	static inline uint8_t inb(ioport_t port)
66	{	66	{
67	uint8_t rv;	67	uint8_t rv;
68		68
69	rv = ((volatile uint8_t )(port));	69	rv = ((volatile uint8_t )(port));
70	memory_barrier();	70	memory_barrier();
71		71
72	return rv;	72	return rv;
73	}	73	}
74		74
75	static inline uint16_t inw(ioport_t port)	75	static inline uint16_t inw(ioport_t port)
76	{	76	{
77	uint16_t rv;	77	uint16_t rv;
78		78
79	rv = ((volatile uint16_t )(port));	79	rv = ((volatile uint16_t )(port));
80	memory_barrier();	80	memory_barrier();
81		81
82	return rv;	82	return rv;
83	}	83	}
84		84
85	static inline uint32_t inl(ioport_t port)	85	static inline uint32_t inl(ioport_t port)
86	{	86	{
87	uint32_t rv;	87	uint32_t rv;
88		88
89	rv = ((volatile uint32_t )(port));	89	rv = ((volatile uint32_t )(port));
90	memory_barrier();	90	memory_barrier();
91		91
92	return rv;	92	return rv;
93	}	93	}
94		94
95	/** Read Processor State register.	95	/** Read Processor State register.
96	*	96	*
97	* @return Value of PSTATE register.	97	* @return Value of PSTATE register.
98	*/	98	*/
99	static inline uint64_t pstate_read(void)	99	static inline uint64_t pstate_read(void)
100	{	100	{
101	uint64_t v;	101	uint64_t v;
102		102
103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));	103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
104		104
105	return v;	105	return v;
106	}	106	}
107		107
108	/** Write Processor State register.	108	/** Write Processor State register.
109	*	109	*
110	* @param v New value of PSTATE register.	110	* @param v New value of PSTATE register.
111	*/	111	*/
112	static inline void pstate_write(uint64_t v)	112	static inline void pstate_write(uint64_t v)
113	{	113	{
114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
115	}	115	}
116		116
117	/** Read TICK_compare Register.	117	/** Read TICK_compare Register.
118	*	118	*
119	* @return Value of TICK_comapre register.	119	* @return Value of TICK_comapre register.
120	*/	120	*/
121	static inline uint64_t tick_compare_read(void)	121	static inline uint64_t tick_compare_read(void)
122	{	122	{
123	uint64_t v;	123	uint64_t v;
124		124
125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
126		126
127	return v;	127	return v;
128	}	128	}
129		129
130	/** Write TICK_compare Register.	130	/** Write TICK_compare Register.
131	*	131	*
132	* @param v New value of TICK_comapre register.	132	* @param v New value of TICK_comapre register.
133	*/	133	*/
134	static inline void tick_compare_write(uint64_t v)	134	static inline void tick_compare_write(uint64_t v)
135	{	135	{
136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
137	}	137	}
138		138
139	/** Read STICK_compare Register.	139	/** Read STICK_compare Register.
140	*	140	*
141	* @return Value of STICK_compare register.	141	* @return Value of STICK_compare register.
142	*/	142	*/
143	static inline uint64_t stick_compare_read(void)	143	static inline uint64_t stick_compare_read(void)
144	{	144	{
145	uint64_t v;	145	uint64_t v;
146		146
147	asm volatile ("rd %%asr25, %0\n" : "=r" (v));	147	asm volatile ("rd %%asr25, %0\n" : "=r" (v));
148		148
149	return v;	149	return v;
150	}	150	}
151		151
152	/** Write STICK_compare Register.	152	/** Write STICK_compare Register.
153	*	153	*
154	* @param v New value of STICK_comapre register.	154	* @param v New value of STICK_comapre register.
155	*/	155	*/
156	static inline void stick_compare_write(uint64_t v)	156	static inline void stick_compare_write(uint64_t v)
157	{	157	{
158	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));	158	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
159	}	159	}
160		160
161	/** Read TICK Register.	161	/** Read TICK Register.
162	*	162	*
163	* @return Value of TICK register.	163	* @return Value of TICK register.
164	*/	164	*/
165	static inline uint64_t tick_read(void)	165	static inline uint64_t tick_read(void)
166	{	166	{
167	uint64_t v;	167	uint64_t v;
168		168
169	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));	169	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
170		170
171	return v;	171	return v;
172	}	172	}
173		173
174	/** Write TICK Register.	-
175	*	-
176	* @param v New value of TICK register.	-
177	*/	-
178	static inline void tick_write(uint64_t v)	-
179	{	-
180	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	-
181	}	-
182		-
183	/** Read FPRS Register.	174	/** Read FPRS Register.
184	*	175	*
185	* @return Value of FPRS register.	176	* @return Value of FPRS register.
186	*/	177	*/
187	static inline uint64_t fprs_read(void)	178	static inline uint64_t fprs_read(void)
188	{	179	{
189	uint64_t v;	180	uint64_t v;
190		181
191	asm volatile ("rd %%fprs, %0\n" : "=r" (v));	182	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
192		183
193	return v;	184	return v;
194	}	185	}
195		186
196	/** Write FPRS Register.	187	/** Write FPRS Register.
197	*	188	*
198	* @param v New value of FPRS register.	189	* @param v New value of FPRS register.
199	*/	190	*/
200	static inline void fprs_write(uint64_t v)	191	static inline void fprs_write(uint64_t v)
201	{	192	{
202	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	193	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
203	}	194	}
204		195
205	/** Read SOFTINT Register.	196	/** Read SOFTINT Register.
206	*	197	*
207	* @return Value of SOFTINT register.	198	* @return Value of SOFTINT register.
208	*/	199	*/
209	static inline uint64_t softint_read(void)	200	static inline uint64_t softint_read(void)
210	{	201	{
211	uint64_t v;	202	uint64_t v;
212		203
213	asm volatile ("rd %%softint, %0\n" : "=r" (v));	204	asm volatile ("rd %%softint, %0\n" : "=r" (v));
214		205
215	return v;	206	return v;
216	}	207	}
217		208
218	/** Write SOFTINT Register.	209	/** Write SOFTINT Register.
219	*	210	*
220	* @param v New value of SOFTINT register.	211	* @param v New value of SOFTINT register.
221	*/	212	*/
222	static inline void softint_write(uint64_t v)	213	static inline void softint_write(uint64_t v)
223	{	214	{
224	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	215	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
225	}	216	}
226		217
227	/** Write CLEAR_SOFTINT Register.	218	/** Write CLEAR_SOFTINT Register.
228	*	219	*
229	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	220	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
230	*	221	*
231	* @param v New value of CLEAR_SOFTINT register.	222	* @param v New value of CLEAR_SOFTINT register.
232	*/	223	*/
233	static inline void clear_softint_write(uint64_t v)	224	static inline void clear_softint_write(uint64_t v)
234	{	225	{
235	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	226	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
236	}	227	}
237		228
238	/** Write SET_SOFTINT Register.	229	/** Write SET_SOFTINT Register.
239	*	230	*
240	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	231	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
241	*	232	*
242	* @param v New value of SET_SOFTINT register.	233	* @param v New value of SET_SOFTINT register.
243	*/	234	*/
244	static inline void set_softint_write(uint64_t v)	235	static inline void set_softint_write(uint64_t v)
245	{	236	{
246	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	237	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
247	}	238	}
248		239
249	/** Enable interrupts.	240	/** Enable interrupts.
250	*	241	*
251	* Enable interrupts and return previous	242	* Enable interrupts and return previous
252	* value of IPL.	243	* value of IPL.
253	*	244	*
254	* @return Old interrupt priority level.	245	* @return Old interrupt priority level.
255	*/	246	*/
256	static inline ipl_t interrupts_enable(void) {	247	static inline ipl_t interrupts_enable(void) {
257	pstate_reg_t pstate;	248	pstate_reg_t pstate;
258	uint64_t value;	249	uint64_t value;
259		250
260	value = pstate_read();	251	value = pstate_read();
261	pstate.value = value;	252	pstate.value = value;
262	pstate.ie = true;	253	pstate.ie = true;
263	pstate_write(pstate.value);	254	pstate_write(pstate.value);
264		255
265	return (ipl_t) value;	256	return (ipl_t) value;
266	}	257	}
267		258
268	/** Disable interrupts.	259	/** Disable interrupts.
269	*	260	*
270	* Disable interrupts and return previous	261	* Disable interrupts and return previous
271	* value of IPL.	262	* value of IPL.
272	*	263	*
273	* @return Old interrupt priority level.	264	* @return Old interrupt priority level.
274	*/	265	*/
275	static inline ipl_t interrupts_disable(void) {	266	static inline ipl_t interrupts_disable(void) {
276	pstate_reg_t pstate;	267	pstate_reg_t pstate;
277	uint64_t value;	268	uint64_t value;
278		269
279	value = pstate_read();	270	value = pstate_read();
280	pstate.value = value;	271	pstate.value = value;
281	pstate.ie = false;	272	pstate.ie = false;
282	pstate_write(pstate.value);	273	pstate_write(pstate.value);
283		274
284	return (ipl_t) value;	275	return (ipl_t) value;
285	}	276	}
286		277
287	/** Restore interrupt priority level.	278	/** Restore interrupt priority level.
288	*	279	*
289	* Restore IPL.	280	* Restore IPL.
290	*	281	*
291	* @param ipl Saved interrupt priority level.	282	* @param ipl Saved interrupt priority level.
292	*/	283	*/
293	static inline void interrupts_restore(ipl_t ipl) {	284	static inline void interrupts_restore(ipl_t ipl) {
294	pstate_reg_t pstate;	285	pstate_reg_t pstate;
295		286
296	pstate.value = pstate_read();	287	pstate.value = pstate_read();
297	pstate.ie = ((pstate_reg_t) ipl).ie;	288	pstate.ie = ((pstate_reg_t) ipl).ie;
298	pstate_write(pstate.value);	289	pstate_write(pstate.value);
299	}	290	}
300		291
301	/** Return interrupt priority level.	292	/** Return interrupt priority level.
302	*	293	*
303	* Return IPL.	294	* Return IPL.
304	*	295	*
305	* @return Current interrupt priority level.	296	* @return Current interrupt priority level.
306	*/	297	*/
307	static inline ipl_t interrupts_read(void) {	298	static inline ipl_t interrupts_read(void) {
308	return (ipl_t) pstate_read();	299	return (ipl_t) pstate_read();
309	}	300	}
310		301
311	/** Return base address of current stack.	302	/** Return base address of current stack.
312	*	303	*
313	* Return the base address of the current stack.	304	* Return the base address of the current stack.
314	* The stack is assumed to be STACK_SIZE bytes long.	305	* The stack is assumed to be STACK_SIZE bytes long.
315	* The stack must start on page boundary.	306	* The stack must start on page boundary.
316	*/	307	*/
317	static inline uintptr_t get_stack_base(void)	308	static inline uintptr_t get_stack_base(void)
318	{	309	{
319	uintptr_t unbiased_sp;	310	uintptr_t unbiased_sp;
320		311
321	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	312	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
322		313
323	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	314	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
324	}	315	}
325		-
326	/** Read Version Register.	-
327	*	-
328	* @return Value of VER register.	-
329	*/	-
330	static inline uint64_t ver_read(void)	-
331	{	-
332	uint64_t v;	-
333		-
334	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));	-
335		-
336	return v;	-
337	}	-
338		316
339	/** Read Trap Program Counter register.	317	/** Read Trap Program Counter register.
340	*	318	*
341	* @return Current value in TPC.	319	* @return Current value in TPC.
342	*/	320	*/
343	static inline uint64_t tpc_read(void)	321	static inline uint64_t tpc_read(void)
344	{	322	{
345	uint64_t v;	323	uint64_t v;
346		324
347	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));	325	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
348		326
349	return v;	327	return v;
350	}	328	}
351		329
352	/** Read Trap Level register.	330	/** Read Trap Level register.
353	*	331	*
354	* @return Current value in TL.	332	* @return Current value in TL.
355	*/	333	*/
356	static inline uint64_t tl_read(void)	334	static inline uint64_t tl_read(void)
357	{	335	{
358	uint64_t v;	336	uint64_t v;
359		337
360	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));	338	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
361		339
362	return v;	340	return v;
363	}	341	}
364		342
365	/** Read Trap Base Address register.	343	/** Read Trap Base Address register.
366	*	344	*
367	* @return Current value in TBA.	345	* @return Current value in TBA.
368	*/	346	*/
369	static inline uint64_t tba_read(void)	347	static inline uint64_t tba_read(void)
370	{	348	{
371	uint64_t v;	349	uint64_t v;
372		350
373	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));	351	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
374		352
375	return v;	353	return v;
376	}	354	}
377		355
378	/** Write Trap Base Address register.	356	/** Write Trap Base Address register.
379	*	357	*
380	* @param v New value of TBA.	358	* @param v New value of TBA.
381	*/	359	*/
382	static inline void tba_write(uint64_t v)	360	static inline void tba_write(uint64_t v)
383	{	361	{
384	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	362	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
385	}	363	}
386		364
387	/** Load uint64_t from alternate space.	365	/** Load uint64_t from alternate space.
388	*	366	*
389	* @param asi ASI determining the alternate space.	367	* @param asi ASI determining the alternate space.
390	* @param va Virtual address within the ASI.	368	* @param va Virtual address within the ASI.
391	*	369	*
392	* @return Value read from the virtual address in the specified address space.	370	* @return Value read from the virtual address in the specified address space.
393	*/	371	*/
394	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	372	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
395	{	373	{
396	uint64_t v;	374	uint64_t v;
397		375
398	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	376	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
399		377
400	return v;	378	return v;
401	}	379	}
402		380
403	/** Store uint64_t to alternate space.	381	/** Store uint64_t to alternate space.
404	*	382	*
405	* @param asi ASI determining the alternate space.	383	* @param asi ASI determining the alternate space.
406	* @param va Virtual address within the ASI.	384	* @param va Virtual address within the ASI.
407	* @param v Value to be written.	385	* @param v Value to be written.
408	*/	386	*/
409	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	387	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
410	{	388	{
411	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	389	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
412	}	390	}
413		391
414	/** Flush all valid register windows to memory. */	392	/** Flush all valid register windows to memory. */
415	static inline void flushw(void)	393	static inline void flushw(void)
416	{	394	{
417	asm volatile ("flushw\n");	395	asm volatile ("flushw\n");
418	}	396	}
419		397
420	/** Switch to nucleus by setting TL to 1. */	398	/** Switch to nucleus by setting TL to 1. */
421	static inline void nucleus_enter(void)	399	static inline void nucleus_enter(void)
422	{	400	{
423	asm volatile ("wrpr %g0, 1, %tl\n");	401	asm volatile ("wrpr %g0, 1, %tl\n");
424	}	402	}
425		403
426	/** Switch from nucleus by setting TL to 0. */	404	/** Switch from nucleus by setting TL to 0. */
427	static inline void nucleus_leave(void)	405	static inline void nucleus_leave(void)
428	{	406	{
429	asm volatile ("wrpr %g0, %g0, %tl\n");	407	asm volatile ("wrpr %g0, %g0, %tl\n");
430	}	408	}
431		409
432	extern void cpu_halt(void);	410	extern void cpu_halt(void);
433	extern void cpu_sleep(void);	411	extern void cpu_sleep(void);
434	extern void asm_delay_loop(const uint32_t usec);	412	extern void asm_delay_loop(const uint32_t usec);
435		413
436	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	414	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
437		415
438	#if defined(SUN4U)	416	#if defined(SUN4U)
439	#include <arch/sun4u/asm.h>	417	#include <arch/sun4u/asm.h>
440	#elif defined (SUN4V)	418	#elif defined (SUN4V)
441	#include <arch/sun4v/asm.h>	419	#include <arch/sun4v/asm.h>
442	#endif	420	#endif
443		421
444	#endif	422	#endif
445		423
446	/** @}	424	/** @}
447	*/	425	*/
448		426

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(root)/branches/sparc/kernel/arch/sparc64/include/asm.h – Rev 3993 → 4130