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1
/*
1
/*
2
 * Copyright (c) 2005 Jakub Jermar
2
 * Copyright (c) 2005 Jakub Jermar
3
 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
/** @addtogroup sparc64
29
/** @addtogroup sparc64
30
 * @{
30
 * @{
31
 */
31
 */
32
/** @file
32
/** @file
33
 */
33
 */
34
 
34
 
35
#ifndef KERN_sparc64_ASM_H_
35
#ifndef KERN_sparc64_ASM_H_
36
#define KERN_sparc64_ASM_H_
36
#define KERN_sparc64_ASM_H_
37
 
37
 
38
#include <arch/arch.h>
38
#include <arch/arch.h>
39
#include <arch/types.h>
39
#include <arch/types.h>
40
#include <typedefs.h>
40
#include <typedefs.h>
41
#include <align.h>
41
#include <align.h>
42
#include <arch/register.h>
42
#include <arch/register.h>
43
#include <config.h>
43
#include <config.h>
44
#include <arch/stack.h>
44
#include <arch/stack.h>
45
#include <arch/barrier.h>
45
#include <arch/barrier.h>
46
 
46
 
47
static inline void outb(ioport_t port, uint8_t v)
47
static inline void outb(ioport_t port, uint8_t v)
48
{
48
{
49
    *((volatile uint8_t *)(port)) = v;
49
    *((volatile uint8_t *)(port)) = v;
50
    memory_barrier();
50
    memory_barrier();
51
}
51
}
52
 
52
 
53
static inline void outw(ioport_t port, uint16_t v)
53
static inline void outw(ioport_t port, uint16_t v)
54
{
54
{
55
    *((volatile uint16_t *)(port)) = v;
55
    *((volatile uint16_t *)(port)) = v;
56
    memory_barrier();
56
    memory_barrier();
57
}
57
}
58
 
58
 
59
static inline void outl(ioport_t port, uint32_t v)
59
static inline void outl(ioport_t port, uint32_t v)
60
{
60
{
61
    *((volatile uint32_t *)(port)) = v;
61
    *((volatile uint32_t *)(port)) = v;
62
    memory_barrier();
62
    memory_barrier();
63
}
63
}
64
 
64
 
65
static inline uint8_t inb(ioport_t port)
65
static inline uint8_t inb(ioport_t port)
66
{
66
{
67
    uint8_t rv;
67
    uint8_t rv;
68
 
68
 
69
    rv = *((volatile uint8_t *)(port));
69
    rv = *((volatile uint8_t *)(port));
70
    memory_barrier();
70
    memory_barrier();
71
 
71
 
72
    return rv;
72
    return rv;
73
}
73
}
74
 
74
 
75
static inline uint16_t inw(ioport_t port)
75
static inline uint16_t inw(ioport_t port)
76
{
76
{
77
    uint16_t rv;
77
    uint16_t rv;
78
 
78
 
79
    rv = *((volatile uint16_t *)(port));
79
    rv = *((volatile uint16_t *)(port));
80
    memory_barrier();
80
    memory_barrier();
81
 
81
 
82
    return rv;
82
    return rv;
83
}
83
}
84
 
84
 
85
static inline uint32_t inl(ioport_t port)
85
static inline uint32_t inl(ioport_t port)
86
{
86
{
87
    uint32_t rv;
87
    uint32_t rv;
88
 
88
 
89
    rv = *((volatile uint32_t *)(port));
89
    rv = *((volatile uint32_t *)(port));
90
    memory_barrier();
90
    memory_barrier();
91
 
91
 
92
    return rv;
92
    return rv;
93
}
93
}
94
 
94
 
95
/** Read Processor State register.
95
/** Read Processor State register.
96
 *
96
 *
97
 * @return Value of PSTATE register.
97
 * @return Value of PSTATE register.
98
 */
98
 */
99
static inline uint64_t pstate_read(void)
99
static inline uint64_t pstate_read(void)
100
{
100
{
101
    uint64_t v;
101
    uint64_t v;
102
   
102
   
103
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
103
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
104
   
104
   
105
    return v;
105
    return v;
106
}
106
}
107
 
107
 
108
/** Write Processor State register.
108
/** Write Processor State register.
109
 *
109
 *
110
 * @param v New value of PSTATE register.
110
 * @param v New value of PSTATE register.
111
 */
111
 */
112
static inline void pstate_write(uint64_t v)
112
static inline void pstate_write(uint64_t v)
113
{
113
{
114
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
114
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
115
}
115
}
116
 
116
 
117
/** Read TICK_compare Register.
117
/** Read TICK_compare Register.
118
 *
118
 *
119
 * @return Value of TICK_comapre register.
119
 * @return Value of TICK_comapre register.
120
 */
120
 */
121
static inline uint64_t tick_compare_read(void)
121
static inline uint64_t tick_compare_read(void)
122
{
122
{
123
    uint64_t v;
123
    uint64_t v;
124
   
124
   
125
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
125
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
126
   
126
   
127
    return v;
127
    return v;
128
}
128
}
129
 
129
 
130
/** Write TICK_compare Register.
130
/** Write TICK_compare Register.
131
 *
131
 *
132
 * @param v New value of TICK_comapre register.
132
 * @param v New value of TICK_comapre register.
133
 */
133
 */
134
static inline void tick_compare_write(uint64_t v)
134
static inline void tick_compare_write(uint64_t v)
135
{
135
{
136
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
136
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
137
}
137
}
138
 
138
 
139
/** Read STICK_compare Register.
139
/** Read STICK_compare Register.
140
 *
140
 *
141
 * @return Value of STICK_compare register.
141
 * @return Value of STICK_compare register.
142
 */
142
 */
143
static inline uint64_t stick_compare_read(void)
143
static inline uint64_t stick_compare_read(void)
144
{
144
{
145
    uint64_t v;
145
    uint64_t v;
146
   
146
   
147
    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
147
    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
148
   
148
   
149
    return v;
149
    return v;
150
}
150
}
151
 
151
 
152
/** Write STICK_compare Register.
152
/** Write STICK_compare Register.
153
 *
153
 *
154
 * @param v New value of STICK_comapre register.
154
 * @param v New value of STICK_comapre register.
155
 */
155
 */
156
static inline void stick_compare_write(uint64_t v)
156
static inline void stick_compare_write(uint64_t v)
157
{
157
{
158
    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
158
    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
159
}
159
}
160
 
160
 
161
/** Read TICK Register.
161
/** Read TICK Register.
162
 *
162
 *
163
 * @return Value of TICK register.
163
 * @return Value of TICK register.
164
 */
164
 */
165
static inline uint64_t tick_read(void)
165
static inline uint64_t tick_read(void)
166
{
166
{
167
    uint64_t v;
167
    uint64_t v;
168
   
168
   
169
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
169
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
170
   
170
   
171
    return v;
171
    return v;
172
}
172
}
173
 
173
 
174
/** Write TICK Register.
174
/** Write TICK Register.
175
 *
175
 *
176
 * @param v New value of TICK register.
176
 * @param v New value of TICK register.
177
 */
177
 */
178
static inline void tick_write(uint64_t v)
178
static inline void tick_write(uint64_t v)
179
{
179
{
180
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
180
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
181
}
181
}
182
 
182
 
183
/** Read FPRS Register.
183
/** Read FPRS Register.
184
 *
184
 *
185
 * @return Value of FPRS register.
185
 * @return Value of FPRS register.
186
 */
186
 */
187
static inline uint64_t fprs_read(void)
187
static inline uint64_t fprs_read(void)
188
{
188
{
189
    uint64_t v;
189
    uint64_t v;
190
   
190
   
191
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
191
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
192
   
192
   
193
    return v;
193
    return v;
194
}
194
}
195
 
195
 
196
/** Write FPRS Register.
196
/** Write FPRS Register.
197
 *
197
 *
198
 * @param v New value of FPRS register.
198
 * @param v New value of FPRS register.
199
 */
199
 */
200
static inline void fprs_write(uint64_t v)
200
static inline void fprs_write(uint64_t v)
201
{
201
{
202
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
202
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
203
}
203
}
204
 
204
 
205
/** Read SOFTINT Register.
205
/** Read SOFTINT Register.
206
 *
206
 *
207
 * @return Value of SOFTINT register.
207
 * @return Value of SOFTINT register.
208
 */
208
 */
209
static inline uint64_t softint_read(void)
209
static inline uint64_t softint_read(void)
210
{
210
{
211
    uint64_t v;
211
    uint64_t v;
212
 
212
 
213
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
213
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
214
 
214
 
215
    return v;
215
    return v;
216
}
216
}
217
 
217
 
218
/** Write SOFTINT Register.
218
/** Write SOFTINT Register.
219
 *
219
 *
220
 * @param v New value of SOFTINT register.
220
 * @param v New value of SOFTINT register.
221
 */
221
 */
222
static inline void softint_write(uint64_t v)
222
static inline void softint_write(uint64_t v)
223
{
223
{
224
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
224
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
225
}
225
}
226
 
226
 
227
/** Write CLEAR_SOFTINT Register.
227
/** Write CLEAR_SOFTINT Register.
228
 *
228
 *
229
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
229
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
230
 *
230
 *
231
 * @param v New value of CLEAR_SOFTINT register.
231
 * @param v New value of CLEAR_SOFTINT register.
232
 */
232
 */
233
static inline void clear_softint_write(uint64_t v)
233
static inline void clear_softint_write(uint64_t v)
234
{
234
{
235
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
235
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
236
}
236
}
237
 
237
 
238
/** Write SET_SOFTINT Register.
238
/** Write SET_SOFTINT Register.
239
 *
239
 *
240
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
240
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
241
 *
241
 *
242
 * @param v New value of SET_SOFTINT register.
242
 * @param v New value of SET_SOFTINT register.
243
 */
243
 */
244
static inline void set_softint_write(uint64_t v)
244
static inline void set_softint_write(uint64_t v)
245
{
245
{
246
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
246
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
247
}
247
}
248
 
248
 
249
/** Enable interrupts.
249
/** Enable interrupts.
250
 *
250
 *
251
 * Enable interrupts and return previous
251
 * Enable interrupts and return previous
252
 * value of IPL.
252
 * value of IPL.
253
 *
253
 *
254
 * @return Old interrupt priority level.
254
 * @return Old interrupt priority level.
255
 */
255
 */
256
static inline ipl_t interrupts_enable(void) {
256
static inline ipl_t interrupts_enable(void) {
257
    pstate_reg_t pstate;
257
    pstate_reg_t pstate;
258
    uint64_t value;
258
    uint64_t value;
259
   
259
   
260
    value = pstate_read();
260
    value = pstate_read();
261
    pstate.value = value;
261
    pstate.value = value;
262
    pstate.ie = true;
262
    pstate.ie = true;
263
    pstate_write(pstate.value);
263
    pstate_write(pstate.value);
264
   
264
   
265
    return (ipl_t) value;
265
    return (ipl_t) value;
266
}
266
}
267
 
267
 
268
/** Disable interrupts.
268
/** Disable interrupts.
269
 *
269
 *
270
 * Disable interrupts and return previous
270
 * Disable interrupts and return previous
271
 * value of IPL.
271
 * value of IPL.
272
 *
272
 *
273
 * @return Old interrupt priority level.
273
 * @return Old interrupt priority level.
274
 */
274
 */
275
static inline ipl_t interrupts_disable(void) {
275
static inline ipl_t interrupts_disable(void) {
276
    pstate_reg_t pstate;
276
    pstate_reg_t pstate;
277
    uint64_t value;
277
    uint64_t value;
278
   
278
   
279
    value = pstate_read();
279
    value = pstate_read();
280
    pstate.value = value;
280
    pstate.value = value;
281
    pstate.ie = false;
281
    pstate.ie = false;
282
    pstate_write(pstate.value);
282
    pstate_write(pstate.value);
283
   
283
   
284
    return (ipl_t) value;
284
    return (ipl_t) value;
285
}
285
}
286
 
286
 
287
/** Restore interrupt priority level.
287
/** Restore interrupt priority level.
288
 *
288
 *
289
 * Restore IPL.
289
 * Restore IPL.
290
 *
290
 *
291
 * @param ipl Saved interrupt priority level.
291
 * @param ipl Saved interrupt priority level.
292
 */
292
 */
293
static inline void interrupts_restore(ipl_t ipl) {
293
static inline void interrupts_restore(ipl_t ipl) {
294
    pstate_reg_t pstate;
294
    pstate_reg_t pstate;
295
   
295
   
296
    pstate.value = pstate_read();
296
    pstate.value = pstate_read();
297
    pstate.ie = ((pstate_reg_t) ipl).ie;
297
    pstate.ie = ((pstate_reg_t) ipl).ie;
298
    pstate_write(pstate.value);
298
    pstate_write(pstate.value);
299
}
299
}
300
 
300
 
301
/** Return interrupt priority level.
301
/** Return interrupt priority level.
302
 *
302
 *
303
 * Return IPL.
303
 * Return IPL.
304
 *
304
 *
305
 * @return Current interrupt priority level.
305
 * @return Current interrupt priority level.
306
 */
306
 */
307
static inline ipl_t interrupts_read(void) {
307
static inline ipl_t interrupts_read(void) {
308
    return (ipl_t) pstate_read();
308
    return (ipl_t) pstate_read();
309
}
309
}
310
 
310
 
311
/** Return base address of current stack.
311
/** Return base address of current stack.
312
 *
312
 *
313
 * Return the base address of the current stack.
313
 * Return the base address of the current stack.
314
 * The stack is assumed to be STACK_SIZE bytes long.
314
 * The stack is assumed to be STACK_SIZE bytes long.
315
 * The stack must start on page boundary.
315
 * The stack must start on page boundary.
316
 */
316
 */
317
static inline uintptr_t get_stack_base(void)
317
static inline uintptr_t get_stack_base(void)
318
{
318
{
319
    uintptr_t unbiased_sp;
319
    uintptr_t unbiased_sp;
320
   
320
   
321
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
321
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
322
   
322
   
323
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
323
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
324
}
324
}
325
 
325
 
326
/** Read Version Register.
326
/** Read Version Register.
327
 *
327
 *
328
 * @return Value of VER register.
328
 * @return Value of VER register.
329
 */
329
 */
330
static inline uint64_t ver_read(void)
330
static inline uint64_t ver_read(void)
331
{
331
{
332
    uint64_t v;
332
    uint64_t v;
333
   
333
   
334
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
334
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
335
   
335
   
336
    return v;
336
    return v;
337
}
337
}
338
 
338
 
339
/** Read Trap Program Counter register.
339
/** Read Trap Program Counter register.
340
 *
340
 *
341
 * @return Current value in TPC.
341
 * @return Current value in TPC.
342
 */
342
 */
343
static inline uint64_t tpc_read(void)
343
static inline uint64_t tpc_read(void)
344
{
344
{
345
    uint64_t v;
345
    uint64_t v;
346
   
346
   
347
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
347
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
348
   
348
   
349
    return v;
349
    return v;
350
}
350
}
351
 
351
 
352
/** Read Trap Level register.
352
/** Read Trap Level register.
353
 *
353
 *
354
 * @return Current value in TL.
354
 * @return Current value in TL.
355
 */
355
 */
356
static inline uint64_t tl_read(void)
356
static inline uint64_t tl_read(void)
357
{
357
{
358
    uint64_t v;
358
    uint64_t v;
359
   
359
   
360
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
360
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
361
   
361
   
362
    return v;
362
    return v;
363
}
363
}
364
 
364
 
365
/** Read Trap Base Address register.
365
/** Read Trap Base Address register.
366
 *
366
 *
367
 * @return Current value in TBA.
367
 * @return Current value in TBA.
368
 */
368
 */
369
static inline uint64_t tba_read(void)
369
static inline uint64_t tba_read(void)
370
{
370
{
371
    uint64_t v;
371
    uint64_t v;
372
   
372
   
373
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
373
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
374
   
374
   
375
    return v;
375
    return v;
376
}
376
}
377
 
377
 
378
/** Write Trap Base Address register.
378
/** Write Trap Base Address register.
379
 *
379
 *
380
 * @param v New value of TBA.
380
 * @param v New value of TBA.
381
 */
381
 */
382
static inline void tba_write(uint64_t v)
382
static inline void tba_write(uint64_t v)
383
{
383
{
384
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
384
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
385
}
385
}
386
 
386
 
387
/** Load uint64_t from alternate space.
387
/** Load uint64_t from alternate space.
388
 *
388
 *
389
 * @param asi ASI determining the alternate space.
389
 * @param asi ASI determining the alternate space.
390
 * @param va Virtual address within the ASI.
390
 * @param va Virtual address within the ASI.
391
 *
391
 *
392
 * @return Value read from the virtual address in the specified address space.
392
 * @return Value read from the virtual address in the specified address space.
393
 */
393
 */
394
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
394
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
395
{
395
{
396
    uint64_t v;
396
    uint64_t v;
397
   
397
   
398
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
398
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
399
   
399
   
400
    return v;
400
    return v;
401
}
401
}
402
 
402
 
403
/** Store uint64_t to alternate space.
403
/** Store uint64_t to alternate space.
404
 *
404
 *
405
 * @param asi ASI determining the alternate space.
405
 * @param asi ASI determining the alternate space.
406
 * @param va Virtual address within the ASI.
406
 * @param va Virtual address within the ASI.
407
 * @param v Value to be written.
407
 * @param v Value to be written.
408
 */
408
 */
409
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
409
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
410
{
410
{
411
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
411
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
412
}
412
}
413
 
413
 
414
/** Flush all valid register windows to memory. */
414
/** Flush all valid register windows to memory. */
415
static inline void flushw(void)
415
static inline void flushw(void)
416
{
416
{
417
    asm volatile ("flushw\n");
417
    asm volatile ("flushw\n");
418
}
418
}
419
 
419
 
420
/** Switch to nucleus by setting TL to 1. */
420
/** Switch to nucleus by setting TL to 1. */
421
static inline void nucleus_enter(void)
421
static inline void nucleus_enter(void)
422
{
422
{
423
    asm volatile ("wrpr %g0, 1, %tl\n");
423
    asm volatile ("wrpr %g0, 1, %tl\n");
424
}
424
}
425
 
425
 
426
/** Switch from nucleus by setting TL to 0. */
426
/** Switch from nucleus by setting TL to 0. */
427
static inline void nucleus_leave(void)
427
static inline void nucleus_leave(void)
428
{
428
{
429
    asm volatile ("wrpr %g0, %g0, %tl\n");
429
    asm volatile ("wrpr %g0, %g0, %tl\n");
430
}
430
}
431
 
431
 
432
extern void cpu_halt(void);
432
extern void cpu_halt(void);
433
extern void cpu_sleep(void);
433
extern void cpu_sleep(void);
434
extern void asm_delay_loop(const uint32_t usec);
434
extern void asm_delay_loop(const uint32_t usec);
435
 
435
 
436
extern uint64_t read_from_ag_g7(void);
-
 
437
extern void write_to_ag_g6(uint64_t val);
-
 
438
extern void write_to_ag_g7(uint64_t val);
-
 
439
extern void write_to_ig_g6(uint64_t val);
-
 
440
 
-
 
441
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
436
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
442
 
437
 
-
 
438
#if defined(SUN4U)
-
 
439
#include <arch/sun4u/asm.h>
-
 
440
#elif defined (SUN4V)
-
 
441
#include <arch/sun4v/asm.h>
-
 
442
#endif
-
 
443
 
443
#endif
444
#endif
444
 
445
 
445
/** @}
446
/** @}
446
 */
447
 */
447
 
448