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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32mm |
29 | /** @addtogroup mips32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/asid.h> |
36 | #include <mm/asid.h> |
37 | #include <mm/tlb.h> |
37 | #include <mm/tlb.h> |
38 | #include <mm/page.h> |
38 | #include <mm/page.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch/cp0.h> |
40 | #include <arch/cp0.h> |
41 | #include <panic.h> |
41 | #include <panic.h> |
42 | #include <arch.h> |
42 | #include <arch.h> |
43 | #include <symtab.h> |
43 | #include <symtab.h> |
44 | #include <synch/spinlock.h> |
44 | #include <synch/spinlock.h> |
45 | #include <print.h> |
45 | #include <print.h> |
46 | #include <debug.h> |
46 | #include <debug.h> |
47 | #include <align.h> |
47 | #include <align.h> |
48 | #include <interrupt.h> |
48 | #include <interrupt.h> |
49 | 49 | ||
50 | static void tlb_refill_fail(istate_t *istate); |
50 | static void tlb_refill_fail(istate_t *); |
51 | static void tlb_invalid_fail(istate_t *istate); |
51 | static void tlb_invalid_fail(istate_t *); |
52 | static void tlb_modified_fail(istate_t *istate); |
52 | static void tlb_modified_fail(istate_t *); |
53 | 53 | ||
54 | static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc); |
54 | static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *); |
55 | 55 | ||
56 | /** Initialize TLB |
56 | /** Initialize TLB. |
57 | * |
57 | * |
58 | * Initialize TLB. |
- | |
59 | * Invalidate all entries and mark wired entries. |
58 | * Invalidate all entries and mark wired entries. |
60 | */ |
59 | */ |
61 | void tlb_arch_init(void) |
60 | void tlb_arch_init(void) |
62 | { |
61 | { |
63 | int i; |
62 | int i; |
64 | 63 | ||
65 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
64 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
66 | cp0_entry_hi_write(0); |
65 | cp0_entry_hi_write(0); |
67 | cp0_entry_lo0_write(0); |
66 | cp0_entry_lo0_write(0); |
68 | cp0_entry_lo1_write(0); |
67 | cp0_entry_lo1_write(0); |
69 | 68 | ||
70 | /* Clear and initialize TLB. */ |
69 | /* Clear and initialize TLB. */ |
71 | 70 | ||
72 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
71 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
73 | cp0_index_write(i); |
72 | cp0_index_write(i); |
74 | tlbwi(); |
73 | tlbwi(); |
75 | } |
74 | } |
76 | 75 | ||
77 | /* |
76 | /* |
78 | * The kernel is going to make use of some wired |
77 | * The kernel is going to make use of some wired |
79 | * entries (e.g. mapping kernel stacks in kseg3). |
78 | * entries (e.g. mapping kernel stacks in kseg3). |
80 | */ |
79 | */ |
81 | cp0_wired_write(TLB_WIRED); |
80 | cp0_wired_write(TLB_WIRED); |
82 | } |
81 | } |
83 | 82 | ||
84 | /** Process TLB Refill Exception |
83 | /** Process TLB Refill Exception. |
85 | * |
84 | * |
86 | * Process TLB Refill Exception. |
- | |
87 | * |
- | |
88 | * @param istate Interrupted register context. |
85 | * @param istate Interrupted register context. |
89 | */ |
86 | */ |
90 | void tlb_refill(istate_t *istate) |
87 | void tlb_refill(istate_t *istate) |
91 | { |
88 | { |
92 | entry_lo_t lo; |
89 | entry_lo_t lo; |
93 | entry_hi_t hi; |
90 | entry_hi_t hi; |
94 | asid_t asid; |
91 | asid_t asid; |
95 | uintptr_t badvaddr; |
92 | uintptr_t badvaddr; |
96 | pte_t *pte; |
93 | pte_t *pte; |
97 | int pfrc; |
94 | int pfrc; |
98 | 95 | ||
99 | badvaddr = cp0_badvaddr_read(); |
96 | badvaddr = cp0_badvaddr_read(); |
100 | 97 | ||
101 | spinlock_lock(&AS->lock); |
98 | spinlock_lock(&AS->lock); |
102 | asid = AS->asid; |
99 | asid = AS->asid; |
103 | spinlock_unlock(&AS->lock); |
100 | spinlock_unlock(&AS->lock); |
104 | 101 | ||
105 | page_table_lock(AS, true); |
102 | page_table_lock(AS, true); |
106 | 103 | ||
107 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
104 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
108 | if (!pte) { |
105 | if (!pte) { |
109 | switch (pfrc) { |
106 | switch (pfrc) { |
110 | case AS_PF_FAULT: |
107 | case AS_PF_FAULT: |
111 | goto fail; |
108 | goto fail; |
112 | break; |
109 | break; |
113 | case AS_PF_DEFER: |
110 | case AS_PF_DEFER: |
114 | /* |
111 | /* |
115 | * The page fault came during copy_from_uspace() |
112 | * The page fault came during copy_from_uspace() |
116 | * or copy_to_uspace(). |
113 | * or copy_to_uspace(). |
117 | */ |
114 | */ |
118 | page_table_unlock(AS, true); |
115 | page_table_unlock(AS, true); |
119 | return; |
116 | return; |
120 | default: |
117 | default: |
121 | panic("unexpected pfrc (%d)\n", pfrc); |
118 | panic("unexpected pfrc (%d)\n", pfrc); |
122 | } |
119 | } |
123 | } |
120 | } |
124 | 121 | ||
125 | /* |
122 | /* |
126 | * Record access to PTE. |
123 | * Record access to PTE. |
127 | */ |
124 | */ |
128 | pte->a = 1; |
125 | pte->a = 1; |
129 | 126 | ||
130 | tlb_prepare_entry_hi(&hi, asid, badvaddr); |
127 | tlb_prepare_entry_hi(&hi, asid, badvaddr); |
131 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
128 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, |
- | 129 | pte->pfn); |
|
132 | 130 | ||
133 | /* |
131 | /* |
134 | * New entry is to be inserted into TLB |
132 | * New entry is to be inserted into TLB |
135 | */ |
133 | */ |
136 | cp0_entry_hi_write(hi.value); |
134 | cp0_entry_hi_write(hi.value); |
137 | if ((badvaddr/PAGE_SIZE) % 2 == 0) { |
135 | if ((badvaddr / PAGE_SIZE) % 2 == 0) { |
138 | cp0_entry_lo0_write(lo.value); |
136 | cp0_entry_lo0_write(lo.value); |
139 | cp0_entry_lo1_write(0); |
137 | cp0_entry_lo1_write(0); |
140 | } |
138 | } |
141 | else { |
139 | else { |
142 | cp0_entry_lo0_write(0); |
140 | cp0_entry_lo0_write(0); |
143 | cp0_entry_lo1_write(lo.value); |
141 | cp0_entry_lo1_write(lo.value); |
144 | } |
142 | } |
145 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
143 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
146 | tlbwr(); |
144 | tlbwr(); |
147 | 145 | ||
148 | page_table_unlock(AS, true); |
146 | page_table_unlock(AS, true); |
149 | return; |
147 | return; |
150 | 148 | ||
151 | fail: |
149 | fail: |
152 | page_table_unlock(AS, true); |
150 | page_table_unlock(AS, true); |
153 | tlb_refill_fail(istate); |
151 | tlb_refill_fail(istate); |
154 | } |
152 | } |
155 | 153 | ||
156 | /** Process TLB Invalid Exception |
154 | /** Process TLB Invalid Exception. |
157 | * |
- | |
158 | * Process TLB Invalid Exception. |
- | |
159 | * |
155 | * |
160 | * @param istate Interrupted register context. |
156 | * @param istate Interrupted register context. |
161 | */ |
157 | */ |
162 | void tlb_invalid(istate_t *istate) |
158 | void tlb_invalid(istate_t *istate) |
163 | { |
159 | { |
164 | tlb_index_t index; |
160 | tlb_index_t index; |
165 | uintptr_t badvaddr; |
161 | uintptr_t badvaddr; |
166 | entry_lo_t lo; |
162 | entry_lo_t lo; |
167 | entry_hi_t hi; |
163 | entry_hi_t hi; |
168 | pte_t *pte; |
164 | pte_t *pte; |
169 | int pfrc; |
165 | int pfrc; |
170 | 166 | ||
171 | badvaddr = cp0_badvaddr_read(); |
167 | badvaddr = cp0_badvaddr_read(); |
172 | 168 | ||
173 | /* |
169 | /* |
174 | * Locate the faulting entry in TLB. |
170 | * Locate the faulting entry in TLB. |
175 | */ |
171 | */ |
176 | hi.value = cp0_entry_hi_read(); |
172 | hi.value = cp0_entry_hi_read(); |
177 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
173 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
178 | cp0_entry_hi_write(hi.value); |
174 | cp0_entry_hi_write(hi.value); |
179 | tlbp(); |
175 | tlbp(); |
180 | index.value = cp0_index_read(); |
176 | index.value = cp0_index_read(); |
181 | 177 | ||
182 | page_table_lock(AS, true); |
178 | page_table_lock(AS, true); |
183 | 179 | ||
184 | /* |
180 | /* |
185 | * Fail if the entry is not in TLB. |
181 | * Fail if the entry is not in TLB. |
186 | */ |
182 | */ |
187 | if (index.p) { |
183 | if (index.p) { |
188 | printf("TLB entry not found.\n"); |
184 | printf("TLB entry not found.\n"); |
189 | goto fail; |
185 | goto fail; |
190 | } |
186 | } |
191 | 187 | ||
192 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
188 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
193 | if (!pte) { |
189 | if (!pte) { |
194 | switch (pfrc) { |
190 | switch (pfrc) { |
195 | case AS_PF_FAULT: |
191 | case AS_PF_FAULT: |
196 | goto fail; |
192 | goto fail; |
197 | break; |
193 | break; |
198 | case AS_PF_DEFER: |
194 | case AS_PF_DEFER: |
199 | /* |
195 | /* |
200 | * The page fault came during copy_from_uspace() |
196 | * The page fault came during copy_from_uspace() |
201 | * or copy_to_uspace(). |
197 | * or copy_to_uspace(). |
202 | */ |
198 | */ |
203 | page_table_unlock(AS, true); |
199 | page_table_unlock(AS, true); |
204 | return; |
200 | return; |
205 | default: |
201 | default: |
206 | panic("unexpected pfrc (%d)\n", pfrc); |
202 | panic("unexpected pfrc (%d)\n", pfrc); |
207 | } |
203 | } |
208 | } |
204 | } |
209 | 205 | ||
210 | /* |
206 | /* |
211 | * Read the faulting TLB entry. |
207 | * Read the faulting TLB entry. |
212 | */ |
208 | */ |
213 | tlbr(); |
209 | tlbr(); |
214 | 210 | ||
215 | /* |
211 | /* |
216 | * Record access to PTE. |
212 | * Record access to PTE. |
217 | */ |
213 | */ |
218 | pte->a = 1; |
214 | pte->a = 1; |
219 | 215 | ||
220 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
216 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, |
- | 217 | pte->pfn); |
|
221 | 218 | ||
222 | /* |
219 | /* |
223 | * The entry is to be updated in TLB. |
220 | * The entry is to be updated in TLB. |
224 | */ |
221 | */ |
225 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
222 | if ((badvaddr / PAGE_SIZE) % 2 == 0) |
226 | cp0_entry_lo0_write(lo.value); |
223 | cp0_entry_lo0_write(lo.value); |
227 | else |
224 | else |
228 | cp0_entry_lo1_write(lo.value); |
225 | cp0_entry_lo1_write(lo.value); |
229 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
226 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
230 | tlbwi(); |
227 | tlbwi(); |
231 | 228 | ||
232 | page_table_unlock(AS, true); |
229 | page_table_unlock(AS, true); |
233 | return; |
230 | return; |
234 | 231 | ||
235 | fail: |
232 | fail: |
236 | page_table_unlock(AS, true); |
233 | page_table_unlock(AS, true); |
237 | tlb_invalid_fail(istate); |
234 | tlb_invalid_fail(istate); |
238 | } |
235 | } |
239 | 236 | ||
240 | /** Process TLB Modified Exception |
237 | /** Process TLB Modified Exception. |
241 | * |
- | |
242 | * Process TLB Modified Exception. |
- | |
243 | * |
238 | * |
244 | * @param istate Interrupted register context. |
239 | * @param istate Interrupted register context. |
245 | */ |
240 | */ |
246 | void tlb_modified(istate_t *istate) |
241 | void tlb_modified(istate_t *istate) |
247 | { |
242 | { |
248 | tlb_index_t index; |
243 | tlb_index_t index; |
249 | uintptr_t badvaddr; |
244 | uintptr_t badvaddr; |
250 | entry_lo_t lo; |
245 | entry_lo_t lo; |
251 | entry_hi_t hi; |
246 | entry_hi_t hi; |
252 | pte_t *pte; |
247 | pte_t *pte; |
253 | int pfrc; |
248 | int pfrc; |
254 | 249 | ||
255 | badvaddr = cp0_badvaddr_read(); |
250 | badvaddr = cp0_badvaddr_read(); |
256 | 251 | ||
257 | /* |
252 | /* |
258 | * Locate the faulting entry in TLB. |
253 | * Locate the faulting entry in TLB. |
259 | */ |
254 | */ |
260 | hi.value = cp0_entry_hi_read(); |
255 | hi.value = cp0_entry_hi_read(); |
261 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
256 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
262 | cp0_entry_hi_write(hi.value); |
257 | cp0_entry_hi_write(hi.value); |
263 | tlbp(); |
258 | tlbp(); |
264 | index.value = cp0_index_read(); |
259 | index.value = cp0_index_read(); |
265 | 260 | ||
266 | page_table_lock(AS, true); |
261 | page_table_lock(AS, true); |
267 | 262 | ||
268 | /* |
263 | /* |
269 | * Fail if the entry is not in TLB. |
264 | * Fail if the entry is not in TLB. |
270 | */ |
265 | */ |
271 | if (index.p) { |
266 | if (index.p) { |
272 | printf("TLB entry not found.\n"); |
267 | printf("TLB entry not found.\n"); |
273 | goto fail; |
268 | goto fail; |
274 | } |
269 | } |
275 | 270 | ||
276 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
271 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
277 | if (!pte) { |
272 | if (!pte) { |
278 | switch (pfrc) { |
273 | switch (pfrc) { |
279 | case AS_PF_FAULT: |
274 | case AS_PF_FAULT: |
280 | goto fail; |
275 | goto fail; |
281 | break; |
276 | break; |
282 | case AS_PF_DEFER: |
277 | case AS_PF_DEFER: |
283 | /* |
278 | /* |
284 | * The page fault came during copy_from_uspace() |
279 | * The page fault came during copy_from_uspace() |
285 | * or copy_to_uspace(). |
280 | * or copy_to_uspace(). |
286 | */ |
281 | */ |
287 | page_table_unlock(AS, true); |
282 | page_table_unlock(AS, true); |
288 | return; |
283 | return; |
289 | default: |
284 | default: |
290 | panic("unexpected pfrc (%d)\n", pfrc); |
285 | panic("unexpected pfrc (%d)\n", pfrc); |
291 | } |
286 | } |
292 | } |
287 | } |
293 | 288 | ||
294 | /* |
289 | /* |
295 | * Fail if the page is not writable. |
- | |
296 | */ |
- | |
297 | if (!pte->w) |
- | |
298 | goto fail; |
- | |
299 | - | ||
300 | /* |
- | |
301 | * Read the faulting TLB entry. |
290 | * Read the faulting TLB entry. |
302 | */ |
291 | */ |
303 | tlbr(); |
292 | tlbr(); |
304 | 293 | ||
305 | /* |
294 | /* |
306 | * Record access and write to PTE. |
295 | * Record access and write to PTE. |
307 | */ |
296 | */ |
308 | pte->a = 1; |
297 | pte->a = 1; |
309 | pte->d = 1; |
298 | pte->d = 1; |
310 | 299 | ||
311 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); |
300 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, |
- | 301 | pte->pfn); |
|
312 | 302 | ||
313 | /* |
303 | /* |
314 | * The entry is to be updated in TLB. |
304 | * The entry is to be updated in TLB. |
315 | */ |
305 | */ |
316 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
306 | if ((badvaddr / PAGE_SIZE) % 2 == 0) |
317 | cp0_entry_lo0_write(lo.value); |
307 | cp0_entry_lo0_write(lo.value); |
318 | else |
308 | else |
319 | cp0_entry_lo1_write(lo.value); |
309 | cp0_entry_lo1_write(lo.value); |
320 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
310 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
321 | tlbwi(); |
311 | tlbwi(); |
322 | 312 | ||
323 | page_table_unlock(AS, true); |
313 | page_table_unlock(AS, true); |
324 | return; |
314 | return; |
325 | 315 | ||
326 | fail: |
316 | fail: |
327 | page_table_unlock(AS, true); |
317 | page_table_unlock(AS, true); |
328 | tlb_modified_fail(istate); |
318 | tlb_modified_fail(istate); |
329 | } |
319 | } |
330 | 320 | ||
331 | void tlb_refill_fail(istate_t *istate) |
321 | void tlb_refill_fail(istate_t *istate) |
332 | { |
322 | { |
333 | char *symbol = ""; |
323 | char *symbol = ""; |
334 | char *sym2 = ""; |
324 | char *sym2 = ""; |
335 | 325 | ||
336 | char *s = get_symtab_entry(istate->epc); |
326 | char *s = get_symtab_entry(istate->epc); |
337 | if (s) |
327 | if (s) |
338 | symbol = s; |
328 | symbol = s; |
339 | s = get_symtab_entry(istate->ra); |
329 | s = get_symtab_entry(istate->ra); |
340 | if (s) |
330 | if (s) |
341 | sym2 = s; |
331 | sym2 = s; |
342 | 332 | ||
343 | fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read()); |
333 | fault_if_from_uspace(istate, "TLB Refill Exception on %p", |
- | 334 | cp0_badvaddr_read()); |
|
344 | panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2); |
335 | panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), |
- | 336 | istate->epc, symbol, sym2); |
|
345 | } |
337 | } |
346 | 338 | ||
347 | 339 | ||
348 | void tlb_invalid_fail(istate_t *istate) |
340 | void tlb_invalid_fail(istate_t *istate) |
349 | { |
341 | { |
350 | char *symbol = ""; |
342 | char *symbol = ""; |
351 | 343 | ||
352 | char *s = get_symtab_entry(istate->epc); |
344 | char *s = get_symtab_entry(istate->epc); |
353 | if (s) |
345 | if (s) |
354 | symbol = s; |
346 | symbol = s; |
355 | fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read()); |
347 | fault_if_from_uspace(istate, "TLB Invalid Exception on %p", |
- | 348 | cp0_badvaddr_read()); |
|
356 | panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
349 | panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), |
- | 350 | istate->epc, symbol); |
|
357 | } |
351 | } |
358 | 352 | ||
359 | void tlb_modified_fail(istate_t *istate) |
353 | void tlb_modified_fail(istate_t *istate) |
360 | { |
354 | { |
361 | char *symbol = ""; |
355 | char *symbol = ""; |
362 | 356 | ||
363 | char *s = get_symtab_entry(istate->epc); |
357 | char *s = get_symtab_entry(istate->epc); |
364 | if (s) |
358 | if (s) |
365 | symbol = s; |
359 | symbol = s; |
366 | fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read()); |
360 | fault_if_from_uspace(istate, "TLB Modified Exception on %p", |
- | 361 | cp0_badvaddr_read()); |
|
367 | panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
362 | panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), |
- | 363 | istate->epc, symbol); |
|
368 | } |
364 | } |
369 | 365 | ||
370 | /** Try to find PTE for faulting address |
366 | /** Try to find PTE for faulting address. |
371 | * |
367 | * |
372 | * Try to find PTE for faulting address. |
- | |
373 | * The AS->lock must be held on entry to this function. |
368 | * The AS->lock must be held on entry to this function. |
374 | * |
369 | * |
375 | * @param badvaddr Faulting virtual address. |
370 | * @param badvaddr Faulting virtual address. |
376 | * @param access Access mode that caused the fault. |
371 | * @param access Access mode that caused the fault. |
377 | * @param istate Pointer to interrupted state. |
372 | * @param istate Pointer to interrupted state. |
378 | * @param pfrc Pointer to variable where as_page_fault() return code will be stored. |
373 | * @param pfrc Pointer to variable where as_page_fault() return code |
- | 374 | * will be stored. |
|
379 | * |
375 | * |
380 | * @return PTE on success, NULL otherwise. |
376 | * @return PTE on success, NULL otherwise. |
381 | */ |
377 | */ |
- | 378 | pte_t * |
|
382 | pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc) |
379 | find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, |
- | 380 | int *pfrc) |
|
383 | { |
381 | { |
384 | entry_hi_t hi; |
382 | entry_hi_t hi; |
385 | pte_t *pte; |
383 | pte_t *pte; |
386 | 384 | ||
387 | hi.value = cp0_entry_hi_read(); |
385 | hi.value = cp0_entry_hi_read(); |
388 | 386 | ||
389 | /* |
387 | /* |
390 | * Handler cannot succeed if the ASIDs don't match. |
388 | * Handler cannot succeed if the ASIDs don't match. |
391 | */ |
389 | */ |
392 | if (hi.asid != AS->asid) { |
390 | if (hi.asid != AS->asid) { |
393 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
391 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
394 | return NULL; |
392 | return NULL; |
395 | } |
393 | } |
396 | 394 | ||
397 | /* |
395 | /* |
398 | * Check if the mapping exists in page tables. |
396 | * Check if the mapping exists in page tables. |
399 | */ |
397 | */ |
400 | pte = page_mapping_find(AS, badvaddr); |
398 | pte = page_mapping_find(AS, badvaddr); |
401 | if (pte && pte->p) { |
399 | if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) { |
402 | /* |
400 | /* |
403 | * Mapping found in page tables. |
401 | * Mapping found in page tables. |
404 | * Immediately succeed. |
402 | * Immediately succeed. |
405 | */ |
403 | */ |
406 | return pte; |
404 | return pte; |
407 | } else { |
405 | } else { |
408 | int rc; |
406 | int rc; |
409 | 407 | ||
410 | /* |
408 | /* |
411 | * Mapping not found in page tables. |
409 | * Mapping not found in page tables. |
412 | * Resort to higher-level page fault handler. |
410 | * Resort to higher-level page fault handler. |
413 | */ |
411 | */ |
414 | page_table_unlock(AS, true); |
412 | page_table_unlock(AS, true); |
415 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
413 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
416 | case AS_PF_OK: |
414 | case AS_PF_OK: |
417 | /* |
415 | /* |
418 | * The higher-level page fault handler succeeded, |
416 | * The higher-level page fault handler succeeded, |
419 | * The mapping ought to be in place. |
417 | * The mapping ought to be in place. |
420 | */ |
418 | */ |
421 | page_table_lock(AS, true); |
419 | page_table_lock(AS, true); |
422 | pte = page_mapping_find(AS, badvaddr); |
420 | pte = page_mapping_find(AS, badvaddr); |
423 | ASSERT(pte && pte->p); |
421 | ASSERT(pte && pte->p); |
- | 422 | ASSERT(pte->w || access != PF_ACCESS_WRITE); |
|
424 | return pte; |
423 | return pte; |
425 | break; |
424 | break; |
426 | case AS_PF_DEFER: |
425 | case AS_PF_DEFER: |
427 | page_table_lock(AS, true); |
426 | page_table_lock(AS, true); |
428 | *pfrc = AS_PF_DEFER; |
427 | *pfrc = AS_PF_DEFER; |
429 | return NULL; |
428 | return NULL; |
430 | break; |
429 | break; |
431 | case AS_PF_FAULT: |
430 | case AS_PF_FAULT: |
432 | page_table_lock(AS, true); |
431 | page_table_lock(AS, true); |
433 | printf("Page fault.\n"); |
432 | printf("Page fault.\n"); |
434 | *pfrc = AS_PF_FAULT; |
433 | *pfrc = AS_PF_FAULT; |
435 | return NULL; |
434 | return NULL; |
436 | break; |
435 | break; |
437 | default: |
436 | default: |
438 | panic("unexpected rc (%d)\n", rc); |
437 | panic("unexpected rc (%d)\n", rc); |
439 | } |
438 | } |
440 | 439 | ||
441 | } |
440 | } |
442 | } |
441 | } |
443 | 442 | ||
- | 443 | void |
|
444 | void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn) |
444 | tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, |
- | 445 | uintptr_t pfn) |
|
445 | { |
446 | { |
446 | lo->value = 0; |
447 | lo->value = 0; |
447 | lo->g = g; |
448 | lo->g = g; |
448 | lo->v = v; |
449 | lo->v = v; |
449 | lo->d = d; |
450 | lo->d = d; |
450 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
451 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
451 | lo->pfn = pfn; |
452 | lo->pfn = pfn; |
452 | } |
453 | } |
453 | 454 | ||
454 | void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
455 | void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
455 | { |
456 | { |
456 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
457 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
457 | hi->asid = asid; |
458 | hi->asid = asid; |
458 | } |
459 | } |
459 | 460 | ||
460 | /** Print contents of TLB. */ |
461 | /** Print contents of TLB. */ |
461 | void tlb_print(void) |
462 | void tlb_print(void) |
462 | { |
463 | { |
463 | page_mask_t mask; |
464 | page_mask_t mask; |
464 | entry_lo_t lo0, lo1; |
465 | entry_lo_t lo0, lo1; |
465 | entry_hi_t hi, hi_save; |
466 | entry_hi_t hi, hi_save; |
466 | unsigned int i; |
467 | unsigned int i; |
467 | 468 | ||
468 | hi_save.value = cp0_entry_hi_read(); |
469 | hi_save.value = cp0_entry_hi_read(); |
469 | 470 | ||
470 | printf("# ASID VPN2 MASK G V D C PFN\n"); |
471 | printf("# ASID VPN2 MASK G V D C PFN\n"); |
471 | printf("-- ---- ------ ---- - - - - ------\n"); |
472 | printf("-- ---- ------ ---- - - - - ------\n"); |
472 | 473 | ||
473 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
474 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
474 | cp0_index_write(i); |
475 | cp0_index_write(i); |
475 | tlbr(); |
476 | tlbr(); |
476 | 477 | ||
477 | mask.value = cp0_pagemask_read(); |
478 | mask.value = cp0_pagemask_read(); |
478 | hi.value = cp0_entry_hi_read(); |
479 | hi.value = cp0_entry_hi_read(); |
479 | lo0.value = cp0_entry_lo0_read(); |
480 | lo0.value = cp0_entry_lo0_read(); |
480 | lo1.value = cp0_entry_lo1_read(); |
481 | lo1.value = cp0_entry_lo1_read(); |
481 | 482 | ||
482 | printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n", |
483 | printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n", |
483 | i, hi.asid, hi.vpn2, mask.mask, |
484 | i, hi.asid, hi.vpn2, mask.mask, |
484 | lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn); |
485 | lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn); |
485 | printf(" %1u %1u %1u %1u %#6x\n", |
486 | printf(" %1u %1u %1u %1u %#6x\n", |
486 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
487 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
487 | } |
488 | } |
488 | 489 | ||
489 | cp0_entry_hi_write(hi_save.value); |
490 | cp0_entry_hi_write(hi_save.value); |
490 | } |
491 | } |
491 | 492 | ||
492 | /** Invalidate all not wired TLB entries. */ |
493 | /** Invalidate all not wired TLB entries. */ |
493 | void tlb_invalidate_all(void) |
494 | void tlb_invalidate_all(void) |
494 | { |
495 | { |
495 | ipl_t ipl; |
496 | ipl_t ipl; |
496 | entry_lo_t lo0, lo1; |
497 | entry_lo_t lo0, lo1; |
497 | entry_hi_t hi_save; |
498 | entry_hi_t hi_save; |
498 | int i; |
499 | int i; |
499 | 500 | ||
500 | hi_save.value = cp0_entry_hi_read(); |
501 | hi_save.value = cp0_entry_hi_read(); |
501 | ipl = interrupts_disable(); |
502 | ipl = interrupts_disable(); |
502 | 503 | ||
503 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
504 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
504 | cp0_index_write(i); |
505 | cp0_index_write(i); |
505 | tlbr(); |
506 | tlbr(); |
506 | 507 | ||
507 | lo0.value = cp0_entry_lo0_read(); |
508 | lo0.value = cp0_entry_lo0_read(); |
508 | lo1.value = cp0_entry_lo1_read(); |
509 | lo1.value = cp0_entry_lo1_read(); |
509 | 510 | ||
510 | lo0.v = 0; |
511 | lo0.v = 0; |
511 | lo1.v = 0; |
512 | lo1.v = 0; |
512 | 513 | ||
513 | cp0_entry_lo0_write(lo0.value); |
514 | cp0_entry_lo0_write(lo0.value); |
514 | cp0_entry_lo1_write(lo1.value); |
515 | cp0_entry_lo1_write(lo1.value); |
515 | 516 | ||
516 | tlbwi(); |
517 | tlbwi(); |
517 | } |
518 | } |
518 | 519 | ||
519 | interrupts_restore(ipl); |
520 | interrupts_restore(ipl); |
520 | cp0_entry_hi_write(hi_save.value); |
521 | cp0_entry_hi_write(hi_save.value); |
521 | } |
522 | } |
522 | 523 | ||
523 | /** Invalidate all TLB entries belonging to specified address space. |
524 | /** Invalidate all TLB entries belonging to specified address space. |
524 | * |
525 | * |
525 | * @param asid Address space identifier. |
526 | * @param asid Address space identifier. |
526 | */ |
527 | */ |
527 | void tlb_invalidate_asid(asid_t asid) |
528 | void tlb_invalidate_asid(asid_t asid) |
528 | { |
529 | { |
529 | ipl_t ipl; |
530 | ipl_t ipl; |
530 | entry_lo_t lo0, lo1; |
531 | entry_lo_t lo0, lo1; |
531 | entry_hi_t hi, hi_save; |
532 | entry_hi_t hi, hi_save; |
532 | int i; |
533 | int i; |
533 | 534 | ||
534 | ASSERT(asid != ASID_INVALID); |
535 | ASSERT(asid != ASID_INVALID); |
535 | 536 | ||
536 | hi_save.value = cp0_entry_hi_read(); |
537 | hi_save.value = cp0_entry_hi_read(); |
537 | ipl = interrupts_disable(); |
538 | ipl = interrupts_disable(); |
538 | 539 | ||
539 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
540 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
540 | cp0_index_write(i); |
541 | cp0_index_write(i); |
541 | tlbr(); |
542 | tlbr(); |
542 | 543 | ||
543 | hi.value = cp0_entry_hi_read(); |
544 | hi.value = cp0_entry_hi_read(); |
544 | 545 | ||
545 | if (hi.asid == asid) { |
546 | if (hi.asid == asid) { |
546 | lo0.value = cp0_entry_lo0_read(); |
547 | lo0.value = cp0_entry_lo0_read(); |
547 | lo1.value = cp0_entry_lo1_read(); |
548 | lo1.value = cp0_entry_lo1_read(); |
548 | 549 | ||
549 | lo0.v = 0; |
550 | lo0.v = 0; |
550 | lo1.v = 0; |
551 | lo1.v = 0; |
551 | 552 | ||
552 | cp0_entry_lo0_write(lo0.value); |
553 | cp0_entry_lo0_write(lo0.value); |
553 | cp0_entry_lo1_write(lo1.value); |
554 | cp0_entry_lo1_write(lo1.value); |
554 | 555 | ||
555 | tlbwi(); |
556 | tlbwi(); |
556 | } |
557 | } |
557 | } |
558 | } |
558 | 559 | ||
559 | interrupts_restore(ipl); |
560 | interrupts_restore(ipl); |
560 | cp0_entry_hi_write(hi_save.value); |
561 | cp0_entry_hi_write(hi_save.value); |
561 | } |
562 | } |
562 | 563 | ||
563 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
564 | /** Invalidate TLB entries for specified page range belonging to specified |
- | 565 | * address space. |
|
564 | * |
566 | * |
565 | * @param asid Address space identifier. |
567 | * @param asid Address space identifier. |
566 | * @param page First page whose TLB entry is to be invalidated. |
568 | * @param page First page whose TLB entry is to be invalidated. |
567 | * @param cnt Number of entries to invalidate. |
569 | * @param cnt Number of entries to invalidate. |
568 | */ |
570 | */ |
569 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
571 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
570 | { |
572 | { |
571 | unsigned int i; |
573 | unsigned int i; |
572 | ipl_t ipl; |
574 | ipl_t ipl; |
573 | entry_lo_t lo0, lo1; |
575 | entry_lo_t lo0, lo1; |
574 | entry_hi_t hi, hi_save; |
576 | entry_hi_t hi, hi_save; |
575 | tlb_index_t index; |
577 | tlb_index_t index; |
576 | 578 | ||
577 | ASSERT(asid != ASID_INVALID); |
579 | ASSERT(asid != ASID_INVALID); |
578 | 580 | ||
579 | hi_save.value = cp0_entry_hi_read(); |
581 | hi_save.value = cp0_entry_hi_read(); |
580 | ipl = interrupts_disable(); |
582 | ipl = interrupts_disable(); |
581 | 583 | ||
582 | for (i = 0; i < cnt + 1; i += 2) { |
584 | for (i = 0; i < cnt + 1; i += 2) { |
583 | hi.value = 0; |
585 | hi.value = 0; |
584 | tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
586 | tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
585 | cp0_entry_hi_write(hi.value); |
587 | cp0_entry_hi_write(hi.value); |
586 | 588 | ||
587 | tlbp(); |
589 | tlbp(); |
588 | index.value = cp0_index_read(); |
590 | index.value = cp0_index_read(); |
589 | 591 | ||
590 | if (!index.p) { |
592 | if (!index.p) { |
- | 593 | /* |
|
591 | /* Entry was found, index register contains valid index. */ |
594 | * Entry was found, index register contains valid |
- | 595 | * index. |
|
- | 596 | */ |
|
592 | tlbr(); |
597 | tlbr(); |
593 | 598 | ||
594 | lo0.value = cp0_entry_lo0_read(); |
599 | lo0.value = cp0_entry_lo0_read(); |
595 | lo1.value = cp0_entry_lo1_read(); |
600 | lo1.value = cp0_entry_lo1_read(); |
596 | 601 | ||
597 | lo0.v = 0; |
602 | lo0.v = 0; |
598 | lo1.v = 0; |
603 | lo1.v = 0; |
599 | 604 | ||
600 | cp0_entry_lo0_write(lo0.value); |
605 | cp0_entry_lo0_write(lo0.value); |
601 | cp0_entry_lo1_write(lo1.value); |
606 | cp0_entry_lo1_write(lo1.value); |
602 | 607 | ||
603 | tlbwi(); |
608 | tlbwi(); |
604 | } |
609 | } |
605 | } |
610 | } |
606 | 611 | ||
607 | interrupts_restore(ipl); |
612 | interrupts_restore(ipl); |
608 | cp0_entry_hi_write(hi_save.value); |
613 | cp0_entry_hi_write(hi_save.value); |
609 | } |
614 | } |
610 | 615 | ||
611 | /** @} |
616 | /** @} |
612 | */ |
617 | */ |
613 | 618 |