WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/ia32/include/atomic.h


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia32_ATOMIC_H_
#define KERN_ia32_ATOMIC_H_
 
#include <arch/types.h>
#include <arch/barrier.h>
#include <preemption.h>
 
static inline void atomic_inc(atomic_t *val) {
#ifdef CONFIG_SMP
    asm volatile ("lock incl %0\n" : "+m" (val->count));
#else
    asm volatile ("incl %0\n" : "+m" (val->count));
#endif /* CONFIG_SMP */
}
 
static inline void atomic_dec(atomic_t *val) {
#ifdef CONFIG_SMP
    asm volatile ("lock decl %0\n" : "+m" (val->count));
#else
    asm volatile ("decl %0\n" : "+m" (val->count));
#endif /* CONFIG_SMP */
}
 
static inline long atomic_postinc(atomic_t *val)
{
    long r = 1;
 
    asm volatile (
        "lock xaddl %1, %0\n"
        : "+m" (val->count), "+r" (r)
    );
 
    return r;
}
 
static inline long atomic_postdec(atomic_t *val)
{
    long r = -1;
   
    asm volatile (
        "lock xaddl %1, %0\n"
        : "+m" (val->count), "+r"(r)
    );
   
    return r;
}
 
#define atomic_preinc(val) (atomic_postinc(val) + 1)
#define atomic_predec(val) (atomic_postdec(val) - 1)
 
static inline uint32_t test_and_set(atomic_t *val) {
    uint32_t v;
   
    asm volatile (
        "movl $1, %0\n"
        "xchgl %0, %1\n"
        : "=r" (v),"+m" (val->count)
    );
   
    return v;
}
 
/** ia32 specific fast spinlock */
static inline void atomic_lock_arch(atomic_t *val)
{
    uint32_t tmp;
 
    preemption_disable();
    asm volatile (
        "0:\n"
#ifdef CONFIG_HT
        "pause\n" /* Pentium 4's HT love this instruction */
#endif
        "mov %0, %1\n"
        "testl %1, %1\n"
        "jnz 0b\n"       /* lightweight looping on locked spinlock */
       
        "incl %1\n"      /* now use the atomic operation */
        "xchgl %0, %1\n"   
        "testl %1, %1\n"
        "jnz 0b\n"
                : "+m" (val->count), "=&r"(tmp)
    );
    /*
     * Prevent critical section code from bleeding out this way up.
     */
    CS_ENTER_BARRIER();
}
 
#endif
 
/** @}
 */
 

Rev 3343	Rev 3397
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia32_ATOMIC_H_	35	#ifndef KERN_ia32_ATOMIC_H_
36	#define KERN_ia32_ATOMIC_H_	36	#define KERN_ia32_ATOMIC_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
39	#include <arch/barrier.h>	39	#include <arch/barrier.h>
40	#include <preemption.h>	40	#include <preemption.h>
41		41
42	static inline void atomic_inc(atomic_t *val) {	42	static inline void atomic_inc(atomic_t *val) {
43	#ifdef CONFIG_SMP	43	#ifdef CONFIG_SMP
44	asm volatile ("lock incl %0\n" : "+m" (val->count));	44	asm volatile ("lock incl %0\n" : "+m" (val->count));
45	#else	45	#else
46	asm volatile ("incl %0\n" : "+m" (val->count));	46	asm volatile ("incl %0\n" : "+m" (val->count));
47	#endif /* CONFIG_SMP */	47	#endif /* CONFIG_SMP */
48	}	48	}
49		49
50	static inline void atomic_dec(atomic_t *val) {	50	static inline void atomic_dec(atomic_t *val) {
51	#ifdef CONFIG_SMP	51	#ifdef CONFIG_SMP
52	asm volatile ("lock decl %0\n" : "+m" (val->count));	52	asm volatile ("lock decl %0\n" : "+m" (val->count));
53	#else	53	#else
54	asm volatile ("decl %0\n" : "+m" (val->count));	54	asm volatile ("decl %0\n" : "+m" (val->count));
55	#endif /* CONFIG_SMP */	55	#endif /* CONFIG_SMP */
56	}	56	}
57		57
58	static inline long atomic_postinc(atomic_t *val)	58	static inline long atomic_postinc(atomic_t *val)
59	{	59	{
60	long r = 1;	60	long r = 1;
61		61
62	asm volatile (	62	asm volatile (
63	"lock xaddl %1, %0\n"	63	"lock xaddl %1, %0\n"
64	: "+m" (val->count), "+r" (r)	64	: "+m" (val->count), "+r" (r)
65	);	65	);
66		66
67	return r;	67	return r;
68	}	68	}
69		69
70	static inline long atomic_postdec(atomic_t *val)	70	static inline long atomic_postdec(atomic_t *val)
71	{	71	{
72	long r = -1;	72	long r = -1;
73		73
74	asm volatile (	74	asm volatile (
75	"lock xaddl %1, %0\n"	75	"lock xaddl %1, %0\n"
76	: "+m" (val->count), "+r"(r)	76	: "+m" (val->count), "+r"(r)
77	);	77	);
78		78
79	return r;	79	return r;
80	}	80	}
81		81
82	#define atomic_preinc(val) (atomic_postinc(val) + 1)	82	#define atomic_preinc(val) (atomic_postinc(val) + 1)
83	#define atomic_predec(val) (atomic_postdec(val) - 1)	83	#define atomic_predec(val) (atomic_postdec(val) - 1)
84		84
85	static inline uint32_t test_and_set(atomic_t *val) {	85	static inline uint32_t test_and_set(atomic_t *val) {
86	uint32_t v;	86	uint32_t v;
87		87
88	asm volatile (	88	asm volatile (
89	"movl $1, %0\n"	89	"movl $1, %0\n"
90	"xchgl %0, %1\n"	90	"xchgl %0, %1\n"
91	: "=r" (v),"+m" (val->count)	91	: "=r" (v),"+m" (val->count)
92	);	92	);
93		93
94	return v;	94	return v;
95	}	95	}
96		96
97	/** ia32 specific fast spinlock */	97	/** ia32 specific fast spinlock */
98	static inline void atomic_lock_arch(atomic_t *val)	98	static inline void atomic_lock_arch(atomic_t *val)
99	{	99	{
100	uint32_t tmp;	100	uint32_t tmp;
101		101
102	preemption_disable();	102	preemption_disable();
103	asm volatile (	103	asm volatile (
104	"0:\n"	104	"0:\n"
105	#ifdef CONFIG_HT	105	#ifdef CONFIG_HT
106	"pause\n" /* Pentium 4's HT love this instruction */	106	"pause\n" /* Pentium 4's HT love this instruction */
107	#endif	107	#endif
108	"mov %0, %1\n"	108	"mov %0, %1\n"
109	"testl %1, %1\n"	109	"testl %1, %1\n"
110	"jnz 0b\n" /* lightweight looping on locked spinlock */	110	"jnz 0b\n" /* lightweight looping on locked spinlock */
111		111
112	"incl %1\n" /* now use the atomic operation */	112	"incl %1\n" /* now use the atomic operation */
113	"xchgl %0, %1\n"	113	"xchgl %0, %1\n"
114	"testl %1, %1\n"	114	"testl %1, %1\n"
115	"jnz 0b\n"	115	"jnz 0b\n"
116	: "+m" (val->count), "=r"(tmp)	116	: "+m" (val->count), "=&r"(tmp)
117	);	117	);
118	/*	118	/*
119	* Prevent critical section code from bleeding out this way up.	119	* Prevent critical section code from bleeding out this way up.
120	*/	120	*/
121	CS_ENTER_BARRIER();	121	CS_ENTER_BARRIER();
122	}	122	}
123		123
124	#endif	124	#endif
125		125
126	/** @}	126	/** @}
127	*/	127	*/
128		128

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(root)/branches/sparc/kernel/arch/ia32/include/atomic.h – Rev 3343 → 3397