WebSVN – HelenOS – Diff – /branches/sparc/boot/arch/sparc64/loader/asm.S


#
# Copyright (c) 2006 Martin Decky
# Copyright (c) 2006 Jakub Jermar 
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <stack.h>
#include <register.h>
 
.register       %g2, #scratch
.register       %g3, #scratch
 
.text
 
.global halt
.global memcpy
.global jump_to_kernel
 
halt:
	b halt
	nop
	
memcpy:
	mov	%o0, %o3		! save dst
	add	%o1, 7, %g1
	and	%g1, -8, %g1
	cmp	%o1, %g1
	be,pn	%xcc, 3f
	add	%o0, 7, %g1
	mov	0, %g3
0:
	brz,pn	%o2, 2f
	mov	0, %g2
1:
	ldub	[%g3 + %o1], %g1
	add	%g2, 1, %g2
	cmp	%o2, %g2
	stb	%g1, [%g3 + %o0]
	bne,pt	%xcc, 1b
	mov	%g2, %g3
2:
	jmp	%o7 + 8			! exit point
	mov	%o3, %o0
3:
	and	%g1, -8, %g1
	cmp	%o0, %g1
	bne,pt	%xcc, 0b
	mov	0, %g3
	srlx	%o2, 3, %g4
	brz,pn	%g4, 5f
	mov	0, %g5
4:
	sllx	%g3, 3, %g2
	add	%g5, 1, %g3
	ldx	[%o1 + %g2], %g1
	mov	%g3, %g5
	cmp	%g4, %g3
	bne,pt	%xcc, 4b
	stx	%g1, [%o0 + %g2]
5:
	and	%o2, 7, %o2
	brz,pn	%o2, 2b
	sllx	%g4, 3, %g1
	mov	0, %g2
	add	%g1, %o0, %o0
	add	%g1, %o1, %g4
	mov	0, %g3
6:
	ldub	[%g2 + %g4], %g1
	stb	%g1, [%g2 + %o0]
	add	%g3, 1, %g2
	cmp	%o2, %g2
	bne,pt	%xcc, 6b
	mov	%g2, %g3
 
	jmp	%o7 + 8			! exit point
	mov	%o3, %o0
 
jump_to_kernel:
	/*
	 * We have copied code and now we need to guarantee cache coherence.
	 * 1. Make sure that the code we have moved has drained to main memory.
	 * 2. Invalidate I-cache.
	 * 3. Flush instruction pipeline.
	 */
 
	/*
	 * US3 processors have a write-invalidate cache, so explicitly
	 * invalidating it is not required. Whether to invalidate I-cache
	 * or not is decided according to the value of the ver.impl bits
	 * in the Version register.
	 */
 
! the lowest/greatest value of ver.impl for US3
#define FIRST_US3_CPU 0x14
#define LAST_US3_CPU 0x19
	rdpr %ver, %g2			! autodetect CPU using the Version register
	sllx %g2, 16, %g2		! extract ver.impl bits
	srlx %g2, 48, %g2
	addcc %g2, -FIRST_US3_CPU, %g0	! flush if ver.impl < FISRT_US3_CPU
	bl 0f
	nop
	addcc %g2, -LAST_US3_CPU, %g0	! flush if ver.impl > LAST_US3_CPU
	bg 0f
	nop
	ba 1f
	nop
0:
	call icache_flush
	nop
1:
	
	membar #StoreStore
	
	/*
	 * Flush the instruction pipeline.
	 */
	flush	%i7
 
	mov %o0, %l1
	mov %o1, %o0
	mov %o2, %o1
	mov %o3, %o2
	jmp %l1				! jump to kernel
	nop
 
#define ICACHE_SIZE		8192
#define ICACHE_LINE_SIZE	32
#define ICACHE_SET_BIT		(1 << 13)
#define ASI_ICACHE_TAG		0x67
 
# Flush I-cache
icache_flush:
	set	((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
	stxa	%g0, [%g1] ASI_ICACHE_TAG
0:	membar	#Sync
	subcc	%g1, ICACHE_LINE_SIZE, %g1
	bnz,pt	%xcc, 0b
	stxa	%g0, [%g1] ASI_ICACHE_TAG
	membar	#Sync
	retl
	! SF Erratum #51
	nop
.global ofw
ofw:
	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
	set ofw_cif, %l0
	ldx [%l0], %l0
 
	rdpr  %pstate, %l1
	and  %l1, ~PSTATE_AM_BIT, %l2
	wrpr  %l2, 0, %pstate
    
	jmpl %l0, %o7
	mov %i0, %o0
 
	wrpr %l1, 0, %pstate
 
	ret
	restore %o0, 0, %o0
 

Rev 3479	Rev 3549
1	#	1	#
2	# Copyright (c) 2006 Martin Decky	2	# Copyright (c) 2006 Martin Decky
3	# Copyright (c) 2006 Jakub Jermar	3	# Copyright (c) 2006 Jakub Jermar
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <stack.h>	30	#include <stack.h>
31	#include <register.h>	31	#include <register.h>
32		32
33	.register %g2, #scratch	33	.register %g2, #scratch
34	.register %g3, #scratch	34	.register %g3, #scratch
35		35
36	.text	36	.text
37		37
38	.global halt	38	.global halt
39	.global memcpy	39	.global memcpy
40	.global jump_to_kernel	40	.global jump_to_kernel
41		41
42	halt:	42	halt:
43	b halt	43	b halt
44	nop	44	nop
45		45
46	memcpy:	46	memcpy:
47	mov %o0, %o3 ! save dst	47	mov %o0, %o3 ! save dst
48	add %o1, 7, %g1	48	add %o1, 7, %g1
49	and %g1, -8, %g1	49	and %g1, -8, %g1
50	cmp %o1, %g1	50	cmp %o1, %g1
51	be,pn %xcc, 3f	51	be,pn %xcc, 3f
52	add %o0, 7, %g1	52	add %o0, 7, %g1
53	mov 0, %g3	53	mov 0, %g3
54	0:	54	0:
55	brz,pn %o2, 2f	55	brz,pn %o2, 2f
56	mov 0, %g2	56	mov 0, %g2
57	1:	57	1:
58	ldub [%g3 + %o1], %g1	58	ldub [%g3 + %o1], %g1
59	add %g2, 1, %g2	59	add %g2, 1, %g2
60	cmp %o2, %g2	60	cmp %o2, %g2
61	stb %g1, [%g3 + %o0]	61	stb %g1, [%g3 + %o0]
62	bne,pt %xcc, 1b	62	bne,pt %xcc, 1b
63	mov %g2, %g3	63	mov %g2, %g3
64	2:	64	2:
65	jmp %o7 + 8 ! exit point	65	jmp %o7 + 8 ! exit point
66	mov %o3, %o0	66	mov %o3, %o0
67	3:	67	3:
68	and %g1, -8, %g1	68	and %g1, -8, %g1
69	cmp %o0, %g1	69	cmp %o0, %g1
70	bne,pt %xcc, 0b	70	bne,pt %xcc, 0b
71	mov 0, %g3	71	mov 0, %g3
72	srlx %o2, 3, %g4	72	srlx %o2, 3, %g4
73	brz,pn %g4, 5f	73	brz,pn %g4, 5f
74	mov 0, %g5	74	mov 0, %g5
75	4:	75	4:
76	sllx %g3, 3, %g2	76	sllx %g3, 3, %g2
77	add %g5, 1, %g3	77	add %g5, 1, %g3
78	ldx [%o1 + %g2], %g1	78	ldx [%o1 + %g2], %g1
79	mov %g3, %g5	79	mov %g3, %g5
80	cmp %g4, %g3	80	cmp %g4, %g3
81	bne,pt %xcc, 4b	81	bne,pt %xcc, 4b
82	stx %g1, [%o0 + %g2]	82	stx %g1, [%o0 + %g2]
83	5:	83	5:
84	and %o2, 7, %o2	84	and %o2, 7, %o2
85	brz,pn %o2, 2b	85	brz,pn %o2, 2b
86	sllx %g4, 3, %g1	86	sllx %g4, 3, %g1
87	mov 0, %g2	87	mov 0, %g2
88	add %g1, %o0, %o0	88	add %g1, %o0, %o0
89	add %g1, %o1, %g4	89	add %g1, %o1, %g4
90	mov 0, %g3	90	mov 0, %g3
91	6:	91	6:
92	ldub [%g2 + %g4], %g1	92	ldub [%g2 + %g4], %g1
93	stb %g1, [%g2 + %o0]	93	stb %g1, [%g2 + %o0]
94	add %g3, 1, %g2	94	add %g3, 1, %g2
95	cmp %o2, %g2	95	cmp %o2, %g2
96	bne,pt %xcc, 6b	96	bne,pt %xcc, 6b
97	mov %g2, %g3	97	mov %g2, %g3
98		98
99	jmp %o7 + 8 ! exit point	99	jmp %o7 + 8 ! exit point
100	mov %o3, %o0	100	mov %o3, %o0
101		101
102	jump_to_kernel:	102	jump_to_kernel:
103	/*	103	/*
104	* We have copied code and now we need to guarantee cache coherence.	104	* We have copied code and now we need to guarantee cache coherence.
105	* 1. Make sure that the code we have moved has drained to main memory.	105	* 1. Make sure that the code we have moved has drained to main memory.
106	* 2. Invalidate I-cache.	106	* 2. Invalidate I-cache.
107	* 3. Flush instruction pipeline.	107	* 3. Flush instruction pipeline.
108	*/	108	*/
109		109
110	/*	110	/*
111	* US3 processors have a write-invalidate cache, so explicitly	111	* US3 processors have a write-invalidate cache, so explicitly
112	* invalidating it is not required. Whether to invalidate I-cache	112	* invalidating it is not required. Whether to invalidate I-cache
113	* or not is decided according to the value of the ver.impl bits	113	* or not is decided according to the value of the ver.impl bits
114	* in the Version register.	114	* in the Version register.
115	*/	115	*/
116	sethi 0x40000, %g0	-
117	! the lowest/greatest value of ver.impl for US3	116	! the lowest/greatest value of ver.impl for US3
118	#define FIRST_US3_CPU 0x14	117	#define FIRST_US3_CPU 0x14
119	#define LAST_US3_CPU 0x19	118	#define LAST_US3_CPU 0x19
120	rdpr %ver, %g2 ! autodetect CPU using the Version register	119	rdpr %ver, %g2 ! autodetect CPU using the Version register
121	sllx %g2, 16, %g2 ! extract ver.impl bits	120	sllx %g2, 16, %g2 ! extract ver.impl bits
122	srlx %g2, 48, %g2	121	srlx %g2, 48, %g2
123	addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU	122	addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU
124	bl 0f	123	bl 0f
125	nop	124	nop
126	addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU	125	addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU
127	bg 0f	126	bg 0f
128	nop	127	nop
129	ba 1f	128	ba 1f
130	nop	129	nop
131	0:	130	0:
132	call icache_flush	131	call icache_flush
133	nop	132	nop
134	1:	133	1:
135		134
136	membar #StoreStore	135	membar #StoreStore
137		136
138	/*	137	/*
139	* Flush the instruction pipeline.	138	* Flush the instruction pipeline.
140	*/	139	*/
141	flush %i7	140	flush %i7
142		141
143	mov %o0, %l1	142	mov %o0, %l1
144	mov %o1, %o0	143	mov %o1, %o0
145	mov %o2, %o1	144	mov %o2, %o1
146	mov %o3, %o2	145	mov %o3, %o2
147	jmp %l1 ! jump to kernel	146	jmp %l1 ! jump to kernel
148	nop	147	nop
149		148
150	#define ICACHE_SIZE 8192	149	#define ICACHE_SIZE 8192
151	#define ICACHE_LINE_SIZE 32	150	#define ICACHE_LINE_SIZE 32
152	#define ICACHE_SET_BIT (1 << 13)	151	#define ICACHE_SET_BIT (1 << 13)
153	#define ASI_ICACHE_TAG 0x67	152	#define ASI_ICACHE_TAG 0x67
154		153
155	# Flush I-cache	154	# Flush I-cache
156	icache_flush:	155	icache_flush:
157	set ((ICACHE_SIZE - ICACHE_LINE_SIZE) \| ICACHE_SET_BIT), %g1	156	set ((ICACHE_SIZE - ICACHE_LINE_SIZE) \| ICACHE_SET_BIT), %g1
158	stxa %g0, [%g1] ASI_ICACHE_TAG	157	stxa %g0, [%g1] ASI_ICACHE_TAG
159	0: membar #Sync	158	0: membar #Sync
160	subcc %g1, ICACHE_LINE_SIZE, %g1	159	subcc %g1, ICACHE_LINE_SIZE, %g1
161	bnz,pt %xcc, 0b	160	bnz,pt %xcc, 0b
162	stxa %g0, [%g1] ASI_ICACHE_TAG	161	stxa %g0, [%g1] ASI_ICACHE_TAG
163	membar #Sync	162	membar #Sync
164	retl	163	retl
165	! SF Erratum #51	164	! SF Erratum #51
166	nop	165	nop
167	.global ofw	166	.global ofw
168	ofw:	167	ofw:
169	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp	168	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
170	set ofw_cif, %l0	169	set ofw_cif, %l0
171	ldx [%l0], %l0	170	ldx [%l0], %l0
172		171
173	rdpr %pstate, %l1	172	rdpr %pstate, %l1
174	and %l1, ~PSTATE_AM_BIT, %l2	173	and %l1, ~PSTATE_AM_BIT, %l2
175	wrpr %l2, 0, %pstate	174	wrpr %l2, 0, %pstate
176		175
177	jmpl %l0, %o7	176	jmpl %l0, %o7
178	mov %i0, %o0	177	mov %i0, %o0
179		178
180	wrpr %l1, 0, %pstate	179	wrpr %l1, 0, %pstate
181		180
182	ret	181	ret
183	restore %o0, 0, %o0	182	restore %o0, 0, %o0
184		183

Subversion Repositories HelenOS

(root)/branches/sparc/boot/arch/sparc64/loader/asm.S @ 3582 – Rev 3479 → 3549