WebSVN – HelenOS – Diff – /branches/snapshot/kernel/genarch/src/drivers/i8042/i8042.c


/*
 * Copyright (c) 2009 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup genarch
 * @{
 */
/**
 * @file
 * @brief i8042 processor driver
 *
 * It takes care of the i8042 serial communication.
 *
 */
 
#include <genarch/drivers/i8042/i8042.h>
#include <genarch/drivers/legacy/ia32/io.h>
#include <arch/asm.h>
#include <console/chardev.h>
#include <mm/slab.h>
#include <ddi/device.h>
 
#define i8042_SET_COMMAND  0x60
#define i8042_COMMAND      0x69
#define i8042_CPU_RESET    0xfe
 
#define i8042_BUFFER_FULL_MASK  0x01
#define i8042_WAIT_MASK         0x02
 
static irq_ownership_t i8042_claim(irq_t *irq)
{
    i8042_instance_t *i8042_instance = irq->instance;
    i8042_t *dev = i8042_instance->i8042;
   
    if (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
        return IRQ_ACCEPT;
    else
        return IRQ_DECLINE;
}
 
static void i8042_irq_handler(irq_t *irq)
{
    i8042_instance_t *instance = irq->instance;
    i8042_t *dev = instance->i8042;
    uint8_t status;
   
    if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) {
        uint8_t data = pio_read_8(&dev->data);
        indev_push_character(instance->kbrdin, data);
    }
}
 
/**< Clear input buffer. */
static void i8042_clear_buffer(i8042_t *dev)
{
    while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
        (void) pio_read_8(&dev->data);
}
 
/** Initialize i8042. */
i8042_instance_t *i8042_init(i8042_t *dev, inr_t inr)
{
    i8042_instance_t *instance
        = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC);
    if (instance) {
        instance->i8042 = dev;
        instance->kbrdin = NULL;
       
        irq_initialize(&instance->irq);
        instance->irq.devno = device_assign_devno();
        instance->irq.inr = inr;
        instance->irq.claim = i8042_claim;
        instance->irq.handler = i8042_irq_handler;
        instance->irq.instance = instance;
       
    }
   
    return instance;
}
 
void i8042_wire(i8042_instance_t *instance, indev_t *kbrdin)
{
    ASSERT(instance);
    ASSERT(kbrdin);
   
    instance->kbrdin = kbrdin;
    irq_register(&instance->irq);
    i8042_clear_buffer(instance->i8042);
}
 
/* Reset CPU by pulsing pin 0 */
void i8042_cpu_reset(i8042_t *dev)
{
    interrupts_disable();
   
    i8042_clear_buffer(dev);
   
    /* Reset CPU */
    pio_write_8(&dev->status, i8042_CPU_RESET);
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/snapshot/kernel/genarch/src/drivers/i8042/i8042.c – Rev 4311 → 4605

Rev 4311		Rev 4605
1	/*	1	/*
2	* Copyright (c) 2009 Jakub Jermar	2	* Copyright (c) 2009 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup genarch	29	/** @addtogroup genarch
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief i8042 processor driver	34	* @brief i8042 processor driver
35	*	35	*
36	* It takes care of the i8042 serial communication.	36	* It takes care of the i8042 serial communication.
37	*	37	*
38	*/	38	*/
39		39
40	#include <genarch/drivers/i8042/i8042.h>	40	#include <genarch/drivers/i8042/i8042.h>
41	#include <genarch/drivers/legacy/ia32/io.h>	41	#include <genarch/drivers/legacy/ia32/io.h>
42	#include <arch/asm.h>	42	#include <arch/asm.h>
43	#include <console/chardev.h>	43	#include <console/chardev.h>
44	#include <mm/slab.h>	44	#include <mm/slab.h>
45	#include <ddi/device.h>	45	#include <ddi/device.h>
46		46
47	#define i8042_SET_COMMAND 0x60	47	#define i8042_SET_COMMAND 0x60
48	#define i8042_COMMAND 0x69	48	#define i8042_COMMAND 0x69
49	#define i8042_CPU_RESET 0xfe	49	#define i8042_CPU_RESET 0xfe
50		50
51	#define i8042_BUFFER_FULL_MASK 0x01	51	#define i8042_BUFFER_FULL_MASK 0x01
52	#define i8042_WAIT_MASK 0x02	52	#define i8042_WAIT_MASK 0x02
53		53
54	static irq_ownership_t i8042_claim(irq_t *irq)	54	static irq_ownership_t i8042_claim(irq_t *irq)
55	{	55	{
56	i8042_instance_t *i8042_instance = irq->instance;	56	i8042_instance_t *i8042_instance = irq->instance;
57	i8042_t *dev = i8042_instance->i8042;	57	i8042_t *dev = i8042_instance->i8042;
58		58
59	if (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)	59	if (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
60	return IRQ_ACCEPT;	60	return IRQ_ACCEPT;
61	else	61	else
62	return IRQ_DECLINE;	62	return IRQ_DECLINE;
63	}	63	}
64		64
65	static void i8042_irq_handler(irq_t *irq)	65	static void i8042_irq_handler(irq_t *irq)
66	{	66	{
67	i8042_instance_t *instance = irq->instance;	67	i8042_instance_t *instance = irq->instance;
68	i8042_t *dev = instance->i8042;	68	i8042_t *dev = instance->i8042;
69	uint8_t status;	69	uint8_t status;
70		70
71	if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) {	71	if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) {
72	uint8_t data = pio_read_8(&dev->data);	72	uint8_t data = pio_read_8(&dev->data);
73	indev_push_character(instance->kbrdin, data);	73	indev_push_character(instance->kbrdin, data);
74	}	74	}
75	}	75	}
76		76
77	/*< Clear input buffer. /	77	/*< Clear input buffer. /
78	static void i8042_clear_buffer(i8042_t *dev)	78	static void i8042_clear_buffer(i8042_t *dev)
79	{	79	{
80	while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)	80	while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
81	(void) pio_read_8(&dev->data);	81	(void) pio_read_8(&dev->data);
82	}	82	}
83		83
84	/** Initialize i8042. */	84	/** Initialize i8042. */
85	i8042_instance_t i8042_init(i8042_t dev, inr_t inr)	85	i8042_instance_t i8042_init(i8042_t dev, inr_t inr)
86	{	86	{
87	i8042_instance_t *instance	87	i8042_instance_t *instance
88	= malloc(sizeof(i8042_instance_t), FRAME_ATOMIC);	88	= malloc(sizeof(i8042_instance_t), FRAME_ATOMIC);
89	if (instance) {	89	if (instance) {
90	instance->i8042 = dev;	90	instance->i8042 = dev;
91	instance->kbrdin = NULL;	91	instance->kbrdin = NULL;
92		92
93	irq_initialize(&instance->irq);	93	irq_initialize(&instance->irq);
94	instance->irq.devno = device_assign_devno();	94	instance->irq.devno = device_assign_devno();
95	instance->irq.inr = inr;	95	instance->irq.inr = inr;
96	instance->irq.claim = i8042_claim;	96	instance->irq.claim = i8042_claim;
97	instance->irq.handler = i8042_irq_handler;	97	instance->irq.handler = i8042_irq_handler;
98	instance->irq.instance = instance;	98	instance->irq.instance = instance;
99		99
100	}	100	}
101		101
102	return instance;	102	return instance;
103	}	103	}
104		104
105	void i8042_wire(i8042_instance_t instance, indev_t kbrdin)	105	void i8042_wire(i8042_instance_t instance, indev_t kbrdin)
106	{	106	{
107	ASSERT(instance);	107	ASSERT(instance);
108	ASSERT(kbrdin);	108	ASSERT(kbrdin);
109		109
110	instance->kbrdin = kbrdin;	110	instance->kbrdin = kbrdin;
111	irq_register(&instance->irq);	111	irq_register(&instance->irq);
112	i8042_clear_buffer(instance->i8042);	112	i8042_clear_buffer(instance->i8042);
113	}	113	}
114		114
115	/* Reset CPU by pulsing pin 0 */	115	/* Reset CPU by pulsing pin 0 */
116	void i8042_cpu_reset(i8042_t *dev)	116	void i8042_cpu_reset(i8042_t *dev)
117	{	117	{
118	interrupts_disable();	118	interrupts_disable();
119		119
120	i8042_clear_buffer(dev);	120	i8042_clear_buffer(dev);
121		121
122	/* Reset CPU */	122	/* Reset CPU */
123	pio_write_8(&dev->status, i8042_CPU_RESET);	123	pio_write_8(&dev->status, i8042_CPU_RESET);
124	}	124	}
125		125
126	/** @}	126	/** @}
127	*/	127	*/
128		128