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1 | /* |
1 | /* |
2 | * Copyright (c) 1999, 2000 |
2 | * Copyright (c) 1999, 2000 |
3 | * Intel Corporation. |
3 | * Intel Corporation. |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * |
12 | * |
13 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the |
14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. |
15 | * documentation and/or other materials provided with the distribution. |
16 | * |
16 | * |
17 | * 3. All advertising materials mentioning features or use of this software |
17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: |
18 | * must display the following acknowledgement: |
19 | * |
19 | * |
20 | * This product includes software developed by Intel Corporation and |
20 | * This product includes software developed by Intel Corporation and |
21 | * its contributors. |
21 | * its contributors. |
22 | * |
22 | * |
23 | * 4. Neither the name of Intel Corporation or its contributors may be |
23 | * 4. Neither the name of Intel Corporation or its contributors may be |
24 | * used to endorse or promote products derived from this software |
24 | * used to endorse or promote products derived from this software |
25 | * without specific prior written permission. |
25 | * without specific prior written permission. |
26 | * |
26 | * |
27 | * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' |
27 | * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' |
28 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
28 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
29 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
29 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
30 | * ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE |
30 | * ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE |
31 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
31 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
32 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
32 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
33 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
33 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
34 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
34 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
35 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
35 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
36 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
36 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
37 | * THE POSSIBILITY OF SUCH DAMAGE. |
37 | * THE POSSIBILITY OF SUCH DAMAGE. |
38 | * |
38 | * |
39 | */ |
39 | */ |
40 | 40 | ||
41 | 41 | ||
42 | #ifndef _EFICONTEXT_H_ |
42 | #ifndef _EFICONTEXT_H_ |
43 | #define _EFICONTEXT_H_ |
43 | #define _EFICONTEXT_H_ |
44 | 44 | ||
45 | 45 | ||
46 | // |
46 | // |
47 | // IA-64 processor exception types |
47 | // IA-64 processor exception types |
48 | // |
48 | // |
49 | #define EXCPT_ALT_DTLB 4 |
49 | #define EXCPT_ALT_DTLB 4 |
50 | #define EXCPT_DNESTED_TLB 5 |
50 | #define EXCPT_DNESTED_TLB 5 |
51 | #define EXCPT_BREAKPOINT 11 |
51 | #define EXCPT_BREAKPOINT 11 |
52 | #define EXCPT_EXTERNAL_INTERRUPT 12 |
52 | #define EXCPT_EXTERNAL_INTERRUPT 12 |
53 | #define EXCPT_GEN_EXCEPT 24 |
53 | #define EXCPT_GEN_EXCEPT 24 |
54 | #define EXCPT_NAT_CONSUMPTION 26 |
54 | #define EXCPT_NAT_CONSUMPTION 26 |
55 | #define EXCPT_DEBUG_EXCEPT 29 |
55 | #define EXCPT_DEBUG_EXCEPT 29 |
56 | #define EXCPT_UNALIGNED_ACCESS 30 |
56 | #define EXCPT_UNALIGNED_ACCESS 30 |
57 | #define EXCPT_FP_FAULT 32 |
57 | #define EXCPT_FP_FAULT 32 |
58 | #define EXCPT_FP_TRAP 33 |
58 | #define EXCPT_FP_TRAP 33 |
59 | #define EXCPT_TAKEN_BRANCH 35 |
59 | #define EXCPT_TAKEN_BRANCH 35 |
60 | #define EXCPT_SINGLE_STEP 36 |
60 | #define EXCPT_SINGLE_STEP 36 |
61 | 61 | ||
62 | // |
62 | // |
63 | // IA-64 processor context definition - must be 512 byte aligned!!! |
63 | // IA-64 processor context definition - must be 512 byte aligned!!! |
64 | // |
64 | // |
65 | typedef |
65 | typedef |
66 | struct { |
66 | struct { |
67 | UINT64 reserved; // necessary to preserve alignment for the correct bits in UNAT and to insure F2 is 16 byte aligned... |
67 | UINT64 reserved; // necessary to preserve alignment for the correct bits in UNAT and to insure F2 is 16 byte aligned... |
68 | 68 | ||
69 | UINT64 r1; |
69 | UINT64 r1; |
70 | UINT64 r2; |
70 | UINT64 r2; |
71 | UINT64 r3; |
71 | UINT64 r3; |
72 | UINT64 r4; |
72 | UINT64 r4; |
73 | UINT64 r5; |
73 | UINT64 r5; |
74 | UINT64 r6; |
74 | UINT64 r6; |
75 | UINT64 r7; |
75 | UINT64 r7; |
76 | UINT64 r8; |
76 | UINT64 r8; |
77 | UINT64 r9; |
77 | UINT64 r9; |
78 | UINT64 r10; |
78 | UINT64 r10; |
79 | UINT64 r11; |
79 | UINT64 r11; |
80 | UINT64 r12; |
80 | UINT64 r12; |
81 | UINT64 r13; |
81 | UINT64 r13; |
82 | UINT64 r14; |
82 | UINT64 r14; |
83 | UINT64 r15; |
83 | UINT64 r15; |
84 | UINT64 r16; |
84 | UINT64 r16; |
85 | UINT64 r17; |
85 | UINT64 r17; |
86 | UINT64 r18; |
86 | UINT64 r18; |
87 | UINT64 r19; |
87 | UINT64 r19; |
88 | UINT64 r20; |
88 | UINT64 r20; |
89 | UINT64 r21; |
89 | UINT64 r21; |
90 | UINT64 r22; |
90 | UINT64 r22; |
91 | UINT64 r23; |
91 | UINT64 r23; |
92 | UINT64 r24; |
92 | UINT64 r24; |
93 | UINT64 r25; |
93 | UINT64 r25; |
94 | UINT64 r26; |
94 | UINT64 r26; |
95 | UINT64 r27; |
95 | UINT64 r27; |
96 | UINT64 r28; |
96 | UINT64 r28; |
97 | UINT64 r29; |
97 | UINT64 r29; |
98 | UINT64 r30; |
98 | UINT64 r30; |
99 | UINT64 r31; |
99 | UINT64 r31; |
100 | 100 | ||
101 | UINT64 f2[2]; |
101 | UINT64 f2[2]; |
102 | UINT64 f3[2]; |
102 | UINT64 f3[2]; |
103 | UINT64 f4[2]; |
103 | UINT64 f4[2]; |
104 | UINT64 f5[2]; |
104 | UINT64 f5[2]; |
105 | UINT64 f6[2]; |
105 | UINT64 f6[2]; |
106 | UINT64 f7[2]; |
106 | UINT64 f7[2]; |
107 | UINT64 f8[2]; |
107 | UINT64 f8[2]; |
108 | UINT64 f9[2]; |
108 | UINT64 f9[2]; |
109 | UINT64 f10[2]; |
109 | UINT64 f10[2]; |
110 | UINT64 f11[2]; |
110 | UINT64 f11[2]; |
111 | UINT64 f12[2]; |
111 | UINT64 f12[2]; |
112 | UINT64 f13[2]; |
112 | UINT64 f13[2]; |
113 | UINT64 f14[2]; |
113 | UINT64 f14[2]; |
114 | UINT64 f15[2]; |
114 | UINT64 f15[2]; |
115 | UINT64 f16[2]; |
115 | UINT64 f16[2]; |
116 | UINT64 f17[2]; |
116 | UINT64 f17[2]; |
117 | UINT64 f18[2]; |
117 | UINT64 f18[2]; |
118 | UINT64 f19[2]; |
118 | UINT64 f19[2]; |
119 | UINT64 f20[2]; |
119 | UINT64 f20[2]; |
120 | UINT64 f21[2]; |
120 | UINT64 f21[2]; |
121 | UINT64 f22[2]; |
121 | UINT64 f22[2]; |
122 | UINT64 f23[2]; |
122 | UINT64 f23[2]; |
123 | UINT64 f24[2]; |
123 | UINT64 f24[2]; |
124 | UINT64 f25[2]; |
124 | UINT64 f25[2]; |
125 | UINT64 f26[2]; |
125 | UINT64 f26[2]; |
126 | UINT64 f27[2]; |
126 | UINT64 f27[2]; |
127 | UINT64 f28[2]; |
127 | UINT64 f28[2]; |
128 | UINT64 f29[2]; |
128 | UINT64 f29[2]; |
129 | UINT64 f30[2]; |
129 | UINT64 f30[2]; |
130 | UINT64 f31[2]; |
130 | UINT64 f31[2]; |
131 | 131 | ||
132 | UINT64 pr; |
132 | UINT64 pr; |
133 | 133 | ||
134 | UINT64 b0; |
134 | UINT64 b0; |
135 | UINT64 b1; |
135 | UINT64 b1; |
136 | UINT64 b2; |
136 | UINT64 b2; |
137 | UINT64 b3; |
137 | UINT64 b3; |
138 | UINT64 b4; |
138 | UINT64 b4; |
139 | UINT64 b5; |
139 | UINT64 b5; |
140 | UINT64 b6; |
140 | UINT64 b6; |
141 | UINT64 b7; |
141 | UINT64 b7; |
142 | 142 | ||
143 | // application registers |
143 | // application registers |
144 | UINT64 ar_rsc; |
144 | UINT64 ar_rsc; |
145 | UINT64 ar_bsp; |
145 | UINT64 ar_bsp; |
146 | UINT64 ar_bspstore; |
146 | UINT64 ar_bspstore; |
147 | UINT64 ar_rnat; |
147 | UINT64 ar_rnat; |
148 | 148 | ||
149 | UINT64 ar_fcr; |
149 | UINT64 ar_fcr; |
150 | 150 | ||
151 | UINT64 ar_eflag; |
151 | UINT64 ar_eflag; |
152 | UINT64 ar_csd; |
152 | UINT64 ar_csd; |
153 | UINT64 ar_ssd; |
153 | UINT64 ar_ssd; |
154 | UINT64 ar_cflg; |
154 | UINT64 ar_cflg; |
155 | UINT64 ar_fsr; |
155 | UINT64 ar_fsr; |
156 | UINT64 ar_fir; |
156 | UINT64 ar_fir; |
157 | UINT64 ar_fdr; |
157 | UINT64 ar_fdr; |
158 | 158 | ||
159 | UINT64 ar_ccv; |
159 | UINT64 ar_ccv; |
160 | 160 | ||
161 | UINT64 ar_unat; |
161 | UINT64 ar_unat; |
162 | 162 | ||
163 | UINT64 ar_fpsr; |
163 | UINT64 ar_fpsr; |
164 | 164 | ||
165 | UINT64 ar_pfs; |
165 | UINT64 ar_pfs; |
166 | UINT64 ar_lc; |
166 | UINT64 ar_lc; |
167 | UINT64 ar_ec; |
167 | UINT64 ar_ec; |
168 | 168 | ||
169 | // control registers |
169 | // control registers |
170 | UINT64 cr_dcr; |
170 | UINT64 cr_dcr; |
171 | UINT64 cr_itm; |
171 | UINT64 cr_itm; |
172 | UINT64 cr_iva; |
172 | UINT64 cr_iva; |
173 | UINT64 cr_pta; |
173 | UINT64 cr_pta; |
174 | UINT64 cr_ipsr; |
174 | UINT64 cr_ipsr; |
175 | UINT64 cr_isr; |
175 | UINT64 cr_isr; |
176 | UINT64 cr_iip; |
176 | UINT64 cr_iip; |
177 | UINT64 cr_ifa; |
177 | UINT64 cr_ifa; |
178 | UINT64 cr_itir; |
178 | UINT64 cr_itir; |
179 | UINT64 cr_iipa; |
179 | UINT64 cr_iipa; |
180 | UINT64 cr_ifs; |
180 | UINT64 cr_ifs; |
181 | UINT64 cr_iim; |
181 | UINT64 cr_iim; |
182 | UINT64 cr_iha; |
182 | UINT64 cr_iha; |
183 | 183 | ||
184 | // debug registers |
184 | // debug registers |
185 | UINT64 dbr0; |
185 | UINT64 dbr0; |
186 | UINT64 dbr1; |
186 | UINT64 dbr1; |
187 | UINT64 dbr2; |
187 | UINT64 dbr2; |
188 | UINT64 dbr3; |
188 | UINT64 dbr3; |
189 | UINT64 dbr4; |
189 | UINT64 dbr4; |
190 | UINT64 dbr5; |
190 | UINT64 dbr5; |
191 | UINT64 dbr6; |
191 | UINT64 dbr6; |
192 | UINT64 dbr7; |
192 | UINT64 dbr7; |
193 | 193 | ||
194 | UINT64 ibr0; |
194 | UINT64 ibr0; |
195 | UINT64 ibr1; |
195 | UINT64 ibr1; |
196 | UINT64 ibr2; |
196 | UINT64 ibr2; |
197 | UINT64 ibr3; |
197 | UINT64 ibr3; |
198 | UINT64 ibr4; |
198 | UINT64 ibr4; |
199 | UINT64 ibr5; |
199 | UINT64 ibr5; |
200 | UINT64 ibr6; |
200 | UINT64 ibr6; |
201 | UINT64 ibr7; |
201 | UINT64 ibr7; |
202 | 202 | ||
203 | // virtual registers |
203 | // virtual registers |
204 | UINT64 int_nat; // nat bits for R1-R31 |
204 | UINT64 int_nat; // nat bits for R1-R31 |
205 | 205 | ||
206 | } SYSTEM_CONTEXT; |
206 | } SYSTEM_CONTEXT; |
207 | 207 | ||
208 | #endif /* _EFI_CONTEXT_H_ */ |
208 | #endif /* _EFI_CONTEXT_H_ */ |
209 | 209 |