WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/sparc64/src/mm/tsb.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tsb.h>
#include <arch/mm/tlb.h>
#include <arch/mm/page.h>
#include <arch/barrier.h>
#include <mm/as.h>
#include <arch/types.h>
#include <macros.h>
#include <debug.h>
 
#define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
 
/** Invalidate portion of TSB.
 *
 * We assume that the address space is already locked. Note that respective
 * portions of both TSBs are invalidated at a time.
 *
 * @param as Address space.
 * @param page First page to invalidate in TSB.
 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
 *  whole TSB.
 */
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
{
    index_t i0, i;
    count_t cnt;
   
    ASSERT(as->arch.itsb && as->arch.dtsb);
   
    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
 
    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
        cnt = ITSB_ENTRY_COUNT;
    else
        cnt = pages * 2;
   
    for (i = 0; i < cnt; i++) {
        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
            true;
        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
            true;
    }
}
 
/** Copy software PTE to ITSB.
 *
 * @param t     Software PTE.
 * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
 */
void itsb_pte_copy(pte_t *t, index_t index)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
 
    ASSERT(index <= 1);
   
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    ASSERT(entry < ITSB_ENTRY_COUNT);
    tsb = &as->arch.itsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = false;   /* mark the entry as valid */
}
 
/** Copy software PTE to DTSB.
 *
 * @param t Software PTE.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 * @param ro    If true, the mapping is copied read-only.
 */
void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
   
    ASSERT(index <= 1);
 
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    ASSERT(entry < DTSB_ENTRY_COUNT);
    tsb = &as->arch.dtsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    /* the shift is bigger than PAGE_WIDTH, do not bother with index */
    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    tsb->data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.w = ro ? false : t->w;
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = false;   /* mark the entry as valid */
}
 
/** @}
 */
 

Rev 2292	Rev 2307
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tsb.h>	35	#include <arch/mm/tsb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/mm/page.h>	37	#include <arch/mm/page.h>
38	#include <arch/barrier.h>	38	#include <arch/barrier.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch/types.h>	40	#include <arch/types.h>
41	#include <macros.h>	41	#include <macros.h>
42	#include <debug.h>	42	#include <debug.h>
43		43
44	#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)	44	#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
45		45
46	/** Invalidate portion of TSB.	46	/** Invalidate portion of TSB.
47	*	47	*
48	* We assume that the address space is already locked. Note that respective	48	* We assume that the address space is already locked. Note that respective
49	* portions of both TSBs are invalidated at a time.	49	* portions of both TSBs are invalidated at a time.
50	*	50	*
51	* @param as Address space.	51	* @param as Address space.
52	* @param page First page to invalidate in TSB.	52	* @param page First page to invalidate in TSB.
53	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the	53	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the
54	* whole TSB.	54	* whole TSB.
55	*/	55	*/
56	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)	56	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
57	{	57	{
58	index_t i0, i;	58	index_t i0, i;
59	count_t cnt;	59	count_t cnt;
60		60
61	ASSERT(as->arch.itsb && as->arch.dtsb);	61	ASSERT(as->arch.itsb && as->arch.dtsb);
62		62
63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;	63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
-		64	ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
-		65
64	if (pages == (count_t) -1 \|\| (pages * 2) > ITSB_ENTRY_COUNT)	66	if (pages == (count_t) -1 \|\| (pages * 2) > ITSB_ENTRY_COUNT)
65	cnt = ITSB_ENTRY_COUNT;	67	cnt = ITSB_ENTRY_COUNT;
66	else	68	else
67	cnt = pages * 2;	69	cnt = pages * 2;
68		70
69	for (i = 0; i < cnt; i++) {	71	for (i = 0; i < cnt; i++) {
70	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =	72	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
71	true;	73	true;
72	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =	74	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
73	true;	75	true;
74	}	76	}
75	}	77	}
76		78
77	/** Copy software PTE to ITSB.	79	/** Copy software PTE to ITSB.
78	*	80	*
79	* @param t Software PTE.	81	* @param t Software PTE.
80	* @param index Zero if lower 8K-subpage, one if higher 8K subpage.	82	* @param index Zero if lower 8K-subpage, one if higher 8K subpage.
81	*/	83	*/
82	void itsb_pte_copy(pte_t *t, index_t index)	84	void itsb_pte_copy(pte_t *t, index_t index)
83	{	85	{
84	as_t *as;	86	as_t *as;
85	tsb_entry_t *tsb;	87	tsb_entry_t *tsb;
86	index_t entry;	88	index_t entry;
-		89
-		90	ASSERT(index <= 1);
87		91
88	as = t->as;	92	as = t->as;
89	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;	93	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-		94	ASSERT(entry < ITSB_ENTRY_COUNT);
90	tsb = &as->arch.itsb[entry];	95	tsb = &as->arch.itsb[entry];
91		96
92	/*	97	/*
93	* We use write barriers to make sure that the TSB load	98	* We use write barriers to make sure that the TSB load
94	* won't use inconsistent data or that the fault will	99	* won't use inconsistent data or that the fault will
95	* be repeated.	100	* be repeated.
96	*/	101	*/
97		102
98	tsb->tag.invalid = true; /* invalidate the entry	103	tsb->tag.invalid = true; /* invalidate the entry
99	* (tag target has this	104	* (tag target has this
100	* set to 0) */	105	* set to 0) */
101		106
102	write_barrier();	107	write_barrier();
103		108
104	tsb->tag.context = as->asid;	109	tsb->tag.context = as->asid;
105	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>	110	/* the shift is bigger than PAGE_WIDTH, do not bother with index */
106	VA_TAG_PAGE_SHIFT;	111	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
107	tsb->data.value = 0;	112	tsb->data.value = 0;
108	tsb->data.size = PAGESIZE_8K;	113	tsb->data.size = PAGESIZE_8K;
109	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;	114	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
110	tsb->data.cp = t->c;	115	tsb->data.cp = t->c;
111	tsb->data.p = t->k; /* p as privileged */	116	tsb->data.p = t->k; /* p as privileged */
112	tsb->data.v = t->p;	117	tsb->data.v = t->p;
113		118
114	write_barrier();	119	write_barrier();
115		120
116	tsb->tag.invalid = false; /* mark the entry as valid */	121	tsb->tag.invalid = false; /* mark the entry as valid */
117	}	122	}
118		123
119	/** Copy software PTE to DTSB.	124	/** Copy software PTE to DTSB.
120	*	125	*
121	* @param t Software PTE.	126	* @param t Software PTE.
122	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.	127	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
123	* @param ro If true, the mapping is copied read-only.	128	* @param ro If true, the mapping is copied read-only.
124	*/	129	*/
125	void dtsb_pte_copy(pte_t *t, index_t index, bool ro)	130	void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
126	{	131	{
127	as_t *as;	132	as_t *as;
128	tsb_entry_t *tsb;	133	tsb_entry_t *tsb;
129	index_t entry;	134	index_t entry;
130		135
-		136	ASSERT(index <= 1);
-		137
131	as = t->as;	138	as = t->as;
132	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;	139	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-		140	ASSERT(entry < DTSB_ENTRY_COUNT);
133	tsb = &as->arch.dtsb[entry];	141	tsb = &as->arch.dtsb[entry];
134		142
135	/*	143	/*
136	* We use write barriers to make sure that the TSB load	144	* We use write barriers to make sure that the TSB load
137	* won't use inconsistent data or that the fault will	145	* won't use inconsistent data or that the fault will
138	* be repeated.	146	* be repeated.
139	*/	147	*/
140		148
141	tsb->tag.invalid = true; /* invalidate the entry	149	tsb->tag.invalid = true; /* invalidate the entry
142	* (tag target has this	150	* (tag target has this
143	* set to 0) */	151	* set to 0) */
144		152
145	write_barrier();	153	write_barrier();
146		154
147	tsb->tag.context = as->asid;	155	tsb->tag.context = as->asid;
148	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>	156	/* the shift is bigger than PAGE_WIDTH, do not bother with index */
149	VA_TAG_PAGE_SHIFT;	157	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
150	tsb->data.value = 0;	158	tsb->data.value = 0;
151	tsb->data.size = PAGESIZE_8K;	159	tsb->data.size = PAGESIZE_8K;
152	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;	160	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
153	tsb->data.cp = t->c;	161	tsb->data.cp = t->c;
154	#ifdef CONFIG_VIRT_IDX_DCACHE	162	#ifdef CONFIG_VIRT_IDX_DCACHE
155	tsb->data.cv = t->c;	163	tsb->data.cv = t->c;
156	#endif /* CONFIG_VIRT_IDX_DCACHE */	164	#endif /* CONFIG_VIRT_IDX_DCACHE */
157	tsb->data.p = t->k; /* p as privileged */	165	tsb->data.p = t->k; /* p as privileged */
158	tsb->data.w = ro ? false : t->w;	166	tsb->data.w = ro ? false : t->w;
159	tsb->data.v = t->p;	167	tsb->data.v = t->p;
160		168
161	write_barrier();	169	write_barrier();
162		170
163	tsb->tag.invalid = false; /* mark the entry as valid */	171	tsb->tag.invalid = false; /* mark the entry as valid */
164	}	172	}
165		173
166	/** @}	174	/** @}
167	*/	175	*/
168		176

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(root)/branches/rcu/kernel/arch/sparc64/src/mm/tsb.c @ 2466 – Rev 2292 → 2307