WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
static void dtlb_pte_copy(pte_t *t, bool ro);
static void itlb_pte_copy(pte_t *t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * TLBs are actually initialized early
     * in start.S.
     */
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
    data.cv = cacheable;
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t Page Table Entry to be copied.
 * @param ro If true, the entry will be created read-only, regardless of its w field.
 */
void dtlb_pte_copy(pte_t *t, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    dtlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.cv = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
   
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to ITLB.
 *
 * @param t Page Table Entry to be copied.
 */
void itlb_pte_copy(pte_t *t)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.cv = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t);
#ifdef CONFIG_TSB
        itsb_pte_copy(t);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved
 * by the low-level, assembly language part of the fast_data_access_mmu_miss
 * handler.
 */
void fast_data_access_mmu_miss(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is writable.
         * Demap the old mapping and insert an updated mapping into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
        dtlb_pte_copy(t, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 1880	Rev 1891
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <typedefs.h>	47	#include <typedefs.h>
48	#include <config.h>	48	#include <config.h>
49	#include <arch/trap/trap.h>	49	#include <arch/trap/trap.h>
50	#include <arch/trap/exception.h>	50	#include <arch/trap/exception.h>
51	#include <panic.h>	51	#include <panic.h>
52	#include <arch/asm.h>	52	#include <arch/asm.h>
53		53
-		54	#ifdef CONFIG_TSB
-		55	#include <arch/mm/tsb.h>
-		56	#endif
-		57
54	static void dtlb_pte_copy(pte_t *t, bool ro);	58	static void dtlb_pte_copy(pte_t *t, bool ro);
55	static void itlb_pte_copy(pte_t *t);	59	static void itlb_pte_copy(pte_t *t);
56	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);	60	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);
57	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	61	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
58	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	62	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
59		63
60	char *context_encoding[] = {	64	char *context_encoding[] = {
61	"Primary",	65	"Primary",
62	"Secondary",	66	"Secondary",
63	"Nucleus",	67	"Nucleus",
64	"Reserved"	68	"Reserved"
65	};	69	};
66		70
67	void tlb_arch_init(void)	71	void tlb_arch_init(void)
68	{	72	{
69	/*	73	/*
70	* TLBs are actually initialized early	74	* TLBs are actually initialized early
71	* in start.S.	75	* in start.S.
72	*/	76	*/
73	}	77	}
74		78
75	/** Insert privileged mapping into DMMU TLB.	79	/** Insert privileged mapping into DMMU TLB.
76	*	80	*
77	* @param page Virtual page address.	81	* @param page Virtual page address.
78	* @param frame Physical frame address.	82	* @param frame Physical frame address.
79	* @param pagesize Page size.	83	* @param pagesize Page size.
80	* @param locked True for permanent mappings, false otherwise.	84	* @param locked True for permanent mappings, false otherwise.
81	* @param cacheable True if the mapping is cacheable, false otherwise.	85	* @param cacheable True if the mapping is cacheable, false otherwise.
82	*/	86	*/
83	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)	87	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
84	{	88	{
85	tlb_tag_access_reg_t tag;	89	tlb_tag_access_reg_t tag;
86	tlb_data_t data;	90	tlb_data_t data;
87	page_address_t pg;	91	page_address_t pg;
88	frame_address_t fr;	92	frame_address_t fr;
89		93
90	pg.address = page;	94	pg.address = page;
91	fr.address = frame;	95	fr.address = frame;
92		96
93	tag.value = ASID_KERNEL;	97	tag.value = ASID_KERNEL;
94	tag.vpn = pg.vpn;	98	tag.vpn = pg.vpn;
95		99
96	dtlb_tag_access_write(tag.value);	100	dtlb_tag_access_write(tag.value);
97		101
98	data.value = 0;	102	data.value = 0;
99	data.v = true;	103	data.v = true;
100	data.size = pagesize;	104	data.size = pagesize;
101	data.pfn = fr.pfn;	105	data.pfn = fr.pfn;
102	data.l = locked;	106	data.l = locked;
103	data.cp = cacheable;	107	data.cp = cacheable;
104	data.cv = cacheable;	108	data.cv = cacheable;
105	data.p = true;	109	data.p = true;
106	data.w = true;	110	data.w = true;
107	data.g = false;	111	data.g = false;
108		112
109	dtlb_data_in_write(data.value);	113	dtlb_data_in_write(data.value);
110	}	114	}
111		115
112	/** Copy PTE to TLB.	116	/** Copy PTE to TLB.
113	*	117	*
114	* @param t Page Table Entry to be copied.	118	* @param t Page Table Entry to be copied.
115	* @param ro If true, the entry will be created read-only, regardless of its w field.	119	* @param ro If true, the entry will be created read-only, regardless of its w field.
116	*/	120	*/
117	void dtlb_pte_copy(pte_t *t, bool ro)	121	void dtlb_pte_copy(pte_t *t, bool ro)
118	{	122	{
119	tlb_tag_access_reg_t tag;	123	tlb_tag_access_reg_t tag;
120	tlb_data_t data;	124	tlb_data_t data;
121	page_address_t pg;	125	page_address_t pg;
122	frame_address_t fr;	126	frame_address_t fr;
123		127
124	pg.address = t->page;	128	pg.address = t->page;
125	fr.address = t->frame;	129	fr.address = t->frame;
126		130
127	tag.value = 0;	131	tag.value = 0;
128	tag.context = t->as->asid;	132	tag.context = t->as->asid;
129	tag.vpn = pg.vpn;	133	tag.vpn = pg.vpn;
130		134
131	dtlb_tag_access_write(tag.value);	135	dtlb_tag_access_write(tag.value);
132		136
133	data.value = 0;	137	data.value = 0;
134	data.v = true;	138	data.v = true;
135	data.size = PAGESIZE_8K;	139	data.size = PAGESIZE_8K;
136	data.pfn = fr.pfn;	140	data.pfn = fr.pfn;
137	data.l = false;	141	data.l = false;
138	data.cp = t->c;	142	data.cp = t->c;
139	data.cv = t->c;	143	data.cv = t->c;
140	data.p = t->k; /* p like privileged */	144	data.p = t->k; /* p like privileged */
141	data.w = ro ? false : t->w;	145	data.w = ro ? false : t->w;
142	data.g = t->g;	146	data.g = t->g;
143		147
144	dtlb_data_in_write(data.value);	148	dtlb_data_in_write(data.value);
145	}	149	}
146		150
-		151	/** Copy PTE to ITLB.
-		152	*
-		153	* @param t Page Table Entry to be copied.
-		154	*/
147	void itlb_pte_copy(pte_t *t)	155	void itlb_pte_copy(pte_t *t)
148	{	156	{
149	tlb_tag_access_reg_t tag;	157	tlb_tag_access_reg_t tag;
150	tlb_data_t data;	158	tlb_data_t data;
151	page_address_t pg;	159	page_address_t pg;
152	frame_address_t fr;	160	frame_address_t fr;
153		161
154	pg.address = t->page;	162	pg.address = t->page;
155	fr.address = t->frame;	163	fr.address = t->frame;
156		164
157	tag.value = 0;	165	tag.value = 0;
158	tag.context = t->as->asid;	166	tag.context = t->as->asid;
159	tag.vpn = pg.vpn;	167	tag.vpn = pg.vpn;
160		168
161	itlb_tag_access_write(tag.value);	169	itlb_tag_access_write(tag.value);
162		170
163	data.value = 0;	171	data.value = 0;
164	data.v = true;	172	data.v = true;
165	data.size = PAGESIZE_8K;	173	data.size = PAGESIZE_8K;
166	data.pfn = fr.pfn;	174	data.pfn = fr.pfn;
167	data.l = false;	175	data.l = false;
168	data.cp = t->c;	176	data.cp = t->c;
169	data.cv = t->c;	177	data.cv = t->c;
170	data.p = t->k; /* p like privileged */	178	data.p = t->k; /* p like privileged */
171	data.w = false;	179	data.w = false;
172	data.g = t->g;	180	data.g = t->g;
173		181
174	itlb_data_in_write(data.value);	182	itlb_data_in_write(data.value);
175	}	183	}
176		184
177	/** ITLB miss handler. */	185	/** ITLB miss handler. */
178	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	186	void fast_instruction_access_mmu_miss(int n, istate_t *istate)
179	{	187	{
180	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	188	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
181	pte_t *t;	189	pte_t *t;
182		190
183	page_table_lock(AS, true);	191	page_table_lock(AS, true);
184	t = page_mapping_find(AS, va);	192	t = page_mapping_find(AS, va);
185	if (t && PTE_EXECUTABLE(t)) {	193	if (t && PTE_EXECUTABLE(t)) {
186	/*	194	/*
187	* The mapping was found in the software page hash table.	195	* The mapping was found in the software page hash table.
188	* Insert it into ITLB.	196	* Insert it into ITLB.
189	*/	197	*/
190	t->a = true;	198	t->a = true;
191	itlb_pte_copy(t);	199	itlb_pte_copy(t);
-		200	#ifdef CONFIG_TSB
-		201	itsb_pte_copy(t);
-		202	#endif
192	page_table_unlock(AS, true);	203	page_table_unlock(AS, true);
193	} else {	204	} else {
194	/*	205	/*
195	* Forward the page fault to the address space page fault handler.	206	* Forward the page fault to the address space page fault handler.
196	*/	207	*/
197	page_table_unlock(AS, true);	208	page_table_unlock(AS, true);
198	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	209	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
199	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);	210	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
200	}	211	}
201	}	212	}
202	}	213	}
203		214
204	/** DTLB miss handler.	215	/** DTLB miss handler.
205	*	216	*
206	* Note that some faults (e.g. kernel faults) were already resolved	217	* Note that some faults (e.g. kernel faults) were already resolved
207	* by the low-level, assembly language part of the fast_data_access_mmu_miss	218	* by the low-level, assembly language part of the fast_data_access_mmu_miss
208	* handler.	219	* handler.
209	*/	220	*/
210	void fast_data_access_mmu_miss(int n, istate_t *istate)	221	void fast_data_access_mmu_miss(int n, istate_t *istate)
211	{	222	{
212	tlb_tag_access_reg_t tag;	223	tlb_tag_access_reg_t tag;
213	uintptr_t va;	224	uintptr_t va;
214	pte_t *t;	225	pte_t *t;
215		226
216	tag.value = dtlb_tag_access_read();	227	tag.value = dtlb_tag_access_read();
217	va = tag.vpn << PAGE_WIDTH;	228	va = tag.vpn << PAGE_WIDTH;
218		229
219	if (tag.context == ASID_KERNEL) {	230	if (tag.context == ASID_KERNEL) {
220	if (!tag.vpn) {	231	if (!tag.vpn) {
221	/* NULL access in kernel */	232	/* NULL access in kernel */
222	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	233	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
223	}	234	}
224	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");	235	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
225	}	236	}
226		237
227	page_table_lock(AS, true);	238	page_table_lock(AS, true);
228	t = page_mapping_find(AS, va);	239	t = page_mapping_find(AS, va);
229	if (t) {	240	if (t) {
230	/*	241	/*
231	* The mapping was found in the software page hash table.	242	* The mapping was found in the software page hash table.
232	* Insert it into DTLB.	243	* Insert it into DTLB.
233	*/	244	*/
234	t->a = true;	245	t->a = true;
235	dtlb_pte_copy(t, true);	246	dtlb_pte_copy(t, true);
-		247	#ifdef CONFIG_TSB
-		248	dtsb_pte_copy(t, true);
-		249	#endif
236	page_table_unlock(AS, true);	250	page_table_unlock(AS, true);
237	} else {	251	} else {
238	/*	252	/*
239	* Forward the page fault to the address space page fault handler.	253	* Forward the page fault to the address space page fault handler.
240	*/	254	*/
241	page_table_unlock(AS, true);	255	page_table_unlock(AS, true);
242	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	256	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
243	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	257	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
244	}	258	}
245	}	259	}
246	}	260	}
247		261
248	/** DTLB protection fault handler. */	262	/** DTLB protection fault handler. */
249	void fast_data_access_protection(int n, istate_t *istate)	263	void fast_data_access_protection(int n, istate_t *istate)
250	{	264	{
251	tlb_tag_access_reg_t tag;	265	tlb_tag_access_reg_t tag;
252	uintptr_t va;	266	uintptr_t va;
253	pte_t *t;	267	pte_t *t;
254		268
255	tag.value = dtlb_tag_access_read();	269	tag.value = dtlb_tag_access_read();
256	va = tag.vpn << PAGE_WIDTH;	270	va = tag.vpn << PAGE_WIDTH;
257		271
258	page_table_lock(AS, true);	272	page_table_lock(AS, true);
259	t = page_mapping_find(AS, va);	273	t = page_mapping_find(AS, va);
260	if (t && PTE_WRITABLE(t)) {	274	if (t && PTE_WRITABLE(t)) {
261	/*	275	/*
262	* The mapping was found in the software page hash table and is writable.	276	* The mapping was found in the software page hash table and is writable.
263	* Demap the old mapping and insert an updated mapping into DTLB.	277	* Demap the old mapping and insert an updated mapping into DTLB.
264	*/	278	*/
265	t->a = true;	279	t->a = true;
266	t->d = true;	280	t->d = true;
267	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);	281	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
268	dtlb_pte_copy(t, false);	282	dtlb_pte_copy(t, false);
-		283	#ifdef CONFIG_TSB
-		284	dtsb_pte_copy(t, false);
-		285	#endif
269	page_table_unlock(AS, true);	286	page_table_unlock(AS, true);
270	} else {	287	} else {
271	/*	288	/*
272	* Forward the page fault to the address space page fault handler.	289	* Forward the page fault to the address space page fault handler.
273	*/	290	*/
274	page_table_unlock(AS, true);	291	page_table_unlock(AS, true);
275	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	292	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
276	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);	293	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
277	}	294	}
278	}	295	}
279	}	296	}
280		297
281	/** Print contents of both TLBs. */	298	/** Print contents of both TLBs. */
282	void tlb_print(void)	299	void tlb_print(void)
283	{	300	{
284	int i;	301	int i;
285	tlb_data_t d;	302	tlb_data_t d;
286	tlb_tag_read_reg_t t;	303	tlb_tag_read_reg_t t;
287		304
288	printf("I-TLB contents:\n");	305	printf("I-TLB contents:\n");
289	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	306	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
290	d.value = itlb_data_access_read(i);	307	d.value = itlb_data_access_read(i);
291	t.value = itlb_tag_read_read(i);	308	t.value = itlb_tag_read_read(i);
292		309
293	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	310	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
294	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	311	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
295	}	312	}
296		313
297	printf("D-TLB contents:\n");	314	printf("D-TLB contents:\n");
298	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	315	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
299	d.value = dtlb_data_access_read(i);	316	d.value = dtlb_data_access_read(i);
300	t.value = dtlb_tag_read_read(i);	317	t.value = dtlb_tag_read_read(i);
301		318
302	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	319	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
303	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	320	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
304	}	321	}
305		322
306	}	323	}
307		324
308	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)	325	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)
309	{	326	{
310	fault_if_from_uspace(istate, "%s\n", str);	327	fault_if_from_uspace(istate, "%s\n", str);
311	dump_istate(istate);	328	dump_istate(istate);
312	panic("%s\n", str);	329	panic("%s\n", str);
313	}	330	}
314		331
315	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	332	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
316	{	333	{
317	uintptr_t va;	334	uintptr_t va;
318		335
319	va = tag.vpn << PAGE_WIDTH;	336	va = tag.vpn << PAGE_WIDTH;
320		337
321	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	338	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
322	dump_istate(istate);	339	dump_istate(istate);
323	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	340	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
324	panic("%s\n", str);	341	panic("%s\n", str);
325	}	342	}
326		343
327	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	344	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
328	{	345	{
329	uintptr_t va;	346	uintptr_t va;
330		347
331	va = tag.vpn << PAGE_WIDTH;	348	va = tag.vpn << PAGE_WIDTH;
332		349
333	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	350	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
334	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	351	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
335	dump_istate(istate);	352	dump_istate(istate);
336	panic("%s\n", str);	353	panic("%s\n", str);
337	}	354	}
338		355
339	/** Invalidate all unlocked ITLB and DTLB entries. */	356	/** Invalidate all unlocked ITLB and DTLB entries. */
340	void tlb_invalidate_all(void)	357	void tlb_invalidate_all(void)
341	{	358	{
342	int i;	359	int i;
343	tlb_data_t d;	360	tlb_data_t d;
344	tlb_tag_read_reg_t t;	361	tlb_tag_read_reg_t t;
345		362
346	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	363	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
347	d.value = itlb_data_access_read(i);	364	d.value = itlb_data_access_read(i);
348	if (!d.l) {	365	if (!d.l) {
349	t.value = itlb_tag_read_read(i);	366	t.value = itlb_tag_read_read(i);
350	d.v = false;	367	d.v = false;
351	itlb_tag_access_write(t.value);	368	itlb_tag_access_write(t.value);
352	itlb_data_access_write(i, d.value);	369	itlb_data_access_write(i, d.value);
353	}	370	}
354	}	371	}
355		372
356	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	373	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
357	d.value = dtlb_data_access_read(i);	374	d.value = dtlb_data_access_read(i);
358	if (!d.l) {	375	if (!d.l) {
359	t.value = dtlb_tag_read_read(i);	376	t.value = dtlb_tag_read_read(i);
360	d.v = false;	377	d.v = false;
361	dtlb_tag_access_write(t.value);	378	dtlb_tag_access_write(t.value);
362	dtlb_data_access_write(i, d.value);	379	dtlb_data_access_write(i, d.value);
363	}	380	}
364	}	381	}
365		382
366	}	383	}
367		384
368	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	385	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
369	*	386	*
370	* @param asid Address Space ID.	387	* @param asid Address Space ID.
371	*/	388	*/
372	void tlb_invalidate_asid(asid_t asid)	389	void tlb_invalidate_asid(asid_t asid)
373	{	390	{
374	tlb_context_reg_t pc_save, ctx;	391	tlb_context_reg_t pc_save, ctx;
375		392
376	/* switch to nucleus because we are mapped by the primary context */	393	/* switch to nucleus because we are mapped by the primary context */
377	nucleus_enter();	394	nucleus_enter();
378		395
379	ctx.v = pc_save.v = mmu_primary_context_read();	396	ctx.v = pc_save.v = mmu_primary_context_read();
380	ctx.context = asid;	397	ctx.context = asid;
381	mmu_primary_context_write(ctx.v);	398	mmu_primary_context_write(ctx.v);
382		399
383	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	400	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
384	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	401	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
385		402
386	mmu_primary_context_write(pc_save.v);	403	mmu_primary_context_write(pc_save.v);
387		404
388	nucleus_leave();	405	nucleus_leave();
389	}	406	}
390		407
391	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	408	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
392	*	409	*
393	* @param asid Address Space ID.	410	* @param asid Address Space ID.
394	* @param page First page which to sweep out from ITLB and DTLB.	411	* @param page First page which to sweep out from ITLB and DTLB.
395	* @param cnt Number of ITLB and DTLB entries to invalidate.	412	* @param cnt Number of ITLB and DTLB entries to invalidate.
396	*/	413	*/
397	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	414	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
398	{	415	{
399	int i;	416	int i;
400	tlb_context_reg_t pc_save, ctx;	417	tlb_context_reg_t pc_save, ctx;
401		418
402	/* switch to nucleus because we are mapped by the primary context */	419	/* switch to nucleus because we are mapped by the primary context */
403	nucleus_enter();	420	nucleus_enter();
404		421
405	ctx.v = pc_save.v = mmu_primary_context_read();	422	ctx.v = pc_save.v = mmu_primary_context_read();
406	ctx.context = asid;	423	ctx.context = asid;
407	mmu_primary_context_write(ctx.v);	424	mmu_primary_context_write(ctx.v);
408		425
409	for (i = 0; i < cnt; i++) {	426	for (i = 0; i < cnt; i++) {
410	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	427	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
411	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	428	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
412	}	429	}
413		430
414	mmu_primary_context_write(pc_save.v);	431	mmu_primary_context_write(pc_save.v);
415		432
416	nucleus_leave();	433	nucleus_leave();
417	}	434	}
418		435
419	/** @}	436	/** @}
420	*/	437	*/
421		438

Subversion Repositories HelenOS

(root)/branches/rcu/kernel/arch/sparc64/src/mm/tlb.c @ 4757 – Rev 1880 → 1891