WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <mm/asid.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
 
 
 
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * TLBs are actually initialized early
 
     * in start.S.
     */
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
    data.cv = cacheable;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
    tlb_tag_access_reg_t tag;
    uintptr_t tpc;
    char *tpc_str;
 
    tag.value = dtlb_tag_access_read();
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
        tpc = tpc_read();
        tpc_str = get_symtab_entry(tpc);
 
        printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
        printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
        panic("%s\n", __FUNCTION__);
    }
 
    /*
     * Identity map piece of faulting kernel address space.
     */
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
   
    for (i = 0; i < cnt; i++) {
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    }
}
 
/** @}
 */
 

Rev 1793	Rev 1842
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <arch/mm/frame.h>	37	#include <arch/mm/frame.h>
38	#include <arch/mm/page.h>	38	#include <arch/mm/page.h>
39	#include <arch/mm/mmu.h>	39	#include <arch/mm/mmu.h>
40	#include <mm/asid.h>	40	#include <mm/asid.h>
41	#include <print.h>	41	#include <print.h>
42	#include <arch/types.h>	42	#include <arch/types.h>
43	#include <typedefs.h>	43	#include <typedefs.h>
44	#include <config.h>	44	#include <config.h>
45	#include <arch/trap/trap.h>	45	#include <arch/trap/trap.h>
46	#include <panic.h>	46	#include <panic.h>
47	#include <arch/asm.h>	47	#include <arch/asm.h>
48	#include <symtab.h>	48	#include <symtab.h>
49		49
50	#include <arch/drivers/fb.h>	-
51	#include <arch/drivers/i8042.h>	-
52		-
53	char *context_encoding[] = {	50	char *context_encoding[] = {
54	"Primary",	51	"Primary",
55	"Secondary",	52	"Secondary",
56	"Nucleus",	53	"Nucleus",
57	"Reserved"	54	"Reserved"
58	};	55	};
59		56
60	void tlb_arch_init(void)	57	void tlb_arch_init(void)
61	{	58	{
62	/*	59	/*
63	* TLBs are actually initialized by	60	* TLBs are actually initialized early
64	* take_over_tlb_and_tt() early	-
65	* in start.S.	61	* in start.S.
66	*/	62	*/
67	}	63	}
68		64
69	/** Insert privileged mapping into DMMU TLB.	65	/** Insert privileged mapping into DMMU TLB.
70	*	66	*
71	* @param page Virtual page address.	67	* @param page Virtual page address.
72	* @param frame Physical frame address.	68	* @param frame Physical frame address.
73	* @param pagesize Page size.	69	* @param pagesize Page size.
74	* @param locked True for permanent mappings, false otherwise.	70	* @param locked True for permanent mappings, false otherwise.
75	* @param cacheable True if the mapping is cacheable, false otherwise.	71	* @param cacheable True if the mapping is cacheable, false otherwise.
76	*/	72	*/
77	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)	73	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
78	{	74	{
79	tlb_tag_access_reg_t tag;	75	tlb_tag_access_reg_t tag;
80	tlb_data_t data;	76	tlb_data_t data;
81	page_address_t pg;	77	page_address_t pg;
82	frame_address_t fr;	78	frame_address_t fr;
83		79
84	pg.address = page;	80	pg.address = page;
85	fr.address = frame;	81	fr.address = frame;
86		82
87	tag.value = ASID_KERNEL;	83	tag.value = ASID_KERNEL;
88	tag.vpn = pg.vpn;	84	tag.vpn = pg.vpn;
89		85
90	dtlb_tag_access_write(tag.value);	86	dtlb_tag_access_write(tag.value);
91		87
92	data.value = 0;	88	data.value = 0;
93	data.v = true;	89	data.v = true;
94	data.size = pagesize;	90	data.size = pagesize;
95	data.pfn = fr.pfn;	91	data.pfn = fr.pfn;
96	data.l = locked;	92	data.l = locked;
97	data.cp = cacheable;	93	data.cp = cacheable;
98	data.cv = cacheable;	94	data.cv = cacheable;
99	data.p = true;	95	data.p = true;
100	data.w = true;	96	data.w = true;
101	data.g = true;	97	data.g = true;
102		98
103	dtlb_data_in_write(data.value);	99	dtlb_data_in_write(data.value);
104	}	100	}
105		101
106	/** ITLB miss handler. */	102	/** ITLB miss handler. */
107	void fast_instruction_access_mmu_miss(void)	103	void fast_instruction_access_mmu_miss(void)
108	{	104	{
109	panic("%s\n", __FUNCTION__);	105	panic("%s\n", __FUNCTION__);
110	}	106	}
111		107
112	/** DTLB miss handler. */	108	/** DTLB miss handler. */
113	void fast_data_access_mmu_miss(void)	109	void fast_data_access_mmu_miss(void)
114	{	110	{
115	tlb_tag_access_reg_t tag;	111	tlb_tag_access_reg_t tag;
116	uintptr_t tpc;	112	uintptr_t tpc;
117	char *tpc_str;	113	char *tpc_str;
118		114
119	tag.value = dtlb_tag_access_read();	115	tag.value = dtlb_tag_access_read();
120	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {	116	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {
121	tpc = tpc_read();	117	tpc = tpc_read();
122	tpc_str = get_symtab_entry(tpc);	118	tpc_str = get_symtab_entry(tpc);
123		119
124	printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);	120	printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
125	printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");	121	printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
126	panic("%s\n", __FUNCTION__);	122	panic("%s\n", __FUNCTION__);
127	}	123	}
128		124
129	/*	125	/*
130	* Identity map piece of faulting kernel address space.	126	* Identity map piece of faulting kernel address space.
131	*/	127	*/
132	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);	128	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
133	}	129	}
134		130
135	/** DTLB protection fault handler. */	131	/** DTLB protection fault handler. */
136	void fast_data_access_protection(void)	132	void fast_data_access_protection(void)
137	{	133	{
138	panic("%s\n", __FUNCTION__);	134	panic("%s\n", __FUNCTION__);
139	}	135	}
140		136
141	/** Print contents of both TLBs. */	137	/** Print contents of both TLBs. */
142	void tlb_print(void)	138	void tlb_print(void)
143	{	139	{
144	int i;	140	int i;
145	tlb_data_t d;	141	tlb_data_t d;
146	tlb_tag_read_reg_t t;	142	tlb_tag_read_reg_t t;
147		143
148	printf("I-TLB contents:\n");	144	printf("I-TLB contents:\n");
149	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	145	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
150	d.value = itlb_data_access_read(i);	146	d.value = itlb_data_access_read(i);
151	t.value = itlb_tag_read_read(i);	147	t.value = itlb_tag_read_read(i);
152		148
153	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	149	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
154	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	150	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
155	}	151	}
156		152
157	printf("D-TLB contents:\n");	153	printf("D-TLB contents:\n");
158	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	154	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
159	d.value = dtlb_data_access_read(i);	155	d.value = dtlb_data_access_read(i);
160	t.value = dtlb_tag_read_read(i);	156	t.value = dtlb_tag_read_read(i);
161		157
162	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	158	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
163	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	159	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
164	}	160	}
165		161
166	}	162	}
167		163
168	/** Invalidate all unlocked ITLB and DTLB entries. */	164	/** Invalidate all unlocked ITLB and DTLB entries. */
169	void tlb_invalidate_all(void)	165	void tlb_invalidate_all(void)
170	{	166	{
171	int i;	167	int i;
172	tlb_data_t d;	168	tlb_data_t d;
173	tlb_tag_read_reg_t t;	169	tlb_tag_read_reg_t t;
174		170
175	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	171	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
176	d.value = itlb_data_access_read(i);	172	d.value = itlb_data_access_read(i);
177	if (!d.l) {	173	if (!d.l) {
178	t.value = itlb_tag_read_read(i);	174	t.value = itlb_tag_read_read(i);
179	d.v = false;	175	d.v = false;
180	itlb_tag_access_write(t.value);	176	itlb_tag_access_write(t.value);
181	itlb_data_access_write(i, d.value);	177	itlb_data_access_write(i, d.value);
182	}	178	}
183	}	179	}
184		180
185	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	181	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
186	d.value = dtlb_data_access_read(i);	182	d.value = dtlb_data_access_read(i);
187	if (!d.l) {	183	if (!d.l) {
188	t.value = dtlb_tag_read_read(i);	184	t.value = dtlb_tag_read_read(i);
189	d.v = false;	185	d.v = false;
190	dtlb_tag_access_write(t.value);	186	dtlb_tag_access_write(t.value);
191	dtlb_data_access_write(i, d.value);	187	dtlb_data_access_write(i, d.value);
192	}	188	}
193	}	189	}
194		190
195	}	191	}
196		192
197	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	193	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
198	*	194	*
199	* @param asid Address Space ID.	195	* @param asid Address Space ID.
200	*/	196	*/
201	void tlb_invalidate_asid(asid_t asid)	197	void tlb_invalidate_asid(asid_t asid)
202	{	198	{
203	/* TODO: write asid to some Context register and encode the register in second parameter below. */	199	/* TODO: write asid to some Context register and encode the register in second parameter below. */
204	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	200	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
205	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	201	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
206	}	202	}
207		203
208	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	204	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
209	*	205	*
210	* @param asid Address Space ID.	206	* @param asid Address Space ID.
211	* @param page First page which to sweep out from ITLB and DTLB.	207	* @param page First page which to sweep out from ITLB and DTLB.
212	* @param cnt Number of ITLB and DTLB entries to invalidate.	208	* @param cnt Number of ITLB and DTLB entries to invalidate.
213	*/	209	*/
214	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	210	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
215	{	211	{
216	int i;	212	int i;
217		213
218	for (i = 0; i < cnt; i++) {	214	for (i = 0; i < cnt; i++) {
219	/* TODO: write asid to some Context register and encode the register in second parameter below. */	215	/* TODO: write asid to some Context register and encode the register in second parameter below. */
220	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	216	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
221	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	217	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
222	}	218	}
223	}	219	}
224		220
225	/** @}	221	/** @}
226	*/	222	*/
227		223

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(root)/branches/rcu/kernel/arch/sparc64/src/mm/tlb.c @ 2308 – Rev 1793 → 1842