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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <smp/ipi.h> |
35 | #include <smp/ipi.h> |
36 | #include <cpu.h> |
36 | #include <cpu.h> |
37 | #include <arch.h> |
37 | #include <arch.h> |
38 | #include <arch/cpu.h> |
38 | #include <arch/cpu.h> |
39 | #include <arch/asm.h> |
39 | #include <arch/asm.h> |
40 | #include <config.h> |
40 | #include <config.h> |
41 | #include <mm/tlb.h> |
41 | #include <mm/tlb.h> |
42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
43 | #include <arch/trap/interrupt.h> |
43 | #include <arch/trap/interrupt.h> |
44 | #include <arch/barrier.h> |
44 | #include <arch/barrier.h> |
45 | #include <preemption.h> |
45 | #include <preemption.h> |
46 | #include <time/delay.h> |
46 | #include <time/delay.h> |
47 | #include <panic.h> |
47 | #include <panic.h> |
48 | 48 | ||
- | 49 | /** Set the contents of the outgoing interrupt vector data. |
|
- | 50 | * |
|
- | 51 | * The first data item (data 0) will be set to the value of func, the |
|
- | 52 | * rest of the vector will contain zeros. |
|
- | 53 | * |
|
- | 54 | * This is a helper function used from within the cross_call function. |
|
- | 55 | * |
|
- | 56 | * @param func value the first data item of the vector will be set to |
|
- | 57 | */ |
|
- | 58 | static inline void set_intr_w_data(void (* func)(void)) |
|
- | 59 | { |
|
- | 60 | #if defined (US) |
|
- | 61 | asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func); |
|
- | 62 | asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
|
- | 63 | asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
|
- | 64 | #elif defined (US3) |
|
- | 65 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func); |
|
- | 66 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0); |
|
- | 67 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0); |
|
- | 68 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0); |
|
- | 69 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0); |
|
- | 70 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0); |
|
- | 71 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0); |
|
- | 72 | asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0); |
|
- | 73 | #endif |
|
- | 74 | } |
|
- | 75 | ||
49 | /** Invoke function on another processor. |
76 | /** Invoke function on another processor. |
50 | * |
77 | * |
51 | * Currently, only functions without arguments are supported. |
78 | * Currently, only functions without arguments are supported. |
52 | * Supporting more arguments in the future should be no big deal. |
79 | * Supporting more arguments in the future should be no big deal. |
53 | * |
80 | * |
54 | * Interrupts must be disabled prior to this call. |
81 | * Interrupts must be disabled prior to this call. |
55 | * |
82 | * |
56 | * @param mid MID of the target processor. |
83 | * @param mid MID of the target processor. |
57 | * @param func Function to be invoked. |
84 | * @param func Function to be invoked. |
58 | */ |
85 | */ |
59 | static void cross_call(int mid, void (* func)(void)) |
86 | static void cross_call(int mid, void (* func)(void)) |
60 | { |
87 | { |
61 | uint64_t status; |
88 | uint64_t status; |
62 | bool done; |
89 | bool done; |
63 | 90 | ||
64 | /* |
91 | /* |
65 | * This function might enable interrupts for a while. |
92 | * This function might enable interrupts for a while. |
66 | * In order to prevent migration to another processor, |
93 | * In order to prevent migration to another processor, |
67 | * we explicitly disable preemption. |
94 | * we explicitly disable preemption. |
68 | */ |
95 | */ |
69 | 96 | ||
70 | preemption_disable(); |
97 | preemption_disable(); |
71 | 98 | ||
72 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
99 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
73 | if (status & INTR_DISPATCH_STATUS_BUSY) |
100 | if (status & INTR_DISPATCH_STATUS_BUSY) |
74 | panic("Interrupt Dispatch Status busy bit set\n"); |
101 | panic("Interrupt Dispatch Status busy bit set."); |
- | 102 | ||
- | 103 | ASSERT(!(pstate_read() & PSTATE_IE_BIT)); |
|
75 | 104 | ||
76 | do { |
105 | do { |
77 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, |
- | |
78 | (uintptr_t) func); |
106 | set_intr_w_data(func); |
79 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
- | |
80 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
- | |
81 | asi_u64_write(ASI_UDB_INTR_W, |
107 | asi_u64_write(ASI_INTR_W, |
82 | (mid << INTR_VEC_DISPATCH_MID_SHIFT) | |
108 | (mid << INTR_VEC_DISPATCH_MID_SHIFT) | |
83 | ASI_UDB_INTR_W_DISPATCH, 0); |
109 | VA_INTR_W_DISPATCH, 0); |
84 | 110 | ||
85 | membar(); |
111 | membar(); |
86 | 112 | ||
87 | do { |
113 | do { |
88 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
114 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
89 | } while (status & INTR_DISPATCH_STATUS_BUSY); |
115 | } while (status & INTR_DISPATCH_STATUS_BUSY); |
90 | 116 | ||
91 | done = !(status & INTR_DISPATCH_STATUS_NACK); |
117 | done = !(status & INTR_DISPATCH_STATUS_NACK); |
92 | if (!done) { |
118 | if (!done) { |
93 | /* |
119 | /* |
94 | * Prevent deadlock. |
120 | * Prevent deadlock. |
95 | */ |
121 | */ |
96 | (void) interrupts_enable(); |
122 | (void) interrupts_enable(); |
97 | delay(20 + (tick_read() & 0xff)); |
123 | delay(20 + (tick_read() & 0xff)); |
98 | (void) interrupts_disable(); |
124 | (void) interrupts_disable(); |
99 | } |
125 | } |
100 | } while (done); |
126 | } while (done); |
101 | 127 | ||
102 | preemption_enable(); |
128 | preemption_enable(); |
103 | } |
129 | } |
104 | 130 | ||
105 | /* |
131 | /* |
106 | * Deliver IPI to all processors except the current one. |
132 | * Deliver IPI to all processors except the current one. |
107 | * |
133 | * |
108 | * The sparc64 architecture does not support any group addressing |
134 | * The sparc64 architecture does not support any group addressing |
109 | * which is found, for instance, on ia32 and amd64. Therefore we |
135 | * which is found, for instance, on ia32 and amd64. Therefore we |
110 | * need to simulate the broadcast by sending the message to |
136 | * need to simulate the broadcast by sending the message to |
111 | * all target processors step by step. |
137 | * all target processors step by step. |
112 | * |
138 | * |
113 | * We assume that interrupts are disabled. |
139 | * We assume that interrupts are disabled. |
114 | * |
140 | * |
115 | * @param ipi IPI number. |
141 | * @param ipi IPI number. |
116 | */ |
142 | */ |
117 | void ipi_broadcast_arch(int ipi) |
143 | void ipi_broadcast_arch(int ipi) |
118 | { |
144 | { |
119 | unsigned int i; |
145 | unsigned int i; |
120 | 146 | ||
121 | void (* func)(void); |
147 | void (* func)(void); |
122 | 148 | ||
123 | switch (ipi) { |
149 | switch (ipi) { |
124 | case IPI_TLB_SHOOTDOWN: |
150 | case IPI_TLB_SHOOTDOWN: |
125 | func = tlb_shootdown_ipi_recv; |
151 | func = tlb_shootdown_ipi_recv; |
126 | break; |
152 | break; |
127 | default: |
153 | default: |
128 | panic("Unknown IPI (%d).\n", ipi); |
154 | panic("Unknown IPI (%d).", ipi); |
129 | break; |
155 | break; |
130 | } |
156 | } |
131 | 157 | ||
132 | /* |
158 | /* |
133 | * As long as we don't support hot-plugging |
159 | * As long as we don't support hot-plugging |
134 | * or hot-unplugging of CPUs, we can walk |
160 | * or hot-unplugging of CPUs, we can walk |
135 | * the cpus array and read processor's MID |
161 | * the cpus array and read processor's MID |
136 | * without locking. |
162 | * without locking. |
137 | */ |
163 | */ |
138 | 164 | ||
139 | for (i = 0; i < config.cpu_active; i++) { |
165 | for (i = 0; i < config.cpu_active; i++) { |
140 | if (&cpus[i] == CPU) |
166 | if (&cpus[i] == CPU) |
141 | continue; /* skip the current CPU */ |
167 | continue; /* skip the current CPU */ |
142 | 168 | ||
143 | cross_call(cpus[i].arch.mid, func); |
169 | cross_call(cpus[i].arch.mid, func); |
144 | } |
170 | } |
145 | } |
171 | } |
146 | 172 | ||
147 | /** @} |
173 | /** @} |
148 | */ |
174 | */ |
149 | 175 |