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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
37 | #include <mm/as.h> |
37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
41 | #include <arch/mm/mmu.h> |
41 | #include <arch/mm/mmu.h> |
42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
43 | #include <arch.h> |
43 | #include <arch.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | #include <arch/types.h> |
45 | #include <arch/types.h> |
46 | #include <typedefs.h> |
46 | #include <typedefs.h> |
47 | #include <config.h> |
47 | #include <config.h> |
48 | #include <arch/trap/trap.h> |
48 | #include <arch/trap/trap.h> |
49 | #include <panic.h> |
49 | #include <panic.h> |
50 | #include <arch/asm.h> |
50 | #include <arch/asm.h> |
51 | #include <symtab.h> |
51 | #include <symtab.h> |
52 | 52 | ||
- | 53 | static void dtlb_pte_copy(pte_t *t, bool ro); |
|
53 | static void dtlb_pte_copy(pte_t *t); |
54 | static void itlb_pte_copy(pte_t *t); |
54 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str); |
55 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str); |
- | 56 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str); |
|
55 | 57 | ||
56 | char *context_encoding[] = { |
58 | char *context_encoding[] = { |
57 | "Primary", |
59 | "Primary", |
58 | "Secondary", |
60 | "Secondary", |
59 | "Nucleus", |
61 | "Nucleus", |
60 | "Reserved" |
62 | "Reserved" |
61 | }; |
63 | }; |
62 | 64 | ||
63 | void tlb_arch_init(void) |
65 | void tlb_arch_init(void) |
64 | { |
66 | { |
65 | /* |
67 | /* |
66 | * TLBs are actually initialized early |
68 | * TLBs are actually initialized early |
67 | * in start.S. |
69 | * in start.S. |
68 | */ |
70 | */ |
69 | } |
71 | } |
70 | 72 | ||
71 | /** Insert privileged mapping into DMMU TLB. |
73 | /** Insert privileged mapping into DMMU TLB. |
72 | * |
74 | * |
73 | * @param page Virtual page address. |
75 | * @param page Virtual page address. |
74 | * @param frame Physical frame address. |
76 | * @param frame Physical frame address. |
75 | * @param pagesize Page size. |
77 | * @param pagesize Page size. |
76 | * @param locked True for permanent mappings, false otherwise. |
78 | * @param locked True for permanent mappings, false otherwise. |
77 | * @param cacheable True if the mapping is cacheable, false otherwise. |
79 | * @param cacheable True if the mapping is cacheable, false otherwise. |
78 | */ |
80 | */ |
79 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
81 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
80 | { |
82 | { |
81 | tlb_tag_access_reg_t tag; |
83 | tlb_tag_access_reg_t tag; |
82 | tlb_data_t data; |
84 | tlb_data_t data; |
83 | page_address_t pg; |
85 | page_address_t pg; |
84 | frame_address_t fr; |
86 | frame_address_t fr; |
85 | 87 | ||
86 | pg.address = page; |
88 | pg.address = page; |
87 | fr.address = frame; |
89 | fr.address = frame; |
88 | 90 | ||
89 | tag.value = ASID_KERNEL; |
91 | tag.value = ASID_KERNEL; |
90 | tag.vpn = pg.vpn; |
92 | tag.vpn = pg.vpn; |
91 | 93 | ||
92 | dtlb_tag_access_write(tag.value); |
94 | dtlb_tag_access_write(tag.value); |
93 | 95 | ||
94 | data.value = 0; |
96 | data.value = 0; |
95 | data.v = true; |
97 | data.v = true; |
96 | data.size = pagesize; |
98 | data.size = pagesize; |
97 | data.pfn = fr.pfn; |
99 | data.pfn = fr.pfn; |
98 | data.l = locked; |
100 | data.l = locked; |
99 | data.cp = cacheable; |
101 | data.cp = cacheable; |
100 | data.cv = cacheable; |
102 | data.cv = cacheable; |
101 | data.p = true; |
103 | data.p = true; |
102 | data.w = true; |
104 | data.w = true; |
103 | data.g = true; |
105 | data.g = true; |
104 | 106 | ||
105 | dtlb_data_in_write(data.value); |
107 | dtlb_data_in_write(data.value); |
106 | } |
108 | } |
107 | 109 | ||
- | 110 | /** Copy PTE to TLB. |
|
- | 111 | * |
|
- | 112 | * @param t Page Table Entry to be copied. |
|
- | 113 | * @param ro If true, the entry will be created read-only, regardless of its w field. |
|
- | 114 | */ |
|
108 | void dtlb_pte_copy(pte_t *t) |
115 | void dtlb_pte_copy(pte_t *t, bool ro) |
109 | { |
116 | { |
- | 117 | tlb_tag_access_reg_t tag; |
|
- | 118 | tlb_data_t data; |
|
- | 119 | page_address_t pg; |
|
- | 120 | frame_address_t fr; |
|
- | 121 | ||
- | 122 | pg.address = t->page; |
|
- | 123 | fr.address = t->frame; |
|
- | 124 | ||
- | 125 | tag.value = 0; |
|
- | 126 | tag.context = t->as->asid; |
|
- | 127 | tag.vpn = pg.vpn; |
|
- | 128 | ||
- | 129 | dtlb_tag_access_write(tag.value); |
|
- | 130 | ||
- | 131 | data.value = 0; |
|
- | 132 | data.v = true; |
|
- | 133 | data.size = PAGESIZE_8K; |
|
- | 134 | data.pfn = fr.pfn; |
|
- | 135 | data.l = false; |
|
- | 136 | data.cp = t->c; |
|
- | 137 | data.cv = t->c; |
|
- | 138 | data.p = t->p; |
|
- | 139 | data.w = ro ? false : t->w; |
|
- | 140 | data.g = t->g; |
|
- | 141 | ||
- | 142 | dtlb_data_in_write(data.value); |
|
- | 143 | } |
|
- | 144 | ||
- | 145 | void itlb_pte_copy(pte_t *t) |
|
- | 146 | { |
|
- | 147 | tlb_tag_access_reg_t tag; |
|
- | 148 | tlb_data_t data; |
|
- | 149 | page_address_t pg; |
|
- | 150 | frame_address_t fr; |
|
- | 151 | ||
- | 152 | pg.address = t->page; |
|
- | 153 | fr.address = t->frame; |
|
- | 154 | ||
- | 155 | tag.value = 0; |
|
- | 156 | tag.context = t->as->asid; |
|
- | 157 | tag.vpn = pg.vpn; |
|
- | 158 | ||
- | 159 | itlb_tag_access_write(tag.value); |
|
- | 160 | ||
- | 161 | data.value = 0; |
|
- | 162 | data.v = true; |
|
- | 163 | data.size = PAGESIZE_8K; |
|
- | 164 | data.pfn = fr.pfn; |
|
- | 165 | data.l = false; |
|
- | 166 | data.cp = t->c; |
|
- | 167 | data.cv = t->c; |
|
- | 168 | data.p = t->p; |
|
- | 169 | data.w = false; |
|
- | 170 | data.g = t->g; |
|
- | 171 | ||
- | 172 | itlb_data_in_write(data.value); |
|
110 | } |
173 | } |
111 | 174 | ||
112 | /** ITLB miss handler. */ |
175 | /** ITLB miss handler. */ |
113 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
176 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
114 | { |
177 | { |
- | 178 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
|
- | 179 | pte_t *t; |
|
- | 180 | ||
- | 181 | page_table_lock(AS, true); |
|
- | 182 | t = page_mapping_find(AS, va); |
|
- | 183 | if (t && PTE_EXECUTABLE(t)) { |
|
- | 184 | /* |
|
- | 185 | * The mapping was found in the software page hash table. |
|
- | 186 | * Insert it into ITLB. |
|
- | 187 | */ |
|
- | 188 | t->a = true; |
|
- | 189 | itlb_pte_copy(t); |
|
115 | panic("%s\n", __FUNCTION__); |
190 | page_table_unlock(AS, true); |
- | 191 | } else { |
|
- | 192 | /* |
|
- | 193 | * Forward the page fault to the address space page fault handler. |
|
- | 194 | */ |
|
- | 195 | page_table_unlock(AS, true); |
|
- | 196 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
|
- | 197 | do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__); |
|
- | 198 | } |
|
- | 199 | } |
|
116 | } |
200 | } |
117 | 201 | ||
118 | /** DTLB miss handler. |
202 | /** DTLB miss handler. |
119 | * |
203 | * |
120 | * Note that some faults (e.g. kernel faults) were already resolved |
204 | * Note that some faults (e.g. kernel faults) were already resolved |
121 | * by the low-level, assembly language part of the fast_data_access_mmu_miss |
205 | * by the low-level, assembly language part of the fast_data_access_mmu_miss |
122 | * handler. |
206 | * handler. |
123 | */ |
207 | */ |
124 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
208 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
125 | { |
209 | { |
126 | tlb_tag_access_reg_t tag; |
210 | tlb_tag_access_reg_t tag; |
127 | uintptr_t va; |
211 | uintptr_t va; |
128 | pte_t *t; |
212 | pte_t *t; |
129 | 213 | ||
130 | tag.value = dtlb_tag_access_read(); |
214 | tag.value = dtlb_tag_access_read(); |
131 | va = tag.vpn * PAGE_SIZE; |
215 | va = tag.vpn * PAGE_SIZE; |
132 | if (tag.context == ASID_KERNEL) { |
216 | if (tag.context == ASID_KERNEL) { |
133 | if (!tag.vpn) { |
217 | if (!tag.vpn) { |
134 | /* NULL access in kernel */ |
218 | /* NULL access in kernel */ |
135 | do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__); |
219 | do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__); |
136 | } |
220 | } |
137 | do_fast_data_access_mmu_miss_fault(istate, "Unexpected kernel page fault."); |
221 | do_fast_data_access_mmu_miss_fault(istate, "Unexpected kernel page fault."); |
138 | } |
222 | } |
139 | 223 | ||
140 | page_table_lock(AS, true); |
224 | page_table_lock(AS, true); |
141 | t = page_mapping_find(AS, va); |
225 | t = page_mapping_find(AS, va); |
142 | if (t) { |
226 | if (t) { |
143 | /* |
227 | /* |
144 | * The mapping was found in the software page hash table. |
228 | * The mapping was found in the software page hash table. |
145 | * Insert it into DTLB. |
229 | * Insert it into DTLB. |
146 | */ |
230 | */ |
- | 231 | t->a = true; |
|
147 | dtlb_pte_copy(t); |
232 | dtlb_pte_copy(t, true); |
148 | page_table_unlock(AS, true); |
233 | page_table_unlock(AS, true); |
149 | } else { |
234 | } else { |
150 | /* |
235 | /* |
151 | * Forward the page fault to the address space page fault handler. |
236 | * Forward the page fault to the address space page fault handler. |
152 | */ |
237 | */ |
153 | page_table_unlock(AS, true); |
238 | page_table_unlock(AS, true); |
154 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
239 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
155 | do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__); |
240 | do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__); |
156 | } |
241 | } |
157 | } |
242 | } |
158 | } |
243 | } |
159 | 244 | ||
160 | /** DTLB protection fault handler. */ |
245 | /** DTLB protection fault handler. */ |
161 | void fast_data_access_protection(int n, istate_t *istate) |
246 | void fast_data_access_protection(int n, istate_t *istate) |
162 | { |
247 | { |
163 | panic("%s\n", __FUNCTION__); |
248 | panic("%s\n", __FUNCTION__); |
164 | } |
249 | } |
165 | 250 | ||
166 | /** Print contents of both TLBs. */ |
251 | /** Print contents of both TLBs. */ |
167 | void tlb_print(void) |
252 | void tlb_print(void) |
168 | { |
253 | { |
169 | int i; |
254 | int i; |
170 | tlb_data_t d; |
255 | tlb_data_t d; |
171 | tlb_tag_read_reg_t t; |
256 | tlb_tag_read_reg_t t; |
172 | 257 | ||
173 | printf("I-TLB contents:\n"); |
258 | printf("I-TLB contents:\n"); |
174 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
259 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
175 | d.value = itlb_data_access_read(i); |
260 | d.value = itlb_data_access_read(i); |
176 | t.value = itlb_tag_read_read(i); |
261 | t.value = itlb_tag_read_read(i); |
177 | 262 | ||
178 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
263 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
179 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
264 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
180 | } |
265 | } |
181 | 266 | ||
182 | printf("D-TLB contents:\n"); |
267 | printf("D-TLB contents:\n"); |
183 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
268 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
184 | d.value = dtlb_data_access_read(i); |
269 | d.value = dtlb_data_access_read(i); |
185 | t.value = dtlb_tag_read_read(i); |
270 | t.value = dtlb_tag_read_read(i); |
186 | 271 | ||
187 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
272 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
188 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
273 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
189 | } |
274 | } |
190 | 275 | ||
191 | } |
276 | } |
- | 277 | ||
- | 278 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str) |
|
- | 279 | { |
|
- | 280 | char *tpc_str = get_symtab_entry(istate->tpc); |
|
- | 281 | ||
- | 282 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
|
- | 283 | panic("%s\n", str); |
|
- | 284 | } |
|
192 | 285 | ||
193 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str) |
286 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str) |
194 | { |
287 | { |
195 | tlb_tag_access_reg_t tag; |
288 | tlb_tag_access_reg_t tag; |
196 | uintptr_t va; |
289 | uintptr_t va; |
197 | char *tpc_str = get_symtab_entry(istate->tpc); |
290 | char *tpc_str = get_symtab_entry(istate->tpc); |
198 | 291 | ||
199 | tag.value = dtlb_tag_access_read(); |
292 | tag.value = dtlb_tag_access_read(); |
200 | va = tag.vpn * PAGE_SIZE; |
293 | va = tag.vpn * PAGE_SIZE; |
201 | 294 | ||
202 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
295 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
203 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
296 | printf("TPC=%p, (%s)\n", istate->tpc, tpc_str); |
204 | panic("%s\n", str); |
297 | panic("%s\n", str); |
205 | } |
298 | } |
206 | 299 | ||
207 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
300 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
208 | void tlb_invalidate_all(void) |
301 | void tlb_invalidate_all(void) |
209 | { |
302 | { |
210 | int i; |
303 | int i; |
211 | tlb_data_t d; |
304 | tlb_data_t d; |
212 | tlb_tag_read_reg_t t; |
305 | tlb_tag_read_reg_t t; |
213 | 306 | ||
214 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
307 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
215 | d.value = itlb_data_access_read(i); |
308 | d.value = itlb_data_access_read(i); |
216 | if (!d.l) { |
309 | if (!d.l) { |
217 | t.value = itlb_tag_read_read(i); |
310 | t.value = itlb_tag_read_read(i); |
218 | d.v = false; |
311 | d.v = false; |
219 | itlb_tag_access_write(t.value); |
312 | itlb_tag_access_write(t.value); |
220 | itlb_data_access_write(i, d.value); |
313 | itlb_data_access_write(i, d.value); |
221 | } |
314 | } |
222 | } |
315 | } |
223 | 316 | ||
224 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
317 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
225 | d.value = dtlb_data_access_read(i); |
318 | d.value = dtlb_data_access_read(i); |
226 | if (!d.l) { |
319 | if (!d.l) { |
227 | t.value = dtlb_tag_read_read(i); |
320 | t.value = dtlb_tag_read_read(i); |
228 | d.v = false; |
321 | d.v = false; |
229 | dtlb_tag_access_write(t.value); |
322 | dtlb_tag_access_write(t.value); |
230 | dtlb_data_access_write(i, d.value); |
323 | dtlb_data_access_write(i, d.value); |
231 | } |
324 | } |
232 | } |
325 | } |
233 | 326 | ||
234 | } |
327 | } |
235 | 328 | ||
236 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
329 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
237 | * |
330 | * |
238 | * @param asid Address Space ID. |
331 | * @param asid Address Space ID. |
239 | */ |
332 | */ |
240 | void tlb_invalidate_asid(asid_t asid) |
333 | void tlb_invalidate_asid(asid_t asid) |
241 | { |
334 | { |
242 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
335 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
243 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
336 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
244 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
337 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
245 | } |
338 | } |
246 | 339 | ||
247 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
340 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
248 | * |
341 | * |
249 | * @param asid Address Space ID. |
342 | * @param asid Address Space ID. |
250 | * @param page First page which to sweep out from ITLB and DTLB. |
343 | * @param page First page which to sweep out from ITLB and DTLB. |
251 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
344 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
252 | */ |
345 | */ |
253 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
346 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
254 | { |
347 | { |
255 | int i; |
348 | int i; |
256 | 349 | ||
257 | for (i = 0; i < cnt; i++) { |
350 | for (i = 0; i < cnt; i++) { |
258 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
351 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
259 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
352 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
260 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
353 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
261 | } |
354 | } |
262 | } |
355 | } |
263 | 356 | ||
264 | /** @} |
357 | /** @} |
265 | */ |
358 | */ |
266 | 359 |