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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_ASM_H_ |
35 | #ifndef KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
37 | 37 | ||
38 | #include <arch/arch.h> |
38 | #include <arch/arch.h> |
39 | #include <arch/types.h> |
39 | #include <arch/types.h> |
40 | #include <align.h> |
40 | #include <align.h> |
41 | #include <arch/register.h> |
41 | #include <arch/register.h> |
42 | #include <config.h> |
42 | #include <config.h> |
43 | #include <arch/stack.h> |
43 | #include <arch/stack.h> |
44 | 44 | ||
45 | /** Read Processor State register. |
45 | /** Read Processor State register. |
46 | * |
46 | * |
47 | * @return Value of PSTATE register. |
47 | * @return Value of PSTATE register. |
48 | */ |
48 | */ |
49 | static inline uint64_t pstate_read(void) |
49 | static inline uint64_t pstate_read(void) |
50 | { |
50 | { |
51 | uint64_t v; |
51 | uint64_t v; |
52 | 52 | ||
53 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
53 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
54 | 54 | ||
55 | return v; |
55 | return v; |
56 | } |
56 | } |
57 | 57 | ||
58 | /** Write Processor State register. |
58 | /** Write Processor State register. |
59 | * |
59 | * |
60 | * @param v New value of PSTATE register. |
60 | * @param v New value of PSTATE register. |
61 | */ |
61 | */ |
62 | static inline void pstate_write(uint64_t v) |
62 | static inline void pstate_write(uint64_t v) |
63 | { |
63 | { |
64 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
64 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
65 | } |
65 | } |
66 | 66 | ||
67 | /** Read TICK_compare Register. |
67 | /** Read TICK_compare Register. |
68 | * |
68 | * |
69 | * @return Value of TICK_comapre register. |
69 | * @return Value of TICK_comapre register. |
70 | */ |
70 | */ |
71 | static inline uint64_t tick_compare_read(void) |
71 | static inline uint64_t tick_compare_read(void) |
72 | { |
72 | { |
73 | uint64_t v; |
73 | uint64_t v; |
74 | 74 | ||
75 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
75 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
76 | 76 | ||
77 | return v; |
77 | return v; |
78 | } |
78 | } |
79 | 79 | ||
80 | /** Write TICK_compare Register. |
80 | /** Write TICK_compare Register. |
81 | * |
81 | * |
82 | * @param v New value of TICK_comapre register. |
82 | * @param v New value of TICK_comapre register. |
83 | */ |
83 | */ |
84 | static inline void tick_compare_write(uint64_t v) |
84 | static inline void tick_compare_write(uint64_t v) |
85 | { |
85 | { |
86 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
86 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
87 | } |
87 | } |
88 | 88 | ||
89 | /** Read TICK Register. |
89 | /** Read TICK Register. |
90 | * |
90 | * |
91 | * @return Value of TICK register. |
91 | * @return Value of TICK register. |
92 | */ |
92 | */ |
93 | static inline uint64_t tick_read(void) |
93 | static inline uint64_t tick_read(void) |
94 | { |
94 | { |
95 | uint64_t v; |
95 | uint64_t v; |
96 | 96 | ||
97 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
97 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
98 | 98 | ||
99 | return v; |
99 | return v; |
100 | } |
100 | } |
101 | 101 | ||
102 | /** Write TICK Register. |
102 | /** Write TICK Register. |
103 | * |
103 | * |
104 | * @param v New value of TICK register. |
104 | * @param v New value of TICK register. |
105 | */ |
105 | */ |
106 | static inline void tick_write(uint64_t v) |
106 | static inline void tick_write(uint64_t v) |
107 | { |
107 | { |
108 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
108 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
109 | } |
109 | } |
110 | 110 | ||
111 | /** Read FPRS Register. |
111 | /** Read FPRS Register. |
112 | * |
112 | * |
113 | * @return Value of FPRS register. |
113 | * @return Value of FPRS register. |
114 | */ |
114 | */ |
115 | static inline uint64_t fprs_read(void) |
115 | static inline uint64_t fprs_read(void) |
116 | { |
116 | { |
117 | uint64_t v; |
117 | uint64_t v; |
118 | 118 | ||
119 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
119 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
120 | 120 | ||
121 | return v; |
121 | return v; |
122 | } |
122 | } |
123 | 123 | ||
124 | /** Write FPRS Register. |
124 | /** Write FPRS Register. |
125 | * |
125 | * |
126 | * @param v New value of FPRS register. |
126 | * @param v New value of FPRS register. |
127 | */ |
127 | */ |
128 | static inline void fprs_write(uint64_t v) |
128 | static inline void fprs_write(uint64_t v) |
129 | { |
129 | { |
130 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
130 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
131 | } |
131 | } |
132 | 132 | ||
133 | /** Read SOFTINT Register. |
133 | /** Read SOFTINT Register. |
134 | * |
134 | * |
135 | * @return Value of SOFTINT register. |
135 | * @return Value of SOFTINT register. |
136 | */ |
136 | */ |
137 | static inline uint64_t softint_read(void) |
137 | static inline uint64_t softint_read(void) |
138 | { |
138 | { |
139 | uint64_t v; |
139 | uint64_t v; |
140 | 140 | ||
141 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
141 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
142 | 142 | ||
143 | return v; |
143 | return v; |
144 | } |
144 | } |
145 | 145 | ||
146 | /** Write SOFTINT Register. |
146 | /** Write SOFTINT Register. |
147 | * |
147 | * |
148 | * @param v New value of SOFTINT register. |
148 | * @param v New value of SOFTINT register. |
149 | */ |
149 | */ |
150 | static inline void softint_write(uint64_t v) |
150 | static inline void softint_write(uint64_t v) |
151 | { |
151 | { |
152 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
152 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
153 | } |
153 | } |
154 | 154 | ||
155 | /** Write CLEAR_SOFTINT Register. |
155 | /** Write CLEAR_SOFTINT Register. |
156 | * |
156 | * |
157 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
157 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
158 | * |
158 | * |
159 | * @param v New value of CLEAR_SOFTINT register. |
159 | * @param v New value of CLEAR_SOFTINT register. |
160 | */ |
160 | */ |
161 | static inline void clear_softint_write(uint64_t v) |
161 | static inline void clear_softint_write(uint64_t v) |
162 | { |
162 | { |
163 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
163 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
164 | } |
164 | } |
165 | 165 | ||
166 | /** Write SET_SOFTINT Register. |
166 | /** Write SET_SOFTINT Register. |
167 | * |
167 | * |
168 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
168 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
169 | * |
169 | * |
170 | * @param v New value of SET_SOFTINT register. |
170 | * @param v New value of SET_SOFTINT register. |
171 | */ |
171 | */ |
172 | static inline void set_softint_write(uint64_t v) |
172 | static inline void set_softint_write(uint64_t v) |
173 | { |
173 | { |
174 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
174 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
175 | } |
175 | } |
176 | 176 | ||
177 | /** Enable interrupts. |
177 | /** Enable interrupts. |
178 | * |
178 | * |
179 | * Enable interrupts and return previous |
179 | * Enable interrupts and return previous |
180 | * value of IPL. |
180 | * value of IPL. |
181 | * |
181 | * |
182 | * @return Old interrupt priority level. |
182 | * @return Old interrupt priority level. |
183 | */ |
183 | */ |
184 | static inline ipl_t interrupts_enable(void) { |
184 | static inline ipl_t interrupts_enable(void) { |
185 | pstate_reg_t pstate; |
185 | pstate_reg_t pstate; |
186 | uint64_t value; |
186 | uint64_t value; |
187 | 187 | ||
188 | value = pstate_read(); |
188 | value = pstate_read(); |
189 | pstate.value = value; |
189 | pstate.value = value; |
190 | pstate.ie = true; |
190 | pstate.ie = true; |
191 | pstate_write(pstate.value); |
191 | pstate_write(pstate.value); |
192 | 192 | ||
193 | return (ipl_t) value; |
193 | return (ipl_t) value; |
194 | } |
194 | } |
195 | 195 | ||
196 | /** Disable interrupts. |
196 | /** Disable interrupts. |
197 | * |
197 | * |
198 | * Disable interrupts and return previous |
198 | * Disable interrupts and return previous |
199 | * value of IPL. |
199 | * value of IPL. |
200 | * |
200 | * |
201 | * @return Old interrupt priority level. |
201 | * @return Old interrupt priority level. |
202 | */ |
202 | */ |
203 | static inline ipl_t interrupts_disable(void) { |
203 | static inline ipl_t interrupts_disable(void) { |
204 | pstate_reg_t pstate; |
204 | pstate_reg_t pstate; |
205 | uint64_t value; |
205 | uint64_t value; |
206 | 206 | ||
207 | value = pstate_read(); |
207 | value = pstate_read(); |
208 | pstate.value = value; |
208 | pstate.value = value; |
209 | pstate.ie = false; |
209 | pstate.ie = false; |
210 | pstate_write(pstate.value); |
210 | pstate_write(pstate.value); |
211 | 211 | ||
212 | return (ipl_t) value; |
212 | return (ipl_t) value; |
213 | } |
213 | } |
214 | 214 | ||
215 | /** Restore interrupt priority level. |
215 | /** Restore interrupt priority level. |
216 | * |
216 | * |
217 | * Restore IPL. |
217 | * Restore IPL. |
218 | * |
218 | * |
219 | * @param ipl Saved interrupt priority level. |
219 | * @param ipl Saved interrupt priority level. |
220 | */ |
220 | */ |
221 | static inline void interrupts_restore(ipl_t ipl) { |
221 | static inline void interrupts_restore(ipl_t ipl) { |
222 | pstate_reg_t pstate; |
222 | pstate_reg_t pstate; |
223 | 223 | ||
224 | pstate.value = pstate_read(); |
224 | pstate.value = pstate_read(); |
225 | pstate.ie = ((pstate_reg_t) ipl).ie; |
225 | pstate.ie = ((pstate_reg_t) ipl).ie; |
226 | pstate_write(pstate.value); |
226 | pstate_write(pstate.value); |
227 | } |
227 | } |
228 | 228 | ||
229 | /** Return interrupt priority level. |
229 | /** Return interrupt priority level. |
230 | * |
230 | * |
231 | * Return IPL. |
231 | * Return IPL. |
232 | * |
232 | * |
233 | * @return Current interrupt priority level. |
233 | * @return Current interrupt priority level. |
234 | */ |
234 | */ |
235 | static inline ipl_t interrupts_read(void) { |
235 | static inline ipl_t interrupts_read(void) { |
236 | return (ipl_t) pstate_read(); |
236 | return (ipl_t) pstate_read(); |
237 | } |
237 | } |
238 | 238 | ||
239 | /** Return base address of current stack. |
239 | /** Return base address of current stack. |
240 | * |
240 | * |
241 | * Return the base address of the current stack. |
241 | * Return the base address of the current stack. |
242 | * The stack is assumed to be STACK_SIZE bytes long. |
242 | * The stack is assumed to be STACK_SIZE bytes long. |
243 | * The stack must start on page boundary. |
243 | * The stack must start on page boundary. |
244 | */ |
244 | */ |
245 | static inline uintptr_t get_stack_base(void) |
245 | static inline uintptr_t get_stack_base(void) |
246 | { |
246 | { |
247 | uintptr_t unbiased_sp; |
247 | uintptr_t unbiased_sp; |
248 | 248 | ||
249 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
249 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
250 | 250 | ||
251 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
251 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
252 | } |
252 | } |
253 | 253 | ||
254 | /** Read Version Register. |
254 | /** Read Version Register. |
255 | * |
255 | * |
256 | * @return Value of VER register. |
256 | * @return Value of VER register. |
257 | */ |
257 | */ |
258 | static inline uint64_t ver_read(void) |
258 | static inline uint64_t ver_read(void) |
259 | { |
259 | { |
260 | uint64_t v; |
260 | uint64_t v; |
261 | 261 | ||
262 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
262 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
263 | 263 | ||
264 | return v; |
264 | return v; |
265 | } |
265 | } |
266 | 266 | ||
267 | /** Read Trap Program Counter register. |
267 | /** Read Trap Program Counter register. |
268 | * |
268 | * |
269 | * @return Current value in TPC. |
269 | * @return Current value in TPC. |
270 | */ |
270 | */ |
271 | static inline uint64_t tpc_read(void) |
271 | static inline uint64_t tpc_read(void) |
272 | { |
272 | { |
273 | uint64_t v; |
273 | uint64_t v; |
274 | 274 | ||
275 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
275 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
276 | 276 | ||
277 | return v; |
277 | return v; |
278 | } |
278 | } |
279 | 279 | ||
280 | /** Read Trap Level register. |
280 | /** Read Trap Level register. |
281 | * |
281 | * |
282 | * @return Current value in TL. |
282 | * @return Current value in TL. |
283 | */ |
283 | */ |
284 | static inline uint64_t tl_read(void) |
284 | static inline uint64_t tl_read(void) |
285 | { |
285 | { |
286 | uint64_t v; |
286 | uint64_t v; |
287 | 287 | ||
288 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
288 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
289 | 289 | ||
290 | return v; |
290 | return v; |
291 | } |
291 | } |
292 | 292 | ||
293 | /** Read Trap Base Address register. |
293 | /** Read Trap Base Address register. |
294 | * |
294 | * |
295 | * @return Current value in TBA. |
295 | * @return Current value in TBA. |
296 | */ |
296 | */ |
297 | static inline uint64_t tba_read(void) |
297 | static inline uint64_t tba_read(void) |
298 | { |
298 | { |
299 | uint64_t v; |
299 | uint64_t v; |
300 | 300 | ||
301 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
301 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
302 | 302 | ||
303 | return v; |
303 | return v; |
304 | } |
304 | } |
305 | 305 | ||
306 | /** Write Trap Base Address register. |
306 | /** Write Trap Base Address register. |
307 | * |
307 | * |
308 | * @param v New value of TBA. |
308 | * @param v New value of TBA. |
309 | */ |
309 | */ |
310 | static inline void tba_write(uint64_t v) |
310 | static inline void tba_write(uint64_t v) |
311 | { |
311 | { |
312 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
312 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
313 | } |
313 | } |
314 | 314 | ||
315 | /** Load uint64_t from alternate space. |
315 | /** Load uint64_t from alternate space. |
316 | * |
316 | * |
317 | * @param asi ASI determining the alternate space. |
317 | * @param asi ASI determining the alternate space. |
318 | * @param va Virtual address within the ASI. |
318 | * @param va Virtual address within the ASI. |
319 | * |
319 | * |
320 | * @return Value read from the virtual address in the specified address space. |
320 | * @return Value read from the virtual address in the specified address space. |
321 | */ |
321 | */ |
322 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
322 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
323 | { |
323 | { |
324 | uint64_t v; |
324 | uint64_t v; |
325 | 325 | ||
326 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
326 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
327 | 327 | ||
328 | return v; |
328 | return v; |
329 | } |
329 | } |
330 | 330 | ||
331 | /** Store uint64_t to alternate space. |
331 | /** Store uint64_t to alternate space. |
332 | * |
332 | * |
333 | * @param asi ASI determining the alternate space. |
333 | * @param asi ASI determining the alternate space. |
334 | * @param va Virtual address within the ASI. |
334 | * @param va Virtual address within the ASI. |
335 | * @param v Value to be written. |
335 | * @param v Value to be written. |
336 | */ |
336 | */ |
337 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
337 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
338 | { |
338 | { |
339 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
339 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
340 | } |
340 | } |
341 | 341 | ||
342 | /** Flush all valid register windows to memory. */ |
342 | /** Flush all valid register windows to memory. */ |
343 | static inline void flushw(void) |
343 | static inline void flushw(void) |
344 | { |
344 | { |
345 | asm volatile ("flushw\n"); |
345 | asm volatile ("flushw\n"); |
346 | } |
346 | } |
347 | 347 | ||
348 | /** Switch to nucleus by setting TL to 1. */ |
348 | /** Switch to nucleus by setting TL to 1. */ |
349 | static inline void nucleus_enter(void) |
349 | static inline void nucleus_enter(void) |
350 | { |
350 | { |
351 | asm volatile ("wrpr %g0, 1, %tl\n"); |
351 | asm volatile ("wrpr %g0, 1, %tl\n"); |
352 | } |
352 | } |
353 | 353 | ||
354 | /** Switch from nucleus by setting TL to 0. */ |
354 | /** Switch from nucleus by setting TL to 0. */ |
355 | static inline void nucleus_leave(void) |
355 | static inline void nucleus_leave(void) |
356 | { |
356 | { |
357 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
357 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
358 | } |
358 | } |
359 | 359 | ||
360 | /** Read UPA_CONFIG register. |
360 | /** Read UPA_CONFIG register. |
361 | * |
361 | * |
362 | * @return Value of the UPA_CONFIG register. |
362 | * @return Value of the UPA_CONFIG register. |
363 | */ |
363 | */ |
364 | static inline uint64_t upa_config_read(void) |
364 | static inline uint64_t upa_config_read(void) |
365 | { |
365 | { |
366 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
366 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
367 | } |
367 | } |
368 | 368 | ||
369 | extern void cpu_halt(void); |
369 | extern void cpu_halt(void); |
370 | extern void cpu_sleep(void); |
370 | extern void cpu_sleep(void); |
371 | extern void asm_delay_loop(const uint32_t usec); |
371 | extern void asm_delay_loop(const uint32_t usec); |
372 | 372 | ||
373 | extern uint64_t read_from_ag_g7(void); |
373 | extern uint64_t read_from_ag_g7(void); |
374 | extern void write_to_ag_g6(uint64_t val); |
374 | extern void write_to_ag_g6(uint64_t val); |
375 | extern void write_to_ag_g7(uint64_t val); |
375 | extern void write_to_ag_g7(uint64_t val); |
376 | extern void write_to_ig_g6(uint64_t val); |
376 | extern void write_to_ig_g6(uint64_t val); |
377 | 377 | ||
378 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
378 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
379 | 379 | ||
380 | #endif |
380 | #endif |
381 | 381 | ||
382 | /** @} |
382 | /** @} |
383 | */ |
383 | */ |
384 | 384 |