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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
| 36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
| 37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
| - | 38 | #include <interrupt.h> |
|
| 38 | #include <mm/as.h> |
39 | #include <mm/as.h> |
| 39 | #include <arch.h> |
40 | #include <arch.h> |
| 40 | #include <print.h> |
41 | #include <print.h> |
| - | 42 | #include <macros.h> |
|
| 41 | #include <symtab.h> |
43 | #include <symtab.h> |
| 42 | 44 | ||
| - | 45 | static unsigned int seed = 10; |
|
| - | 46 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
|
| - | 47 | ||
| - | 48 | ||
| - | 49 | #define TLB_FLUSH \ |
|
| - | 50 | "tlbie %0\n" \ |
|
| - | 51 | "addi %0, %0, 0x1000\n" |
|
| - | 52 | ||
| 43 | 53 | ||
| 44 | /** Try to find PTE for faulting address |
54 | /** Try to find PTE for faulting address |
| 45 | * |
55 | * |
| 46 | * Try to find PTE for faulting address. |
56 | * Try to find PTE for faulting address. |
| 47 | * The as->lock must be held on entry to this function |
57 | * The as->lock must be held on entry to this function |
| 48 | * if lock is true. |
58 | * if lock is true. |
| 49 | * |
59 | * |
| 50 | * @param as Address space. |
60 | * @param as Address space. |
| 51 | * @param lock Lock/unlock the address space. |
61 | * @param lock Lock/unlock the address space. |
| 52 | * @param badvaddr Faulting virtual address. |
62 | * @param badvaddr Faulting virtual address. |
| 53 | * @param access Access mode that caused the fault. |
63 | * @param access Access mode that caused the fault. |
| 54 | * @param istate Pointer to interrupted state. |
64 | * @param istate Pointer to interrupted state. |
| 55 | * @param pfrc Pointer to variable where as_page_fault() return code |
65 | * @param pfrc Pointer to variable where as_page_fault() return code |
| 56 | * will be stored. |
66 | * will be stored. |
| 57 | * @return PTE on success, NULL otherwise. |
67 | * @return PTE on success, NULL otherwise. |
| 58 | * |
68 | * |
| 59 | */ |
69 | */ |
| 60 | static pte_t * |
70 | static pte_t * |
| 61 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
71 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
| 62 | istate_t *istate, int *pfrc) |
72 | istate_t *istate, int *pfrc) |
| 63 | { |
73 | { |
| 64 | /* |
74 | /* |
| 65 | * Check if the mapping exists in page tables. |
75 | * Check if the mapping exists in page tables. |
| 66 | */ |
76 | */ |
| 67 | pte_t *pte = page_mapping_find(as, badvaddr); |
77 | pte_t *pte = page_mapping_find(as, badvaddr); |
| 68 | if ((pte) && (pte->p)) { |
78 | if ((pte) && (pte->present)) { |
| 69 | /* |
79 | /* |
| 70 | * Mapping found in page tables. |
80 | * Mapping found in page tables. |
| 71 | * Immediately succeed. |
81 | * Immediately succeed. |
| 72 | */ |
82 | */ |
| 73 | return pte; |
83 | return pte; |
| 74 | } else { |
84 | } else { |
| 75 | int rc; |
85 | int rc; |
| 76 | 86 | ||
| 77 | /* |
87 | /* |
| 78 | * Mapping not found in page tables. |
88 | * Mapping not found in page tables. |
| 79 | * Resort to higher-level page fault handler. |
89 | * Resort to higher-level page fault handler. |
| 80 | */ |
90 | */ |
| 81 | page_table_unlock(as, lock); |
91 | page_table_unlock(as, lock); |
| 82 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
92 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
| 83 | case AS_PF_OK: |
93 | case AS_PF_OK: |
| 84 | /* |
94 | /* |
| 85 | * The higher-level page fault handler succeeded, |
95 | * The higher-level page fault handler succeeded, |
| 86 | * The mapping ought to be in place. |
96 | * The mapping ought to be in place. |
| 87 | */ |
97 | */ |
| 88 | page_table_lock(as, lock); |
98 | page_table_lock(as, lock); |
| 89 | pte = page_mapping_find(as, badvaddr); |
99 | pte = page_mapping_find(as, badvaddr); |
| 90 | ASSERT((pte) && (pte->p)); |
100 | ASSERT((pte) && (pte->present)); |
| 91 | *pfrc = 0; |
101 | *pfrc = 0; |
| 92 | return pte; |
102 | return pte; |
| 93 | case AS_PF_DEFER: |
103 | case AS_PF_DEFER: |
| 94 | page_table_lock(as, lock); |
104 | page_table_lock(as, lock); |
| 95 | *pfrc = rc; |
105 | *pfrc = rc; |
| 96 | return NULL; |
106 | return NULL; |
| 97 | case AS_PF_FAULT: |
107 | case AS_PF_FAULT: |
| 98 | page_table_lock(as, lock); |
108 | page_table_lock(as, lock); |
| 99 | printf("Page fault.\n"); |
- | |
| 100 | *pfrc = rc; |
109 | *pfrc = rc; |
| 101 | return NULL; |
110 | return NULL; |
| 102 | default: |
111 | default: |
| 103 | panic("unexpected rc (%d)\n", rc); |
112 | panic("Unexpected rc (%d).", rc); |
| 104 | } |
113 | } |
| 105 | } |
114 | } |
| 106 | } |
115 | } |
| 107 | 116 | ||
| 108 | 117 | ||
| 109 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
118 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
| 110 | { |
119 | { |
| 111 | char *symbol = ""; |
120 | char *symbol; |
| 112 | char *sym2 = ""; |
121 | char *sym2; |
| 113 | 122 | ||
| 114 | char *s = get_symtab_entry(istate->pc); |
123 | symbol = symtab_fmt_name_lookup(istate->pc); |
| 115 | if (s) |
- | |
| 116 | symbol = s; |
- | |
| 117 | s = get_symtab_entry(istate->lr); |
124 | sym2 = symtab_fmt_name_lookup(istate->lr); |
| 118 | if (s) |
125 | |
| 119 | sym2 = s; |
126 | fault_if_from_uspace(istate, |
| - | 127 | "PHT Refill Exception on %p.", badvaddr); |
|
| 120 | panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, |
128 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
| 121 | istate->pc, symbol, sym2); |
129 | istate->pc, symbol, sym2); |
| 122 | } |
130 | } |
| 123 | 131 | ||
| 124 | 132 | ||
| 125 | static void pht_insert(const uintptr_t vaddr, const pfn_t pfn) |
133 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
| 126 | { |
134 | { |
| 127 | uint32_t page = (vaddr >> 12) & 0xffff; |
135 | uint32_t page = (vaddr >> 12) & 0xffff; |
| 128 | uint32_t api = (vaddr >> 22) & 0x3f; |
136 | uint32_t api = (vaddr >> 22) & 0x3f; |
| 129 | 137 | ||
| 130 | uint32_t vsid; |
138 | uint32_t vsid; |
| 131 | asm volatile ( |
139 | asm volatile ( |
| 132 | "mfsrin %0, %1\n" |
140 | "mfsrin %0, %1\n" |
| 133 | : "=r" (vsid) |
141 | : "=r" (vsid) |
| 134 | : "r" (vaddr) |
142 | : "r" (vaddr) |
| 135 | ); |
143 | ); |
| 136 | 144 | ||
| 137 | uint32_t sdr1; |
145 | uint32_t sdr1; |
| 138 | asm volatile ( |
146 | asm volatile ( |
| 139 | "mfsdr1 %0\n" |
147 | "mfsdr1 %0\n" |
| 140 | : "=r" (sdr1) |
148 | : "=r" (sdr1) |
| 141 | ); |
149 | ); |
| 142 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
150 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
| 143 | 151 | ||
| 144 | /* Primary hash (xor) */ |
152 | /* Primary hash (xor) */ |
| 145 | uint32_t h = 0; |
153 | uint32_t h = 0; |
| 146 | uint32_t hash = vsid ^ page; |
154 | uint32_t hash = vsid ^ page; |
| 147 | uint32_t base = (hash & 0x3ff) << 3; |
155 | uint32_t base = (hash & 0x3ff) << 3; |
| 148 | uint32_t i; |
156 | uint32_t i; |
| 149 | bool found = false; |
157 | bool found = false; |
| 150 | 158 | ||
| 151 | /* Find unused or colliding |
- | |
| 152 | PTE in PTEG */ |
159 | /* Find colliding PTE in PTEG */ |
| 153 | for (i = 0; i < 8; i++) { |
160 | for (i = 0; i < 8; i++) { |
| - | 161 | if ((phte[base + i].v) |
|
| 154 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && |
162 | && (phte[base + i].vsid == vsid) |
| 155 | (phte[base + i].api == api))) { |
163 | && (phte[base + i].api == api) |
| - | 164 | && (phte[base + i].h == 0)) { |
|
| 156 | found = true; |
165 | found = true; |
| 157 | break; |
166 | break; |
| 158 | } |
167 | } |
| 159 | } |
168 | } |
| 160 | 169 | ||
| 161 | if (!found) { |
170 | if (!found) { |
| 162 | /* Secondary hash (not) */ |
- | |
| 163 | uint32_t base2 = (~hash & 0x3ff) << 3; |
- | |
| 164 | - | ||
| 165 | /* Find unused or colliding |
171 | /* Find unused PTE in PTEG */ |
| 166 | PTE in PTEG */ |
- | |
| 167 | for (i = 0; i < 8; i++) { |
172 | for (i = 0; i < 8; i++) { |
| 168 | if ((!phte[base2 + i].v) || |
173 | if (!phte[base + i].v) { |
| 169 | ((phte[base2 + i].vsid == vsid) && |
- | |
| 170 | (phte[base2 + i].api == api))) { |
- | |
| 171 | found = true; |
174 | found = true; |
| 172 | base = base2; |
- | |
| 173 | h = 1; |
- | |
| 174 | break; |
175 | break; |
| 175 | } |
176 | } |
| 176 | } |
177 | } |
| 177 | - | ||
| 178 | if (!found) { |
- | |
| 179 | // TODO: A/C precedence groups |
- | |
| 180 | i = page % 8; |
- | |
| 181 | } |
- | |
| 182 | } |
- | |
| 183 | - | ||
| 184 | phte[base + i].v = 1; |
- | |
| 185 | phte[base + i].vsid = vsid; |
- | |
| 186 | phte[base + i].h = h; |
- | |
| 187 | phte[base + i].api = api; |
- | |
| 188 | phte[base + i].rpn = pfn; |
- | |
| 189 | phte[base + i].r = 0; |
- | |
| 190 | phte[base + i].c = 0; |
- | |
| 191 | phte[base + i].pp = 2; // FIXME |
- | |
| 192 | } |
- | |
| 193 | - | ||
| 194 | - | ||
| 195 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
- | |
| 196 | { |
- | |
| 197 | uint32_t page = (vaddr >> 12) & 0xffff; |
- | |
| 198 | uint32_t api = (vaddr >> 22) & 0x3f; |
- | |
| 199 | - | ||
| 200 | uint32_t vsid; |
- | |
| 201 | asm volatile ( |
- | |
| 202 | "mfsrin %0, %1\n" |
- | |
| 203 | : "=r" (vsid) |
- | |
| 204 | : "r" (vaddr) |
- | |
| 205 | ); |
- | |
| 206 | - | ||
| 207 | uint32_t sdr1; |
- | |
| 208 | asm volatile ( |
- | |
| 209 | "mfsdr1 %0\n" |
- | |
| 210 | : "=r" (sdr1) |
- | |
| 211 | ); |
- | |
| 212 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
- | |
| 213 | - | ||
| 214 | /* Primary hash (xor) */ |
- | |
| 215 | uint32_t h = 0; |
- | |
| 216 | uint32_t hash = vsid ^ page; |
- | |
| 217 | uint32_t base = (hash & 0x3ff) << 3; |
- | |
| 218 | uint32_t i; |
- | |
| 219 | bool found = false; |
- | |
| 220 | - | ||
| 221 | /* Find unused or colliding |
- | |
| 222 | PTE in PTEG */ |
- | |
| 223 | for (i = 0; i < 8; i++) { |
- | |
| 224 | if ((!phte_physical[base + i].v) || |
- | |
| 225 | ((phte_physical[base + i].vsid == vsid) && |
- | |
| 226 | (phte_physical[base + i].api == api))) { |
- | |
| 227 | found = true; |
- | |
| 228 | break; |
- | |
| 229 | } |
- | |
| 230 | } |
178 | } |
| 231 | 179 | ||
| 232 | if (!found) { |
180 | if (!found) { |
| 233 | /* Secondary hash (not) */ |
181 | /* Secondary hash (not) */ |
| 234 | uint32_t base2 = (~hash & 0x3ff) << 3; |
182 | uint32_t base2 = (~hash & 0x3ff) << 3; |
| 235 | 183 | ||
| 236 | /* Find unused or colliding |
- | |
| 237 | PTE in PTEG */ |
184 | /* Find colliding PTE in PTEG */ |
| 238 | for (i = 0; i < 8; i++) { |
185 | for (i = 0; i < 8; i++) { |
| 239 | if ((!phte_physical[base2 + i].v) || |
186 | if ((phte[base2 + i].v) |
| 240 | ((phte_physical[base2 + i].vsid == vsid) && |
187 | && (phte[base2 + i].vsid == vsid) |
| 241 | (phte_physical[base2 + i].api == api))) { |
188 | && (phte[base2 + i].api == api) |
| - | 189 | && (phte[base2 + i].h == 1)) { |
|
| 242 | found = true; |
190 | found = true; |
| 243 | base = base2; |
191 | base = base2; |
| 244 | h = 1; |
192 | h = 1; |
| 245 | break; |
193 | break; |
| 246 | } |
194 | } |
| 247 | } |
195 | } |
| 248 | 196 | ||
| 249 | if (!found) { |
197 | if (!found) { |
| 250 | // TODO: A/C precedence groups |
198 | /* Find unused PTE in PTEG */ |
| - | 199 | for (i = 0; i < 8; i++) { |
|
| - | 200 | if (!phte[base2 + i].v) { |
|
| - | 201 | found = true; |
|
| 251 | i = page % 8; |
202 | base = base2; |
| - | 203 | h = 1; |
|
| - | 204 | break; |
|
| - | 205 | } |
|
| - | 206 | } |
|
| 252 | } |
207 | } |
| - | 208 | ||
| - | 209 | if (!found) |
|
| - | 210 | i = RANDI(seed) % 8; |
|
| 253 | } |
211 | } |
| 254 | 212 | ||
| 255 | phte_physical[base + i].v = 1; |
213 | phte[base + i].v = 1; |
| 256 | phte_physical[base + i].vsid = vsid; |
214 | phte[base + i].vsid = vsid; |
| 257 | phte_physical[base + i].h = h; |
215 | phte[base + i].h = h; |
| 258 | phte_physical[base + i].api = api; |
216 | phte[base + i].api = api; |
| 259 | phte_physical[base + i].rpn = pfn; |
217 | phte[base + i].rpn = pte->pfn; |
| 260 | phte_physical[base + i].r = 0; |
218 | phte[base + i].r = 0; |
| 261 | phte_physical[base + i].c = 0; |
219 | phte[base + i].c = 0; |
| - | 220 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
|
| 262 | phte_physical[base + i].pp = 2; // FIXME |
221 | phte[base + i].pp = 2; // FIXME |
| 263 | } |
222 | } |
| 264 | 223 | ||
| 265 | 224 | ||
| 266 | /** Process Instruction/Data Storage Interrupt |
225 | /** Process Instruction/Data Storage Exception |
| 267 | * |
226 | * |
| 268 | * @param n Interrupt vector number. |
227 | * @param n Exception vector number. |
| 269 | * @param istate Interrupted register context. |
228 | * @param istate Interrupted register context. |
| 270 | * |
229 | * |
| 271 | */ |
230 | */ |
| 272 | void pht_refill(int n, istate_t *istate) |
231 | void pht_refill(int n, istate_t *istate) |
| 273 | { |
232 | { |
| 274 | uintptr_t badvaddr; |
233 | uintptr_t badvaddr; |
| 275 | pte_t *pte; |
234 | pte_t *pte; |
| 276 | int pfrc; |
235 | int pfrc; |
| 277 | as_t *as; |
236 | as_t *as; |
| 278 | bool lock; |
237 | bool lock; |
| 279 | 238 | ||
| 280 | if (AS == NULL) { |
239 | if (AS == NULL) { |
| 281 | as = AS_KERNEL; |
240 | as = AS_KERNEL; |
| 282 | lock = false; |
241 | lock = false; |
| 283 | } else { |
242 | } else { |
| 284 | as = AS; |
243 | as = AS; |
| 285 | lock = true; |
244 | lock = true; |
| 286 | } |
245 | } |
| 287 | 246 | ||
| 288 | if (n == VECTOR_DATA_STORAGE) { |
247 | if (n == VECTOR_DATA_STORAGE) |
| 289 | asm volatile ( |
- | |
| 290 | "mfdar %0\n" |
- | |
| 291 | : "=r" (badvaddr) |
248 | badvaddr = istate->dar; |
| 292 | ); |
- | |
| 293 | } else |
249 | else |
| 294 | badvaddr = istate->pc; |
250 | badvaddr = istate->pc; |
| 295 | 251 | ||
| 296 | page_table_lock(as, lock); |
252 | page_table_lock(as, lock); |
| 297 | 253 | ||
| 298 | pte = find_mapping_and_check(as, lock, badvaddr, |
254 | pte = find_mapping_and_check(as, lock, badvaddr, |
| 299 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
255 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
| 300 | if (!pte) { |
256 | if (!pte) { |
| 301 | switch (pfrc) { |
257 | switch (pfrc) { |
| 302 | case AS_PF_FAULT: |
258 | case AS_PF_FAULT: |
| 303 | goto fail; |
259 | goto fail; |
| 304 | break; |
260 | break; |
| 305 | case AS_PF_DEFER: |
261 | case AS_PF_DEFER: |
| 306 | /* |
262 | /* |
| 307 | * The page fault came during copy_from_uspace() |
263 | * The page fault came during copy_from_uspace() |
| 308 | * or copy_to_uspace(). |
264 | * or copy_to_uspace(). |
| 309 | */ |
265 | */ |
| 310 | page_table_unlock(as, lock); |
266 | page_table_unlock(as, lock); |
| 311 | return; |
267 | return; |
| 312 | default: |
268 | default: |
| 313 | panic("Unexpected pfrc (%d)\n", pfrc); |
269 | panic("Unexpected pfrc (%d).", pfrc); |
| 314 | } |
270 | } |
| 315 | } |
271 | } |
| 316 | 272 | ||
| 317 | pte->a = 1; /* Record access to PTE */ |
273 | pte->accessed = 1; /* Record access to PTE */ |
| 318 | pht_insert(badvaddr, pte->pfn); |
274 | pht_insert(badvaddr, pte); |
| 319 | 275 | ||
| 320 | page_table_unlock(as, lock); |
276 | page_table_unlock(as, lock); |
| 321 | return; |
277 | return; |
| 322 | 278 | ||
| 323 | fail: |
279 | fail: |
| 324 | page_table_unlock(as, lock); |
280 | page_table_unlock(as, lock); |
| 325 | pht_refill_fail(badvaddr, istate); |
281 | pht_refill_fail(badvaddr, istate); |
| 326 | } |
282 | } |
| 327 | 283 | ||
| 328 | 284 | ||
| 329 | /** Process Instruction/Data Storage Interrupt in Real Mode |
285 | /** Process Instruction/Data Storage Exception in Real Mode |
| 330 | * |
286 | * |
| 331 | * @param n Interrupt vector number. |
287 | * @param n Exception vector number. |
| 332 | * @param istate Interrupted register context. |
288 | * @param istate Interrupted register context. |
| 333 | * |
289 | * |
| 334 | */ |
290 | */ |
| 335 | bool pht_real_refill(int n, istate_t *istate) |
291 | bool pht_refill_real(int n, istate_t *istate) |
| 336 | { |
292 | { |
| 337 | uintptr_t badvaddr; |
293 | uintptr_t badvaddr; |
| 338 | 294 | ||
| 339 | if (n == VECTOR_DATA_STORAGE) { |
295 | if (n == VECTOR_DATA_STORAGE) |
| 340 | asm volatile ( |
- | |
| 341 | "mfdar %0\n" |
- | |
| 342 | : "=r" (badvaddr) |
296 | badvaddr = istate->dar; |
| 343 | ); |
- | |
| 344 | } else |
297 | else |
| 345 | badvaddr = istate->pc; |
298 | badvaddr = istate->pc; |
| 346 | 299 | ||
| 347 | uint32_t physmem; |
300 | uint32_t physmem; |
| 348 | asm volatile ( |
301 | asm volatile ( |
| 349 | "mfsprg3 %0\n" |
302 | "mfsprg3 %0\n" |
| 350 | : "=r" (physmem) |
303 | : "=r" (physmem) |
| 351 | ); |
304 | ); |
| 352 | 305 | ||
| 353 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
306 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
| - | 307 | return false; |
|
| - | 308 | ||
| - | 309 | uint32_t page = (badvaddr >> 12) & 0xffff; |
|
| 354 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
310 | uint32_t api = (badvaddr >> 22) & 0x3f; |
| - | 311 | ||
| - | 312 | uint32_t vsid; |
|
| - | 313 | asm volatile ( |
|
| - | 314 | "mfsrin %0, %1\n" |
|
| - | 315 | : "=r" (vsid) |
|
| - | 316 | : "r" (badvaddr) |
|
| - | 317 | ); |
|
| - | 318 | ||
| - | 319 | uint32_t sdr1; |
|
| - | 320 | asm volatile ( |
|
| - | 321 | "mfsdr1 %0\n" |
|
| - | 322 | : "=r" (sdr1) |
|
| - | 323 | ); |
|
| - | 324 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
|
| - | 325 | ||
| - | 326 | /* Primary hash (xor) */ |
|
| - | 327 | uint32_t h = 0; |
|
| - | 328 | uint32_t hash = vsid ^ page; |
|
| - | 329 | uint32_t base = (hash & 0x3ff) << 3; |
|
| - | 330 | uint32_t i; |
|
| - | 331 | bool found = false; |
|
| - | 332 | ||
| - | 333 | /* Find colliding PTE in PTEG */ |
|
| - | 334 | for (i = 0; i < 8; i++) { |
|
| - | 335 | if ((phte_real[base + i].v) |
|
| - | 336 | && (phte_real[base + i].vsid == vsid) |
|
| - | 337 | && (phte_real[base + i].api == api) |
|
| - | 338 | && (phte_real[base + i].h == 0)) { |
|
| 355 | return true; |
339 | found = true; |
| - | 340 | break; |
|
| - | 341 | } |
|
| 356 | } |
342 | } |
| 357 | 343 | ||
| - | 344 | if (!found) { |
|
| - | 345 | /* Find unused PTE in PTEG */ |
|
| - | 346 | for (i = 0; i < 8; i++) { |
|
| - | 347 | if (!phte_real[base + i].v) { |
|
| - | 348 | found = true; |
|
| - | 349 | break; |
|
| - | 350 | } |
|
| - | 351 | } |
|
| - | 352 | } |
|
| - | 353 | ||
| - | 354 | if (!found) { |
|
| - | 355 | /* Secondary hash (not) */ |
|
| - | 356 | uint32_t base2 = (~hash & 0x3ff) << 3; |
|
| - | 357 | ||
| - | 358 | /* Find colliding PTE in PTEG */ |
|
| - | 359 | for (i = 0; i < 8; i++) { |
|
| - | 360 | if ((phte_real[base2 + i].v) |
|
| - | 361 | && (phte_real[base2 + i].vsid == vsid) |
|
| - | 362 | && (phte_real[base2 + i].api == api) |
|
| - | 363 | && (phte_real[base2 + i].h == 1)) { |
|
| - | 364 | found = true; |
|
| - | 365 | base = base2; |
|
| - | 366 | h = 1; |
|
| - | 367 | break; |
|
| - | 368 | } |
|
| - | 369 | } |
|
| - | 370 | ||
| - | 371 | if (!found) { |
|
| - | 372 | /* Find unused PTE in PTEG */ |
|
| - | 373 | for (i = 0; i < 8; i++) { |
|
| - | 374 | if (!phte_real[base2 + i].v) { |
|
| - | 375 | found = true; |
|
| - | 376 | base = base2; |
|
| - | 377 | h = 1; |
|
| - | 378 | break; |
|
| - | 379 | } |
|
| - | 380 | } |
|
| - | 381 | } |
|
| - | 382 | ||
| - | 383 | if (!found) { |
|
| - | 384 | /* Use secondary hash to avoid collisions |
|
| - | 385 | with usual PHT refill handler. */ |
|
| - | 386 | i = RANDI(seed_real) % 8; |
|
| - | 387 | base = base2; |
|
| - | 388 | h = 1; |
|
| - | 389 | } |
|
| - | 390 | } |
|
| - | 391 | ||
| - | 392 | phte_real[base + i].v = 1; |
|
| - | 393 | phte_real[base + i].vsid = vsid; |
|
| - | 394 | phte_real[base + i].h = h; |
|
| - | 395 | phte_real[base + i].api = api; |
|
| - | 396 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
|
| - | 397 | phte_real[base + i].r = 0; |
|
| - | 398 | phte_real[base + i].c = 0; |
|
| - | 399 | phte_real[base + i].wimg = 0; |
|
| - | 400 | phte_real[base + i].pp = 2; // FIXME |
|
| - | 401 | ||
| 358 | return false; |
402 | return true; |
| - | 403 | } |
|
| - | 404 | ||
| - | 405 | ||
| - | 406 | /** Process ITLB/DTLB Miss Exception in Real Mode |
|
| - | 407 | * |
|
| - | 408 | * |
|
| - | 409 | */ |
|
| - | 410 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
|
| - | 411 | { |
|
| - | 412 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
|
| - | 413 | ||
| - | 414 | uint32_t physmem; |
|
| - | 415 | asm volatile ( |
|
| - | 416 | "mfsprg3 %0\n" |
|
| - | 417 | : "=r" (physmem) |
|
| - | 418 | ); |
|
| - | 419 | ||
| - | 420 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
|
| - | 421 | return; // FIXME |
|
| - | 422 | ||
| - | 423 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
|
| - | 424 | ptelo.wimg = 0; |
|
| - | 425 | ptelo.pp = 2; // FIXME |
|
| - | 426 | ||
| - | 427 | uint32_t index = 0; |
|
| - | 428 | asm volatile ( |
|
| - | 429 | "mtspr 981, %0\n" |
|
| - | 430 | "mtspr 982, %1\n" |
|
| - | 431 | "tlbld %2\n" |
|
| - | 432 | "tlbli %2\n" |
|
| - | 433 | : "=r" (index) |
|
| - | 434 | : "r" (ptehi), |
|
| - | 435 | "r" (ptelo) |
|
| - | 436 | ); |
|
| 359 | } |
437 | } |
| 360 | 438 | ||
| 361 | 439 | ||
| 362 | void tlb_arch_init(void) |
440 | void tlb_arch_init(void) |
| 363 | { |
441 | { |
| 364 | tlb_invalidate_all(); |
442 | tlb_invalidate_all(); |
| 365 | } |
443 | } |
| 366 | 444 | ||
| 367 | 445 | ||
| 368 | void tlb_invalidate_all(void) |
446 | void tlb_invalidate_all(void) |
| 369 | { |
447 | { |
| - | 448 | uint32_t index; |
|
| 370 | asm volatile ( |
449 | asm volatile ( |
| - | 450 | "li %0, 0\n" |
|
| - | 451 | "sync\n" |
|
| - | 452 | ||
| - | 453 | TLB_FLUSH |
|
| - | 454 | TLB_FLUSH |
|
| - | 455 | TLB_FLUSH |
|
| - | 456 | TLB_FLUSH |
|
| - | 457 | TLB_FLUSH |
|
| - | 458 | TLB_FLUSH |
|
| - | 459 | TLB_FLUSH |
|
| - | 460 | TLB_FLUSH |
|
| - | 461 | ||
| - | 462 | TLB_FLUSH |
|
| - | 463 | TLB_FLUSH |
|
| - | 464 | TLB_FLUSH |
|
| - | 465 | TLB_FLUSH |
|
| - | 466 | TLB_FLUSH |
|
| - | 467 | TLB_FLUSH |
|
| - | 468 | TLB_FLUSH |
|
| - | 469 | TLB_FLUSH |
|
| - | 470 | ||
| - | 471 | TLB_FLUSH |
|
| - | 472 | TLB_FLUSH |
|
| - | 473 | TLB_FLUSH |
|
| - | 474 | TLB_FLUSH |
|
| - | 475 | TLB_FLUSH |
|
| - | 476 | TLB_FLUSH |
|
| - | 477 | TLB_FLUSH |
|
| - | 478 | TLB_FLUSH |
|
| - | 479 | ||
| - | 480 | TLB_FLUSH |
|
| - | 481 | TLB_FLUSH |
|
| - | 482 | TLB_FLUSH |
|
| - | 483 | TLB_FLUSH |
|
| - | 484 | TLB_FLUSH |
|
| - | 485 | TLB_FLUSH |
|
| - | 486 | TLB_FLUSH |
|
| - | 487 | TLB_FLUSH |
|
| - | 488 | ||
| - | 489 | TLB_FLUSH |
|
| - | 490 | TLB_FLUSH |
|
| - | 491 | TLB_FLUSH |
|
| - | 492 | TLB_FLUSH |
|
| - | 493 | TLB_FLUSH |
|
| - | 494 | TLB_FLUSH |
|
| - | 495 | TLB_FLUSH |
|
| - | 496 | TLB_FLUSH |
|
| - | 497 | ||
| - | 498 | TLB_FLUSH |
|
| - | 499 | TLB_FLUSH |
|
| - | 500 | TLB_FLUSH |
|
| - | 501 | TLB_FLUSH |
|
| - | 502 | TLB_FLUSH |
|
| - | 503 | TLB_FLUSH |
|
| - | 504 | TLB_FLUSH |
|
| - | 505 | TLB_FLUSH |
|
| - | 506 | ||
| - | 507 | TLB_FLUSH |
|
| - | 508 | TLB_FLUSH |
|
| - | 509 | TLB_FLUSH |
|
| - | 510 | TLB_FLUSH |
|
| - | 511 | TLB_FLUSH |
|
| - | 512 | TLB_FLUSH |
|
| - | 513 | TLB_FLUSH |
|
| - | 514 | TLB_FLUSH |
|
| - | 515 | ||
| - | 516 | TLB_FLUSH |
|
| - | 517 | TLB_FLUSH |
|
| - | 518 | TLB_FLUSH |
|
| - | 519 | TLB_FLUSH |
|
| - | 520 | TLB_FLUSH |
|
| - | 521 | TLB_FLUSH |
|
| - | 522 | TLB_FLUSH |
|
| - | 523 | TLB_FLUSH |
|
| - | 524 | ||
| 371 | "tlbia\n" |
525 | "eieio\n" |
| 372 | "tlbsync\n" |
526 | "tlbsync\n" |
| - | 527 | "sync\n" |
|
| - | 528 | : "=r" (index) |
|
| 373 | ); |
529 | ); |
| 374 | } |
530 | } |
| 375 | 531 | ||
| 376 | 532 | ||
| 377 | void tlb_invalidate_asid(asid_t asid) |
533 | void tlb_invalidate_asid(asid_t asid) |
| 378 | { |
534 | { |
| 379 | uint32_t sdr1; |
535 | uint32_t sdr1; |
| 380 | asm volatile ( |
536 | asm volatile ( |
| 381 | "mfsdr1 %0\n" |
537 | "mfsdr1 %0\n" |
| 382 | : "=r" (sdr1) |
538 | : "=r" (sdr1) |
| 383 | ); |
539 | ); |
| 384 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
540 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
| 385 | 541 | ||
| 386 | uint32_t i; |
542 | uint32_t i; |
| 387 | for (i = 0; i < 8192; i++) { |
543 | for (i = 0; i < 8192; i++) { |
| 388 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
544 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
| 389 | (phte[i].vsid < ((asid << 4) + 16))) |
545 | (phte[i].vsid < ((asid << 4) + 16))) |
| 390 | phte[i].v = 0; |
546 | phte[i].v = 0; |
| 391 | } |
547 | } |
| 392 | tlb_invalidate_all(); |
548 | tlb_invalidate_all(); |
| 393 | } |
549 | } |
| 394 | 550 | ||
| 395 | 551 | ||
| 396 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
552 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
| 397 | { |
553 | { |
| 398 | // TODO |
554 | // TODO |
| 399 | tlb_invalidate_all(); |
555 | tlb_invalidate_all(); |
| 400 | } |
556 | } |
| 401 | 557 | ||
| 402 | 558 | ||
| 403 | #define PRINT_BAT(name, ureg, lreg) \ |
559 | #define PRINT_BAT(name, ureg, lreg) \ |
| 404 | asm volatile ( \ |
560 | asm volatile ( \ |
| 405 | "mfspr %0," #ureg "\n" \ |
561 | "mfspr %0," #ureg "\n" \ |
| 406 | "mfspr %1," #lreg "\n" \ |
562 | "mfspr %1," #lreg "\n" \ |
| 407 | : "=r" (upper), "=r" (lower) \ |
563 | : "=r" (upper), "=r" (lower) \ |
| 408 | ); \ |
564 | ); \ |
| 409 | mask = (upper & 0x1ffc) >> 2; \ |
565 | mask = (upper & 0x1ffc) >> 2; \ |
| 410 | if (upper & 3) { \ |
566 | if (upper & 3) { \ |
| 411 | uint32_t tmp = mask; \ |
567 | uint32_t tmp = mask; \ |
| 412 | length = 128; \ |
568 | length = 128; \ |
| 413 | while (tmp) { \ |
569 | while (tmp) { \ |
| 414 | if ((tmp & 1) == 0) { \ |
570 | if ((tmp & 1) == 0) { \ |
| 415 | printf("ibat[0]: error in mask\n"); \ |
571 | printf("ibat[0]: error in mask\n"); \ |
| 416 | break; \ |
572 | break; \ |
| 417 | } \ |
573 | } \ |
| 418 | length <<= 1; \ |
574 | length <<= 1; \ |
| 419 | tmp >>= 1; \ |
575 | tmp >>= 1; \ |
| 420 | } \ |
576 | } \ |
| 421 | } else \ |
577 | } else \ |
| 422 | length = 0; \ |
578 | length = 0; \ |
| 423 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
579 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
| 424 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
580 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
| 425 | lower & 0xffff0000, length, mask, \ |
581 | lower & 0xffff0000, length, mask, \ |
| 426 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
582 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
| 427 | (upper & 1) ? " user" : ""); |
583 | (upper & 1) ? " user" : ""); |
| 428 | 584 | ||
| 429 | 585 | ||
| 430 | void tlb_print(void) |
586 | void tlb_print(void) |
| 431 | { |
587 | { |
| 432 | uint32_t sr; |
588 | uint32_t sr; |
| 433 | 589 | ||
| 434 | for (sr = 0; sr < 16; sr++) { |
590 | for (sr = 0; sr < 16; sr++) { |
| 435 | uint32_t vsid; |
591 | uint32_t vsid; |
| 436 | asm volatile ( |
592 | asm volatile ( |
| 437 | "mfsrin %0, %1\n" |
593 | "mfsrin %0, %1\n" |
| 438 | : "=r" (vsid) |
594 | : "=r" (vsid) |
| 439 | : "r" (sr << 28) |
595 | : "r" (sr << 28) |
| 440 | ); |
596 | ); |
| 441 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, |
597 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
| 442 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
598 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
| 443 | ((vsid >> 30) & 1) ? " supervisor" : "", |
599 | ((vsid >> 30) & 1) ? " supervisor" : "", |
| 444 | ((vsid >> 29) & 1) ? " user" : ""); |
600 | ((vsid >> 29) & 1) ? " user" : ""); |
| 445 | } |
601 | } |
| 446 | 602 | ||
| 447 | uint32_t upper; |
603 | uint32_t upper; |
| 448 | uint32_t lower; |
604 | uint32_t lower; |
| 449 | uint32_t mask; |
605 | uint32_t mask; |
| 450 | uint32_t length; |
606 | uint32_t length; |
| 451 | 607 | ||
| 452 | PRINT_BAT("ibat[0]", 528, 529); |
608 | PRINT_BAT("ibat[0]", 528, 529); |
| 453 | PRINT_BAT("ibat[1]", 530, 531); |
609 | PRINT_BAT("ibat[1]", 530, 531); |
| 454 | PRINT_BAT("ibat[2]", 532, 533); |
610 | PRINT_BAT("ibat[2]", 532, 533); |
| 455 | PRINT_BAT("ibat[3]", 534, 535); |
611 | PRINT_BAT("ibat[3]", 534, 535); |
| 456 | 612 | ||
| 457 | PRINT_BAT("dbat[0]", 536, 537); |
613 | PRINT_BAT("dbat[0]", 536, 537); |
| 458 | PRINT_BAT("dbat[1]", 538, 539); |
614 | PRINT_BAT("dbat[1]", 538, 539); |
| 459 | PRINT_BAT("dbat[2]", 540, 541); |
615 | PRINT_BAT("dbat[2]", 540, 541); |
| 460 | PRINT_BAT("dbat[3]", 542, 543); |
616 | PRINT_BAT("dbat[3]", 542, 543); |
| 461 | } |
617 | } |
| 462 | 618 | ||
| 463 | /** @} |
619 | /** @} |
| 464 | */ |
620 | */ |
| 465 | 621 | ||