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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch.h> |
29 | #include <arch.h> |
30 | #include <arch/cp0.h> |
30 | #include <arch/cp0.h> |
31 | #include <arch/exception.h> |
31 | #include <arch/exception.h> |
32 | #include <arch/asm/regname.h> |
32 | #include <arch/asm/regname.h> |
33 | #include <arch/asm.h> |
33 | #include <arch/asm.h> |
34 | #include <mm/vm.h> |
34 | #include <mm/vm.h> |
35 | #include <userspace.h> |
35 | #include <userspace.h> |
36 | #include <arch/console.h> |
36 | #include <arch/console.h> |
37 | #include <memstr.h> |
37 | #include <memstr.h> |
38 | #include <arch/interrupt.h> |
38 | #include <arch/interrupt.h> |
- | 39 | #include <arch/drivers/arc.h> |
|
39 | 40 | ||
40 | #include <print.h> |
41 | #include <print.h> |
41 | 42 | ||
42 | /* Size of the code jumping to the exception handler code |
43 | /* Size of the code jumping to the exception handler code |
43 | * - J+NOP |
44 | * - J+NOP |
44 | */ |
45 | */ |
45 | #define EXCEPTION_JUMP_SIZE 8 |
46 | #define EXCEPTION_JUMP_SIZE 8 |
46 | 47 | ||
47 | #define TLB_EXC ((char *) 0x80000000) |
48 | #define TLB_EXC ((char *) 0x80000000) |
48 | #define NORM_EXC ((char *) 0x80000180) |
49 | #define NORM_EXC ((char *) 0x80000180) |
49 | #define CACHE_EXC ((char *) 0x80000100) |
50 | #define CACHE_EXC ((char *) 0x80000100) |
50 | 51 | ||
51 | void arch_pre_mm_init(void) |
52 | void arch_pre_mm_init(void) |
52 | { |
53 | { |
53 | /* It is not assumed by default */ |
54 | /* It is not assumed by default */ |
54 | cpu_priority_high(); |
55 | cpu_priority_high(); |
55 | 56 | ||
- | 57 | init_arc(); |
|
- | 58 | ||
56 | /* Copy the exception vectors to the right places */ |
59 | /* Copy the exception vectors to the right places */ |
57 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
60 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
58 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
61 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
59 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
62 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
60 | 63 | ||
61 | /* |
64 | /* |
62 | * Switch to BEV normal level so that exception vectors point to the kernel. |
65 | * Switch to BEV normal level so that exception vectors point to the kernel. |
63 | * Clear the error level. |
66 | * Clear the error level. |
64 | */ |
67 | */ |
65 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
68 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
66 | 69 | ||
67 | /* |
70 | /* |
68 | * Mask all interrupts |
71 | * Mask all interrupts |
69 | */ |
72 | */ |
70 | cp0_mask_all_int(); |
73 | cp0_mask_all_int(); |
71 | /* |
74 | /* |
72 | * Unmask hardware clock interrupt. |
75 | * Unmask hardware clock interrupt. |
73 | */ |
76 | */ |
74 | cp0_unmask_int(TIMER_INTERRUPT); |
77 | cp0_unmask_int(TIMER_INTERRUPT); |
75 | 78 | ||
76 | /* |
79 | /* |
77 | * Start hardware clock. |
80 | * Start hardware clock. |
78 | */ |
81 | */ |
79 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
82 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
80 | 83 | ||
81 | console_init(); |
84 | console_init(); |
- | 85 | arc_print_memory_map(); |
|
82 | } |
86 | } |
83 | 87 | ||
84 | void arch_post_mm_init(void) |
88 | void arch_post_mm_init(void) |
85 | { |
89 | { |
86 | } |
90 | } |
87 | 91 | ||
88 | void arch_late_init(void) |
92 | void arch_late_init(void) |
89 | { |
93 | { |
90 | } |
94 | } |
91 | 95 | ||
92 | void userspace(void) |
96 | void userspace(void) |
93 | { |
97 | { |
94 | /* EXL=1, UM=1, IE=1 */ |
98 | /* EXL=1, UM=1, IE=1 */ |
95 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
99 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
96 | cp0_status_um_bit | |
100 | cp0_status_um_bit | |
97 | cp0_status_ie_enabled_bit)); |
101 | cp0_status_ie_enabled_bit)); |
98 | 102 | ||
99 | cp0_epc_write(UTEXT_ADDRESS); |
103 | cp0_epc_write(UTEXT_ADDRESS); |
100 | userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
104 | userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
101 | while (1) |
105 | while (1) |
102 | ; |
106 | ; |
103 | } |
107 | } |
104 | 108 | ||
105 | /* Stack pointer saved when entering user mode */ |
109 | /* Stack pointer saved when entering user mode */ |
106 | /* TODO: How do we do it on SMP system???? */ |
110 | /* TODO: How do we do it on SMP system???? */ |
107 | __address supervisor_sp; |
111 | __address supervisor_sp; |
108 | 112 | ||
109 | void before_thread_runs_arch(void) |
113 | void before_thread_runs_arch(void) |
110 | { |
114 | { |
111 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
115 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
112 | } |
116 | } |
113 | - | ||
114 | - | ||
115 | 117 |