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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | 29 | ||
30 | #include <arch.h> |
30 | #include <arch.h> |
31 | #include <arch/cp0.h> |
31 | #include <arch/cp0.h> |
32 | #include <arch/exception.h> |
32 | #include <arch/exception.h> |
33 | #include <arch/asm.h> |
33 | #include <arch/asm.h> |
34 | #include <mm/as.h> |
34 | #include <mm/as.h> |
35 | 35 | ||
36 | #include <userspace.h> |
36 | #include <userspace.h> |
37 | #include <arch/console.h> |
37 | #include <arch/console.h> |
38 | #include <memstr.h> |
38 | #include <memstr.h> |
39 | #include <proc/thread.h> |
39 | #include <proc/thread.h> |
40 | #include <proc/uarg.h> |
40 | #include <proc/uarg.h> |
41 | #include <print.h> |
41 | #include <print.h> |
- | 42 | #include <syscall/syscall.h> |
|
42 | 43 | ||
43 | #include <arch/interrupt.h> |
44 | #include <arch/interrupt.h> |
44 | #include <arch/drivers/arc.h> |
45 | #include <arch/drivers/arc.h> |
45 | #include <console/chardev.h> |
46 | #include <console/chardev.h> |
46 | #include <arch/debugger.h> |
47 | #include <arch/debugger.h> |
47 | 48 | ||
48 | #include <arch/asm/regname.h> |
49 | #include <arch/asm/regname.h> |
49 | 50 | ||
50 | /* Size of the code jumping to the exception handler code |
51 | /* Size of the code jumping to the exception handler code |
51 | * - J+NOP |
52 | * - J+NOP |
52 | */ |
53 | */ |
53 | #define EXCEPTION_JUMP_SIZE 8 |
54 | #define EXCEPTION_JUMP_SIZE 8 |
54 | 55 | ||
55 | #define TLB_EXC ((char *) 0x80000000) |
56 | #define TLB_EXC ((char *) 0x80000000) |
56 | #define NORM_EXC ((char *) 0x80000180) |
57 | #define NORM_EXC ((char *) 0x80000180) |
57 | #define CACHE_EXC ((char *) 0x80000100) |
58 | #define CACHE_EXC ((char *) 0x80000100) |
58 | 59 | ||
59 | void arch_pre_mm_init(void) |
60 | void arch_pre_mm_init(void) |
60 | { |
61 | { |
61 | /* It is not assumed by default */ |
62 | /* It is not assumed by default */ |
62 | interrupts_disable(); |
63 | interrupts_disable(); |
63 | 64 | ||
64 | /* Initialize dispatch table */ |
65 | /* Initialize dispatch table */ |
65 | exception_init(); |
66 | exception_init(); |
66 | interrupt_init(); |
67 | interrupt_init(); |
67 | 68 | ||
68 | arc_init(); |
69 | arc_init(); |
69 | 70 | ||
70 | /* Copy the exception vectors to the right places */ |
71 | /* Copy the exception vectors to the right places */ |
71 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
72 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
72 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
73 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
73 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
74 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
74 | 75 | ||
75 | /* |
76 | /* |
76 | * Switch to BEV normal level so that exception vectors point to the kernel. |
77 | * Switch to BEV normal level so that exception vectors point to the kernel. |
77 | * Clear the error level. |
78 | * Clear the error level. |
78 | */ |
79 | */ |
79 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
80 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
80 | 81 | ||
81 | /* |
82 | /* |
82 | * Mask all interrupts |
83 | * Mask all interrupts |
83 | */ |
84 | */ |
84 | cp0_mask_all_int(); |
85 | cp0_mask_all_int(); |
85 | /* |
86 | /* |
86 | * Unmask hardware clock interrupt. |
87 | * Unmask hardware clock interrupt. |
87 | */ |
88 | */ |
88 | cp0_unmask_int(TIMER_IRQ); |
89 | cp0_unmask_int(TIMER_IRQ); |
89 | 90 | ||
90 | /* |
91 | /* |
91 | * Start hardware clock. |
92 | * Start hardware clock. |
92 | */ |
93 | */ |
93 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
94 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
94 | 95 | ||
95 | console_init(); |
96 | console_init(); |
96 | debugger_init(); |
97 | debugger_init(); |
97 | 98 | ||
98 | /* Setup usermode */ |
99 | /* Setup usermode */ |
99 | init.cnt = 1; |
100 | init.cnt = 1; |
100 | init.tasks[0].addr = INIT_ADDRESS; |
101 | init.tasks[0].addr = INIT_ADDRESS; |
101 | init.tasks[0].size = INIT_SIZE; |
102 | init.tasks[0].size = INIT_SIZE; |
102 | } |
103 | } |
103 | 104 | ||
104 | void arch_post_mm_init(void) |
105 | void arch_post_mm_init(void) |
105 | { |
106 | { |
106 | } |
107 | } |
107 | 108 | ||
108 | void arch_pre_smp_init(void) |
109 | void arch_pre_smp_init(void) |
109 | { |
110 | { |
110 | } |
111 | } |
111 | 112 | ||
112 | void arch_post_smp_init(void) |
113 | void arch_post_smp_init(void) |
113 | { |
114 | { |
114 | } |
115 | } |
115 | 116 | ||
116 | /* Stack pointer saved when entering user mode */ |
117 | /* Stack pointer saved when entering user mode */ |
117 | /* TODO: How do we do it on SMP system???? */ |
118 | /* TODO: How do we do it on SMP system???? */ |
118 | 119 | ||
119 | /* Why the linker moves the variable 64K away in assembler |
120 | /* Why the linker moves the variable 64K away in assembler |
120 | * when not in .text section ???????? |
121 | * when not in .text section ???????? |
121 | */ |
122 | */ |
122 | __address supervisor_sp __attribute__ ((section (".text"))); |
123 | __address supervisor_sp __attribute__ ((section (".text"))); |
123 | 124 | ||
124 | void userspace(uspace_arg_t *kernel_uarg) |
125 | void userspace(uspace_arg_t *kernel_uarg) |
125 | { |
126 | { |
126 | /* EXL=1, UM=1, IE=1 */ |
127 | /* EXL=1, UM=1, IE=1 */ |
127 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
128 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
128 | cp0_status_um_bit | |
129 | cp0_status_um_bit | |
129 | cp0_status_ie_enabled_bit)); |
130 | cp0_status_ie_enabled_bit)); |
130 | cp0_epc_write((__address) kernel_uarg->uspace_entry); |
131 | cp0_epc_write((__address) kernel_uarg->uspace_entry); |
131 | userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), (__address) kernel_uarg->uspace_uarg); |
132 | userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), (__address) kernel_uarg->uspace_uarg); |
132 | while (1) |
133 | while (1) |
133 | ; |
134 | ; |
134 | } |
135 | } |
135 | 136 | ||
136 | void before_thread_runs_arch(void) |
137 | void before_thread_runs_arch(void) |
137 | { |
138 | { |
138 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
139 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
139 | } |
140 | } |
140 | 141 | ||
141 | void after_thread_ran_arch(void) |
142 | void after_thread_ran_arch(void) |
142 | { |
143 | { |
143 | } |
144 | } |
- | 145 | ||
- | 146 | /** Set Thread-local-storeage pointer |
|
- | 147 | * |
|
- | 148 | * We have it currently in K1, it is |
|
- | 149 | * possible to have it separately in the future. |
|
- | 150 | */ |
|
- | 151 | __native sys_tls_set(__native addr) |
|
- | 152 | { |
|
- | 153 | return 0; |
|
- | 154 | } |
|
144 | 155 |