WebSVN – HelenOS – Diff – /branches/network/kernel/arch/mips32/src/interrupt.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32interrupt
 * @{
 */
/** @file
 */
 
#include <interrupt.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <arch/cp0.h>
#include <time/clock.h>
#include <arch/drivers/arc.h>
#include <ipc/sysipc.h>
#include <ddi/device.h>
#include <ddi/irq.h>
 
#define IRQ_COUNT 8
#define TIMER_IRQ 7
 
function virtual_timer_fnc = NULL;
static irq_t timer_irq;
 
/** Disable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_disable(void)
{
    ipl_t ipl = (ipl_t) cp0_status_read();
    cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
    return ipl;
}
 
/** Enable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_enable(void)
{
    ipl_t ipl = (ipl_t) cp0_status_read();
    cp0_status_write(ipl | cp0_status_ie_enabled_bit);
    return ipl;
}
 
/** Restore interrupt priority level.
 *
 * @param ipl Saved interrupt priority level.
 */
void interrupts_restore(ipl_t ipl)
{
    cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
}
 
/** Read interrupt priority level.
 *
 * @return Current interrupt priority level.
 */
ipl_t interrupts_read(void)
{
    return cp0_status_read();
}
 
/* TODO: This is SMP unsafe!!! */
static unsigned long nextcount;
/** Start hardware clock */
static void timer_start(void)
{
    nextcount = cp0_compare_value + cp0_count_read();
    cp0_compare_write(nextcount);
}
 
static irq_ownership_t timer_claim(void)
{
    return IRQ_ACCEPT;
}
 
static void timer_irq_handler(irq_t *irq, void *arg, ...)
{
    unsigned long drift;
 
    drift = cp0_count_read() - nextcount;
    while (drift > cp0_compare_value) {
        drift -= cp0_compare_value;
        CPU->missed_clock_ticks++;
    }
    nextcount = cp0_count_read() + cp0_compare_value - drift;
    cp0_compare_write(nextcount);
    clock();
   
    if (virtual_timer_fnc != NULL)
        virtual_timer_fnc();
}
 
/* Initialize basic tables for exception dispatching */
void interrupt_init(void)
{
    irq_init(IRQ_COUNT, IRQ_COUNT);
   
    irq_initialize(&timer_irq);
    timer_irq.devno = device_assign_devno();
    timer_irq.inr = TIMER_IRQ;
    timer_irq.claim = timer_claim;
    timer_irq.handler = timer_irq_handler;
    irq_register(&timer_irq);
   
    timer_start();
    cp0_unmask_int(TIMER_IRQ);
}
 
/** @}
 */
 

Rev 1955	Rev 2071
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32interrupt	29	/** @addtogroup mips32interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <interrupt.h>	35	#include <interrupt.h>
36	#include <arch/interrupt.h>	36	#include <arch/interrupt.h>
37	#include <arch/types.h>	37	#include <arch/types.h>
38	#include <arch.h>	38	#include <arch.h>
39	#include <arch/cp0.h>	39	#include <arch/cp0.h>
40	#include <time/clock.h>	40	#include <time/clock.h>
41	#include <arch/drivers/arc.h>	41	#include <arch/drivers/arc.h>
42	#include <ipc/sysipc.h>	42	#include <ipc/sysipc.h>
43	#include <ddi/device.h>	43	#include <ddi/device.h>
44	#include <ddi/irq.h>	44	#include <ddi/irq.h>
45		45
46	#define IRQ_COUNT 8	46	#define IRQ_COUNT 8
47	#define TIMER_IRQ 7	47	#define TIMER_IRQ 7
48		48
49	function virtual_timer_fnc = NULL;	49	function virtual_timer_fnc = NULL;
50	static irq_t timer_irq;	50	static irq_t timer_irq;
51		51
52	/** Disable interrupts.	52	/** Disable interrupts.
53	*	53	*
54	* @return Old interrupt priority level.	54	* @return Old interrupt priority level.
55	*/	55	*/
56	ipl_t interrupts_disable(void)	56	ipl_t interrupts_disable(void)
57	{	57	{
58	ipl_t ipl = (ipl_t) cp0_status_read();	58	ipl_t ipl = (ipl_t) cp0_status_read();
59	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);	59	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
60	return ipl;	60	return ipl;
61	}	61	}
62		62
63	/** Enable interrupts.	63	/** Enable interrupts.
64	*	64	*
65	* @return Old interrupt priority level.	65	* @return Old interrupt priority level.
66	*/	66	*/
67	ipl_t interrupts_enable(void)	67	ipl_t interrupts_enable(void)
68	{	68	{
69	ipl_t ipl = (ipl_t) cp0_status_read();	69	ipl_t ipl = (ipl_t) cp0_status_read();
70	cp0_status_write(ipl \| cp0_status_ie_enabled_bit);	70	cp0_status_write(ipl \| cp0_status_ie_enabled_bit);
71	return ipl;	71	return ipl;
72	}	72	}
73		73
74	/** Restore interrupt priority level.	74	/** Restore interrupt priority level.
75	*	75	*
76	* @param ipl Saved interrupt priority level.	76	* @param ipl Saved interrupt priority level.
77	*/	77	*/
78	void interrupts_restore(ipl_t ipl)	78	void interrupts_restore(ipl_t ipl)
79	{	79	{
80	cp0_status_write(cp0_status_read() \| (ipl & cp0_status_ie_enabled_bit));	80	cp0_status_write(cp0_status_read() \| (ipl & cp0_status_ie_enabled_bit));
81	}	81	}
82		82
83	/** Read interrupt priority level.	83	/** Read interrupt priority level.
84	*	84	*
85	* @return Current interrupt priority level.	85	* @return Current interrupt priority level.
86	*/	86	*/
87	ipl_t interrupts_read(void)	87	ipl_t interrupts_read(void)
88	{	88	{
89	return cp0_status_read();	89	return cp0_status_read();
90	}	90	}
91		91
92	/* TODO: This is SMP unsafe!!! */	92	/* TODO: This is SMP unsafe!!! */
93	static unsigned long nextcount;	93	static unsigned long nextcount;
94	/** Start hardware clock */	94	/** Start hardware clock */
95	static void timer_start(void)	95	static void timer_start(void)
96	{	96	{
97	nextcount = cp0_compare_value + cp0_count_read();	97	nextcount = cp0_compare_value + cp0_count_read();
98	cp0_compare_write(nextcount);	98	cp0_compare_write(nextcount);
99	}	99	}
100		100
101	static irq_ownership_t timer_claim(void)	101	static irq_ownership_t timer_claim(void)
102	{	102	{
103	return IRQ_ACCEPT;	103	return IRQ_ACCEPT;
104	}	104	}
105		105
106	static void timer_irq_handler(irq_t irq, void arg, ...)	106	static void timer_irq_handler(irq_t irq, void arg, ...)
107	{	107	{
108	unsigned long drift;	108	unsigned long drift;
109		109
110	drift = cp0_count_read() - nextcount;	110	drift = cp0_count_read() - nextcount;
111	while (drift > cp0_compare_value) {	111	while (drift > cp0_compare_value) {
112	drift -= cp0_compare_value;	112	drift -= cp0_compare_value;
113	CPU->missed_clock_ticks++;	113	CPU->missed_clock_ticks++;
114	}	114	}
115	nextcount = cp0_count_read() + cp0_compare_value - drift;	115	nextcount = cp0_count_read() + cp0_compare_value - drift;
116	cp0_compare_write(nextcount);	116	cp0_compare_write(nextcount);
117	clock();	117	clock();
118		118
119	if (virtual_timer_fnc != NULL)	119	if (virtual_timer_fnc != NULL)
120	virtual_timer_fnc();	120	virtual_timer_fnc();
121	}	121	}
122		122
123	/* Initialize basic tables for exception dispatching */	123	/* Initialize basic tables for exception dispatching */
124	void interrupt_init(void)	124	void interrupt_init(void)
125	{	125	{
126	irq_init(IRQ_COUNT, IRQ_COUNT);	126	irq_init(IRQ_COUNT, IRQ_COUNT);
127		127
128	irq_initialize(&timer_irq);	128	irq_initialize(&timer_irq);
129	timer_irq.devno = device_assign_devno();	129	timer_irq.devno = device_assign_devno();
130	timer_irq.inr = TIMER_IRQ;	130	timer_irq.inr = TIMER_IRQ;
131	timer_irq.claim = timer_claim;	131	timer_irq.claim = timer_claim;
132	timer_irq.handler = timer_irq_handler;	132	timer_irq.handler = timer_irq_handler;
133	irq_register(&timer_irq);	133	irq_register(&timer_irq);
134		134
135	timer_start();	135	timer_start();
136	cp0_unmask_int(TIMER_IRQ);	136	cp0_unmask_int(TIMER_IRQ);
137	}	137	}
138		138
139	/** @}	139	/** @}
140	*/	140	*/
141		141

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(root)/branches/network/kernel/arch/mips32/src/interrupt.c @ 4744 – Rev 1955 → 2071