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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32interrupt |
29 | /** @addtogroup mips32interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <arch/interrupt.h> |
36 | #include <arch/interrupt.h> |
37 | #include <arch/types.h> |
37 | #include <arch/types.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | #include <arch/cp0.h> |
39 | #include <arch/cp0.h> |
40 | #include <time/clock.h> |
40 | #include <time/clock.h> |
41 | #include <arch/drivers/arc.h> |
41 | #include <arch/drivers/arc.h> |
42 | #include <ipc/sysipc.h> |
42 | #include <ipc/sysipc.h> |
43 | #include <ddi/device.h> |
43 | #include <ddi/device.h> |
44 | 44 | ||
45 | #define IRQ_COUNT 8 |
45 | #define IRQ_COUNT 8 |
46 | #define TIMER_IRQ 7 |
46 | #define TIMER_IRQ 7 |
47 | 47 | ||
48 | function virtual_timer_fnc = NULL; |
48 | function virtual_timer_fnc = NULL; |
49 | static irq_t timer_irq; |
49 | static irq_t timer_irq; |
50 | 50 | ||
51 | /** Disable interrupts. |
51 | /** Disable interrupts. |
52 | * |
52 | * |
53 | * @return Old interrupt priority level. |
53 | * @return Old interrupt priority level. |
54 | */ |
54 | */ |
55 | ipl_t interrupts_disable(void) |
55 | ipl_t interrupts_disable(void) |
56 | { |
56 | { |
57 | ipl_t ipl = (ipl_t) cp0_status_read(); |
57 | ipl_t ipl = (ipl_t) cp0_status_read(); |
58 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
58 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
59 | return ipl; |
59 | return ipl; |
60 | } |
60 | } |
61 | 61 | ||
62 | /** Enable interrupts. |
62 | /** Enable interrupts. |
63 | * |
63 | * |
64 | * @return Old interrupt priority level. |
64 | * @return Old interrupt priority level. |
65 | */ |
65 | */ |
66 | ipl_t interrupts_enable(void) |
66 | ipl_t interrupts_enable(void) |
67 | { |
67 | { |
68 | ipl_t ipl = (ipl_t) cp0_status_read(); |
68 | ipl_t ipl = (ipl_t) cp0_status_read(); |
69 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
69 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
70 | return ipl; |
70 | return ipl; |
71 | } |
71 | } |
72 | 72 | ||
73 | /** Restore interrupt priority level. |
73 | /** Restore interrupt priority level. |
74 | * |
74 | * |
75 | * @param ipl Saved interrupt priority level. |
75 | * @param ipl Saved interrupt priority level. |
76 | */ |
76 | */ |
77 | void interrupts_restore(ipl_t ipl) |
77 | void interrupts_restore(ipl_t ipl) |
78 | { |
78 | { |
79 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
79 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
80 | } |
80 | } |
81 | 81 | ||
82 | /** Read interrupt priority level. |
82 | /** Read interrupt priority level. |
83 | * |
83 | * |
84 | * @return Current interrupt priority level. |
84 | * @return Current interrupt priority level. |
85 | */ |
85 | */ |
86 | ipl_t interrupts_read(void) |
86 | ipl_t interrupts_read(void) |
87 | { |
87 | { |
88 | return cp0_status_read(); |
88 | return cp0_status_read(); |
89 | } |
89 | } |
90 | 90 | ||
91 | /* TODO: This is SMP unsafe!!! */ |
91 | /* TODO: This is SMP unsafe!!! */ |
- | 92 | uint32_t count_hi = 0; |
|
92 | static unsigned long nextcount; |
93 | static unsigned long nextcount; |
- | 94 | static unsigned long lastcount; |
|
- | 95 | ||
93 | /** Start hardware clock */ |
96 | /** Start hardware clock */ |
94 | static void timer_start(void) |
97 | static void timer_start(void) |
95 | { |
98 | { |
- | 99 | lastcount = cp0_count_read(); |
|
96 | nextcount = cp0_compare_value + cp0_count_read(); |
100 | nextcount = cp0_compare_value + cp0_count_read(); |
97 | cp0_compare_write(nextcount); |
101 | cp0_compare_write(nextcount); |
98 | } |
102 | } |
99 | 103 | ||
100 | static irq_ownership_t timer_claim(void) |
104 | static irq_ownership_t timer_claim(void) |
101 | { |
105 | { |
102 | return IRQ_ACCEPT; |
106 | return IRQ_ACCEPT; |
103 | } |
107 | } |
104 | 108 | ||
105 | static void timer_irq_handler(irq_t *irq, void *arg, ...) |
109 | static void timer_irq_handler(irq_t *irq, void *arg, ...) |
106 | { |
110 | { |
107 | unsigned long drift; |
111 | unsigned long drift; |
108 | 112 | ||
- | 113 | if (cp0_count_read() < lastcount) { |
|
- | 114 | /* Count overflow detection */ |
|
- | 115 | count_hi++; |
|
- | 116 | lastcount = cp0_count_read(); |
|
- | 117 | } |
|
- | 118 | ||
109 | drift = cp0_count_read() - nextcount; |
119 | drift = cp0_count_read() - nextcount; |
110 | while (drift > cp0_compare_value) { |
120 | while (drift > cp0_compare_value) { |
111 | drift -= cp0_compare_value; |
121 | drift -= cp0_compare_value; |
112 | CPU->missed_clock_ticks++; |
122 | CPU->missed_clock_ticks++; |
113 | } |
123 | } |
114 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
124 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
115 | cp0_compare_write(nextcount); |
125 | cp0_compare_write(nextcount); |
116 | 126 | ||
117 | /* |
127 | /* |
118 | * We are holding a lock which prevents preemption. |
128 | * We are holding a lock which prevents preemption. |
119 | * Release the lock, call clock() and reacquire the lock again. |
129 | * Release the lock, call clock() and reacquire the lock again. |
120 | */ |
130 | */ |
121 | spinlock_unlock(&irq->lock); |
131 | spinlock_unlock(&irq->lock); |
122 | clock(); |
132 | clock(); |
123 | spinlock_lock(&irq->lock); |
133 | spinlock_lock(&irq->lock); |
124 | 134 | ||
125 | if (virtual_timer_fnc != NULL) |
135 | if (virtual_timer_fnc != NULL) |
126 | virtual_timer_fnc(); |
136 | virtual_timer_fnc(); |
127 | } |
137 | } |
128 | 138 | ||
129 | /* Initialize basic tables for exception dispatching */ |
139 | /* Initialize basic tables for exception dispatching */ |
130 | void interrupt_init(void) |
140 | void interrupt_init(void) |
131 | { |
141 | { |
132 | irq_init(IRQ_COUNT, IRQ_COUNT); |
142 | irq_init(IRQ_COUNT, IRQ_COUNT); |
133 | 143 | ||
134 | irq_initialize(&timer_irq); |
144 | irq_initialize(&timer_irq); |
135 | timer_irq.devno = device_assign_devno(); |
145 | timer_irq.devno = device_assign_devno(); |
136 | timer_irq.inr = TIMER_IRQ; |
146 | timer_irq.inr = TIMER_IRQ; |
137 | timer_irq.claim = timer_claim; |
147 | timer_irq.claim = timer_claim; |
138 | timer_irq.handler = timer_irq_handler; |
148 | timer_irq.handler = timer_irq_handler; |
139 | irq_register(&timer_irq); |
149 | irq_register(&timer_irq); |
140 | 150 | ||
141 | timer_start(); |
151 | timer_start(); |
142 | cp0_unmask_int(TIMER_IRQ); |
152 | cp0_unmask_int(TIMER_IRQ); |
143 | } |
153 | } |
144 | 154 | ||
145 | /** @} |
155 | /** @} |
146 | */ |
156 | */ |
147 | 157 |