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1 | # |
1 | # |
2 | # Copyright (C) 2005 Jakub Vana |
2 | # Copyright (C) 2005 Jakub Vana |
3 | # Copyright (C) 2005 Jakub Jermar |
3 | # Copyright (C) 2005 Jakub Jermar |
4 | # All rights reserved. |
4 | # All rights reserved. |
5 | # |
5 | # |
6 | # Redistribution and use in source and binary forms, with or without |
6 | # Redistribution and use in source and binary forms, with or without |
7 | # modification, are permitted provided that the following conditions |
7 | # modification, are permitted provided that the following conditions |
8 | # are met: |
8 | # are met: |
9 | # |
9 | # |
10 | # - Redistributions of source code must retain the above copyright |
10 | # - Redistributions of source code must retain the above copyright |
11 | # notice, this list of conditions and the following disclaimer. |
11 | # notice, this list of conditions and the following disclaimer. |
12 | # - Redistributions in binary form must reproduce the above copyright |
12 | # - Redistributions in binary form must reproduce the above copyright |
13 | # notice, this list of conditions and the following disclaimer in the |
13 | # notice, this list of conditions and the following disclaimer in the |
14 | # documentation and/or other materials provided with the distribution. |
14 | # documentation and/or other materials provided with the distribution. |
15 | # - The name of the author may not be used to endorse or promote products |
15 | # - The name of the author may not be used to endorse or promote products |
16 | # derived from this software without specific prior written permission. |
16 | # derived from this software without specific prior written permission. |
17 | # |
17 | # |
18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | # |
28 | # |
29 | 29 | ||
30 | #include <arch/stack.h> |
30 | #include <arch/stack.h> |
31 | #include <arch/register.h> |
31 | #include <arch/register.h> |
32 | #include <arch/mm/page.h> |
32 | #include <arch/mm/page.h> |
33 | #include <align.h> |
33 | #include <align.h> |
34 | 34 | ||
- | 35 | ||
- | 36 | #define FRS_TO_SAVE 30 |
|
- | 37 | #define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
|
35 | #define STACK_ITEMS 19 |
38 | //#define STACK_ITEMS 19 |
- | 39 | /* 30*2 for FPU registers */ |
|
36 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
40 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
37 | 41 | ||
38 | #if (STACK_ITEMS % 2 == 0) |
42 | #if (STACK_ITEMS % 2 == 0) |
39 | # define STACK_FRAME_BIAS 8 |
43 | # define STACK_FRAME_BIAS 8 |
40 | #else |
44 | #else |
41 | # define STACK_FRAME_BIAS 16 |
45 | # define STACK_FRAME_BIAS 16 |
42 | #endif |
46 | #endif |
43 | 47 | ||
44 | /** Partitioning of bank 0 registers. */ |
48 | /** Partitioning of bank 0 registers. */ |
45 | #define R_OFFS r16 |
49 | #define R_OFFS r16 |
46 | #define R_HANDLER r17 |
50 | #define R_HANDLER r17 |
47 | #define R_RET r18 |
51 | #define R_RET r18 |
48 | #define R_TMP r19 |
52 | #define R_TMP r19 |
49 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */ |
53 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */ |
50 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */ |
54 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */ |
51 | 55 | ||
52 | /** Heavyweight interrupt handler |
56 | /** Heavyweight interrupt handler |
53 | * |
57 | * |
54 | * This macro roughly follows steps from 1 to 19 described in |
58 | * This macro roughly follows steps from 1 to 19 described in |
55 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
59 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
56 | * |
60 | * |
57 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
61 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
58 | * This goal is achieved by using procedure calls after RSE becomes operational. |
62 | * This goal is achieved by using procedure calls after RSE becomes operational. |
59 | * |
63 | * |
60 | * Some steps are skipped (enabling and disabling interrupts). |
64 | * Some steps are skipped (enabling and disabling interrupts). |
61 | * Some steps are not fully supported yet (e.g. dealing with floating-point |
65 | * Some steps are not fully supported yet (e.g. dealing with floating-point |
62 | * context). |
66 | * context). |
63 | * |
67 | * |
64 | * @param offs Offset from the beginning of IVT. |
68 | * @param offs Offset from the beginning of IVT. |
65 | * @param handler Interrupt handler address. |
69 | * @param handler Interrupt handler address. |
66 | */ |
70 | */ |
67 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler |
71 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler |
68 | .org ivt + \offs |
72 | .org ivt + \offs |
69 | mov R_OFFS = \offs |
73 | mov R_OFFS = \offs |
70 | movl R_HANDLER = \handler ;; |
74 | movl R_HANDLER = \handler ;; |
71 | br heavyweight_handler |
75 | br heavyweight_handler |
72 | .endm |
76 | .endm |
73 | 77 | ||
74 | .global heavyweight_handler |
78 | .global heavyweight_handler |
75 | heavyweight_handler: |
79 | heavyweight_handler: |
76 | /* 1. copy interrupt registers into bank 0 */ |
80 | /* 1. copy interrupt registers into bank 0 */ |
77 | 81 | ||
78 | /* |
82 | /* |
79 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
83 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
80 | */ |
84 | */ |
- | 85 | ||
- | 86 | /*Set up FPU as in interrupred*/ |
|
- | 87 | mov r24=psr |
|
- | 88 | mov r25=cr.ipsr |
|
- | 89 | mov r26=(PSR_DFH_MASK) |
|
- | 90 | mov r27=(~(PSR_DFH_MASK));; |
|
- | 91 | and r26=r25,r26 |
|
- | 92 | and r24=r24,r27;; |
|
- | 93 | or r24=r24,r26;; |
|
- | 94 | mov psr.l=r24;; |
|
- | 95 | srlz.i |
|
- | 96 | srlz.d;; |
|
- | 97 | ||
81 | mov r24 = cr.iip |
98 | mov r24 = cr.iip |
82 | mov r25 = cr.ipsr |
99 | mov r25 = cr.ipsr |
83 | mov r26 = cr.iipa |
100 | mov r26 = cr.iipa |
84 | mov r27 = cr.isr |
101 | mov r27 = cr.isr |
85 | mov r28 = cr.ifa |
102 | mov r28 = cr.ifa |
86 | 103 | ||
87 | /* 2. preserve predicate register into bank 0 */ |
104 | /* 2. preserve predicate register into bank 0 */ |
88 | mov r29 = pr ;; |
105 | mov r29 = pr ;; |
89 | 106 | ||
90 | /* 3. switch to kernel memory stack */ |
107 | /* 3. switch to kernel memory stack */ |
91 | mov r30 = cr.ipsr |
108 | mov r30 = cr.ipsr |
92 | shr.u r31 = r12, VRN_SHIFT ;; |
109 | shr.u r31 = r12, VRN_SHIFT ;; |
93 | 110 | ||
94 | shr.u r30 = r30, PSR_CPL_SHIFT ;; |
111 | shr.u r30 = r30, PSR_CPL_SHIFT ;; |
95 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;; |
112 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;; |
96 | 113 | ||
97 | /* |
114 | /* |
98 | * Set p3 to true if the interrupted context executed in kernel mode. |
115 | * Set p3 to true if the interrupted context executed in kernel mode. |
99 | * Set p4 to false if the interrupted context didn't execute in kernel mode. |
116 | * Set p4 to false if the interrupted context didn't execute in kernel mode. |
100 | */ |
117 | */ |
101 | cmp.eq p3, p4 = r30, r0 ;; |
118 | cmp.eq p3, p4 = r30, r0 ;; |
102 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */ |
119 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */ |
103 | 120 | ||
104 | /* |
121 | /* |
105 | * Set p3 to true if the stack register references kernel address space. |
122 | * Set p3 to true if the stack register references kernel address space. |
106 | * Set p4 to false if the stack register doesn't reference kernel address space. |
123 | * Set p4 to false if the stack register doesn't reference kernel address space. |
107 | */ |
124 | */ |
108 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; |
125 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; |
109 | 126 | ||
110 | /* |
127 | /* |
111 | * Now, p4 is true iff the stack needs to be switched to kernel stack. |
128 | * Now, p4 is true iff the stack needs to be switched to kernel stack. |
112 | */ |
129 | */ |
113 | mov r30 = r12 |
130 | mov r30 = r12 |
114 | (p4) mov r12 = R_KSTACK ;; |
131 | (p4) mov r12 = R_KSTACK ;; |
115 | 132 | ||
116 | add r31 = -STACK_FRAME_BIAS, r12 ;; |
133 | add r31 = -STACK_FRAME_BIAS, r12 ;; |
117 | add r12 = -STACK_FRAME_SIZE, r12 |
134 | add r12 = -STACK_FRAME_SIZE, r12 |
118 | 135 | ||
119 | /* 4. save registers in bank 0 into memory stack */ |
136 | /* 4. save registers in bank 0 into memory stack */ |
120 | 137 | ||
121 | /* |
138 | /* |
122 | * If this is break_instruction handler, |
139 | * If this is break_instruction handler, |
123 | * copy input parameters to stack. |
140 | * copy input parameters to stack. |
124 | */ |
141 | */ |
125 | mov R_TMP = 0x2c00 ;; |
142 | mov R_TMP = 0x2c00 ;; |
126 | cmp.eq p6,p5 = R_OFFS, R_TMP ;; |
143 | cmp.eq p6,p5 = R_OFFS, R_TMP ;; |
127 | 144 | ||
128 | /* |
145 | /* |
129 | * From now on, if this is break_instruction handler, p6 is true and p5 is false. |
146 | * From now on, if this is break_instruction handler, p6 is true and p5 is false. |
130 | * Otherwise p6 is false and p5 is true. |
147 | * Otherwise p6 is false and p5 is true. |
131 | * Note that p5 is a preserved predicate register and we make use of it. |
148 | * Note that p5 is a preserved predicate register and we make use of it. |
132 | */ |
149 | */ |
133 | 150 | ||
134 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */ |
151 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */ |
135 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */ |
152 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */ |
136 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */ |
153 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */ |
137 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */ |
154 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */ |
138 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */ |
155 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */ |
139 | (p5) add r31 = -40, r31 ;; |
156 | (p5) add r31 = -40, r31 ;; |
140 | 157 | ||
141 | st8 [r31] = r30, -8 ;; /* save old stack pointer */ |
158 | st8 [r31] = r30, -8 ;; /* save old stack pointer */ |
142 | 159 | ||
143 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
160 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
144 | 161 | ||
145 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
162 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
146 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
163 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
147 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
164 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
148 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
165 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
149 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
166 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
150 | 167 | ||
151 | /* 5. RSE switch from interrupted context */ |
168 | /* 5. RSE switch from interrupted context */ |
152 | mov r24 = ar.rsc |
169 | mov r24 = ar.rsc |
153 | mov r25 = ar.pfs |
170 | mov r25 = ar.pfs |
154 | cover |
171 | cover |
155 | mov r26 = cr.ifs |
172 | mov r26 = cr.ifs |
156 | 173 | ||
157 | st8 [r31] = r24, -8 ;; /* save ar.rsc */ |
174 | st8 [r31] = r24, -8 ;; /* save ar.rsc */ |
158 | st8 [r31] = r25, -8 ;; /* save ar.pfs */ |
175 | st8 [r31] = r25, -8 ;; /* save ar.pfs */ |
159 | st8 [r31] = r26, -8 /* save ar.ifs */ |
176 | st8 [r31] = r26, -8 /* save ar.ifs */ |
160 | 177 | ||
161 | and r24 = ~(RSC_PL_MASK), r24 ;; |
178 | and r24 = ~(RSC_PL_MASK), r24 ;; |
162 | and r30 = ~(RSC_MODE_MASK), r24 ;; |
179 | and r30 = ~(RSC_MODE_MASK), r24 ;; |
163 | mov ar.rsc = r30 ;; /* update RSE state */ |
180 | mov ar.rsc = r30 ;; /* update RSE state */ |
164 | 181 | ||
165 | mov r27 = ar.rnat |
182 | mov r27 = ar.rnat |
166 | mov r28 = ar.bspstore ;; |
183 | mov r28 = ar.bspstore ;; |
167 | 184 | ||
168 | /* |
185 | /* |
169 | * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE. |
186 | * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE. |
170 | */ |
187 | */ |
171 | (p1) shr.u r30 = r28, VRN_SHIFT ;; |
188 | (p1) shr.u r30 = r28, VRN_SHIFT ;; |
172 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; |
189 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; |
173 | 190 | ||
174 | /* |
191 | /* |
175 | * If BSPSTORE needs to be switched, p1 is false and p2 is true. |
192 | * If BSPSTORE needs to be switched, p1 is false and p2 is true. |
176 | */ |
193 | */ |
177 | (p1) mov r30 = r28 |
194 | (p1) mov r30 = r28 |
178 | (p2) mov r30 = R_KSTACK_BSP ;; |
195 | (p2) mov r30 = R_KSTACK_BSP ;; |
179 | (p2) mov ar.bspstore = r30 ;; |
196 | (p2) mov ar.bspstore = r30 ;; |
180 | 197 | ||
181 | mov r29 = ar.bsp |
198 | mov r29 = ar.bsp |
182 | 199 | ||
183 | st8 [r31] = r27, -8 ;; /* save ar.rnat */ |
200 | st8 [r31] = r27, -8 ;; /* save ar.rnat */ |
184 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */ |
201 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */ |
185 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */ |
202 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */ |
186 | st8 [r31] = r29, -8 /* save ar.bsp */ |
203 | st8 [r31] = r29, -8 /* save ar.bsp */ |
187 | 204 | ||
188 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ |
205 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ |
189 | 206 | ||
190 | /* steps 6 - 15 are done by heavyweight_handler_inner() */ |
207 | /* steps 6 - 15 are done by heavyweight_handler_inner() */ |
191 | mov R_RET = b0 /* save b0 belonging to interrupted context */ |
208 | mov R_RET = b0 /* save b0 belonging to interrupted context */ |
192 | br.call.sptk.many b0 = heavyweight_handler_inner |
209 | br.call.sptk.many b0 = heavyweight_handler_inner |
193 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
210 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
194 | 211 | ||
195 | /* 16. RSE switch to interrupted context */ |
212 | /* 16. RSE switch to interrupted context */ |
196 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
213 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
197 | 214 | ||
198 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;; |
215 | add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;; |
199 | 216 | ||
200 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
217 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
201 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
218 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
202 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
219 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
203 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
220 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
204 | shl r27 = r27, 16 |
221 | shl r27 = r27, 16 |
205 | 222 | ||
206 | mov r24 = ar.rsc ;; |
223 | mov r24 = ar.rsc ;; |
207 | and r30 = ~3, r24 ;; |
224 | and r30 = ~3, r24 ;; |
208 | or r24 = r30 , r27 ;; |
225 | or r24 = r30 , r27 ;; |
209 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */ |
226 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */ |
210 | 227 | ||
211 | loadrs /* (step 3) */ |
228 | loadrs /* (step 3) */ |
212 | 229 | ||
213 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */ |
230 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */ |
214 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */ |
231 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */ |
215 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */ |
232 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */ |
216 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */ |
233 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */ |
217 | 234 | ||
218 | mov ar.bspstore = r29 ;; /* (step 4) */ |
235 | mov ar.bspstore = r29 ;; /* (step 4) */ |
219 | mov ar.rnat = r27 /* (step 5) */ |
236 | mov ar.rnat = r27 /* (step 5) */ |
220 | 237 | ||
221 | mov ar.pfs = r25 /* (step 6) */ |
238 | mov ar.pfs = r25 /* (step 6) */ |
222 | mov cr.ifs = r26 |
239 | mov cr.ifs = r26 |
223 | 240 | ||
224 | mov ar.rsc = r24 /* (step 7) */ |
241 | mov ar.rsc = r24 /* (step 7) */ |
225 | 242 | ||
226 | /* 17. restore interruption state from memory stack */ |
243 | /* 17. restore interruption state from memory stack */ |
227 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
244 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
228 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
245 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
229 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
246 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
230 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
247 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
231 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
248 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
232 | 249 | ||
233 | mov cr.iip = r24 |
250 | mov cr.iip = r24;; |
234 | mov cr.ipsr = r25 |
- | |
235 | mov cr.iipa = r26 |
251 | mov cr.iipa = r26 |
236 | mov cr.isr = r27 |
252 | mov cr.isr = r27 |
237 | mov cr.ifa = r28 |
253 | mov cr.ifa = r28 |
- | 254 | /*Set up FPU as in exception*/ |
|
- | 255 | mov r24=psr |
|
- | 256 | mov r26=(PSR_DFH_MASK) |
|
- | 257 | mov r27=(~(PSR_DFH_MASK));; |
|
- | 258 | and r25=r25,r27 |
|
- | 259 | and r24=r24,r26;; |
|
- | 260 | or r25=r25,r24;; |
|
- | 261 | mov cr.ipsr = r25 |
|
- | 262 | ||
238 | 263 | ||
239 | /* 18. restore predicate registers from memory stack */ |
264 | /* 18. restore predicate registers from memory stack */ |
240 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
265 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
241 | mov pr = r29 |
266 | mov pr = r29 |
242 | 267 | ||
243 | /* 19. return from interruption */ |
268 | /* 19. return from interruption */ |
244 | ld8 r12 = [r31] /* load stack pointer */ |
269 | ld8 r12 = [r31] /* load stack pointer */ |
245 | rfi ;; |
270 | rfi ;; |
246 | 271 | ||
247 | .global heavyweight_handler_inner |
272 | .global heavyweight_handler_inner |
248 | heavyweight_handler_inner: |
273 | heavyweight_handler_inner: |
249 | /* |
274 | /* |
250 | * From this point, the rest of the interrupted context |
275 | * From this point, the rest of the interrupted context |
251 | * will be preserved in stacked registers and backing store. |
276 | * will be preserved in stacked registers and backing store. |
252 | */ |
277 | */ |
253 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; |
278 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; |
254 | 279 | ||
255 | /* bank 0 is going to be shadowed, copy essential data from there */ |
280 | /* bank 0 is going to be shadowed, copy essential data from there */ |
256 | mov loc1 = R_RET /* b0 belonging to interrupted context */ |
281 | mov loc1 = R_RET /* b0 belonging to interrupted context */ |
257 | mov loc2 = R_HANDLER |
282 | mov loc2 = R_HANDLER |
258 | mov out0 = R_OFFS |
283 | mov out0 = R_OFFS |
259 | 284 | ||
260 | add out1 = STACK_SCRATCH_AREA_SIZE, r12 |
285 | add out1 = STACK_SCRATCH_AREA_SIZE, r12 |
261 | 286 | ||
262 | /* 6. switch to bank 1 and reenable PSR.ic */ |
287 | /* 6. switch to bank 1 and reenable PSR.ic */ |
263 | ssm PSR_IC_MASK |
288 | ssm PSR_IC_MASK |
264 | bsw.1 ;; |
289 | bsw.1 ;; |
265 | srlz.d |
290 | srlz.d |
266 | 291 | ||
267 | /* 7. preserve branch and application registers */ |
292 | /* 7. preserve branch and application registers */ |
268 | mov loc3 = ar.unat |
293 | mov loc3 = ar.unat |
269 | mov loc4 = ar.lc |
294 | mov loc4 = ar.lc |
270 | mov loc5 = ar.ec |
295 | mov loc5 = ar.ec |
271 | mov loc6 = ar.ccv |
296 | mov loc6 = ar.ccv |
272 | mov loc7 = ar.csd |
297 | mov loc7 = ar.csd |
273 | mov loc8 = ar.ssd |
298 | mov loc8 = ar.ssd |
274 | 299 | ||
275 | mov loc9 = b0 |
300 | mov loc9 = b0 |
276 | mov loc10 = b1 |
301 | mov loc10 = b1 |
277 | mov loc11 = b2 |
302 | mov loc11 = b2 |
278 | mov loc12 = b3 |
303 | mov loc12 = b3 |
279 | mov loc13 = b4 |
304 | mov loc13 = b4 |
280 | mov loc14 = b5 |
305 | mov loc14 = b5 |
281 | mov loc15 = b6 |
306 | mov loc15 = b6 |
282 | mov loc16 = b7 |
307 | mov loc16 = b7 |
283 | 308 | ||
284 | /* 8. preserve general and floating-point registers */ |
309 | /* 8. preserve general and floating-point registers */ |
285 | /* TODO: save floating-point context */ |
310 | /* TODO: save floating-point context */ |
286 | mov loc17 = r1 |
311 | mov loc17 = r1 |
287 | mov loc18 = r2 |
312 | mov loc18 = r2 |
288 | mov loc19 = r3 |
313 | mov loc19 = r3 |
289 | mov loc20 = r4 |
314 | mov loc20 = r4 |
290 | mov loc21 = r5 |
315 | mov loc21 = r5 |
291 | mov loc22 = r6 |
316 | mov loc22 = r6 |
292 | mov loc23 = r7 |
317 | mov loc23 = r7 |
293 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */ |
318 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */ |
294 | mov loc25 = r9 |
319 | mov loc25 = r9 |
295 | mov loc26 = r10 |
320 | mov loc26 = r10 |
296 | mov loc27 = r11 |
321 | mov loc27 = r11 |
297 | /* skip r12 (stack pointer) */ |
322 | /* skip r12 (stack pointer) */ |
298 | mov loc28 = r13 |
323 | mov loc28 = r13 |
299 | mov loc29 = r14 |
324 | mov loc29 = r14 |
300 | mov loc30 = r15 |
325 | mov loc30 = r15 |
301 | mov loc31 = r16 |
326 | mov loc31 = r16 |
302 | mov loc32 = r17 |
327 | mov loc32 = r17 |
303 | mov loc33 = r18 |
328 | mov loc33 = r18 |
304 | mov loc34 = r19 |
329 | mov loc34 = r19 |
305 | mov loc35 = r20 |
330 | mov loc35 = r20 |
306 | mov loc36 = r21 |
331 | mov loc36 = r21 |
307 | mov loc37 = r22 |
332 | mov loc37 = r22 |
308 | mov loc38 = r23 |
333 | mov loc38 = r23 |
309 | mov loc39 = r24 |
334 | mov loc39 = r24 |
310 | mov loc40 = r25 |
335 | mov loc40 = r25 |
311 | mov loc41 = r26 |
336 | mov loc41 = r26 |
312 | mov loc42 = r27 |
337 | mov loc42 = r27 |
313 | mov loc43 = r28 |
338 | mov loc43 = r28 |
314 | mov loc44 = r29 |
339 | mov loc44 = r29 |
315 | mov loc45 = r30 |
340 | mov loc45 = r30 |
316 | mov loc46 = r31 |
341 | mov loc46 = r31 |
317 | 342 | ||
- | 343 | mov r24=96 + STACK_SCRATCH_AREA_SIZE |
|
- | 344 | mov r25=112 + STACK_SCRATCH_AREA_SIZE |
|
- | 345 | mov r26=0 + STACK_SCRATCH_AREA_SIZE |
|
- | 346 | mov r27=16 + STACK_SCRATCH_AREA_SIZE |
|
- | 347 | mov r28=32 + STACK_SCRATCH_AREA_SIZE |
|
- | 348 | mov r29=48 + STACK_SCRATCH_AREA_SIZE |
|
- | 349 | mov r30=64 + STACK_SCRATCH_AREA_SIZE |
|
- | 350 | mov r31=80 + STACK_SCRATCH_AREA_SIZE;; |
|
- | 351 | add r24=r12,r24 |
|
- | 352 | add r25=r12,r25 |
|
- | 353 | add r26=r12,r26 |
|
- | 354 | add r27=r12,r27 |
|
- | 355 | add r28=r12,r28 |
|
- | 356 | add r29=r12,r29 |
|
- | 357 | add r30=r12,r30 |
|
- | 358 | add r31=r12,r31;; |
|
- | 359 | ||
- | 360 | stf.spill [r26]=f2,0x80 |
|
- | 361 | stf.spill [r27]=f3,0x80 |
|
- | 362 | stf.spill [r28]=f4,0x80 |
|
- | 363 | stf.spill [r29]=f5,0x80 |
|
- | 364 | stf.spill [r30]=f6,0x80 |
|
- | 365 | stf.spill [r31]=f7,0x80;; |
|
- | 366 | ||
- | 367 | stf.spill [r24]=f8,0x80 |
|
- | 368 | stf.spill [r25]=f9,0x80 |
|
- | 369 | stf.spill [r26]=f10,0x80 |
|
- | 370 | stf.spill [r27]=f11,0x80 |
|
- | 371 | stf.spill [r28]=f12,0x80 |
|
- | 372 | stf.spill [r29]=f13,0x80 |
|
- | 373 | stf.spill [r30]=f14,0x80 |
|
- | 374 | stf.spill [r31]=f15,0x80;; |
|
- | 375 | ||
- | 376 | stf.spill [r24]=f16,0x80 |
|
- | 377 | stf.spill [r25]=f17,0x80 |
|
- | 378 | stf.spill [r26]=f18,0x80 |
|
- | 379 | stf.spill [r27]=f19,0x80 |
|
- | 380 | stf.spill [r28]=f20,0x80 |
|
- | 381 | stf.spill [r29]=f21,0x80 |
|
- | 382 | stf.spill [r30]=f22,0x80 |
|
- | 383 | stf.spill [r31]=f23,0x80;; |
|
- | 384 | ||
- | 385 | stf.spill [r24]=f24,0x80 |
|
- | 386 | stf.spill [r25]=f25,0x80 |
|
- | 387 | stf.spill [r26]=f26,0x80 |
|
- | 388 | stf.spill [r27]=f27,0x80 |
|
- | 389 | stf.spill [r28]=f28,0x80 |
|
- | 390 | stf.spill [r29]=f29,0x80 |
|
- | 391 | stf.spill [r30]=f30,0x80 |
|
- | 392 | stf.spill [r31]=f31,0x80;; |
|
- | 393 | ||
318 | /* preserve Floating point status register */ |
394 | /* preserve Floating point status register */ |
319 | mov loc47 = ar.fpsr |
395 | mov loc47 = ar.fpsr |
320 | 396 | ||
321 | /* 9. skipped (will not enable interrupts) */ |
397 | /* 9. skipped (will not enable interrupts) */ |
322 | /* |
398 | /* |
323 | * ssm PSR_I_MASK |
399 | * ssm PSR_I_MASK |
324 | * ;; |
400 | * ;; |
325 | * srlz.d |
401 | * srlz.d |
326 | */ |
402 | */ |
327 | 403 | ||
328 | /* 10. call handler */ |
404 | /* 10. call handler */ |
329 | movl r1 = _hardcoded_load_address |
405 | movl r1 = _hardcoded_load_address |
330 | 406 | ||
331 | mov b1 = loc2 |
407 | mov b1 = loc2 |
332 | br.call.sptk.many b0 = b1 |
408 | br.call.sptk.many b0 = b1 |
333 | 409 | ||
334 | /* 11. return from handler */ |
410 | /* 11. return from handler */ |
335 | 0: |
411 | 0: |
336 | 412 | ||
337 | /* 12. skipped (will not disable interrupts) */ |
413 | /* 12. skipped (will not disable interrupts) */ |
338 | /* |
414 | /* |
339 | * rsm PSR_I_MASK |
415 | * rsm PSR_I_MASK |
340 | * ;; |
416 | * ;; |
341 | * srlz.d |
417 | * srlz.d |
342 | */ |
418 | */ |
343 | 419 | ||
344 | /* 13. restore general and floating-point registers */ |
420 | /* 13. restore general and floating-point registers */ |
345 | /* TODO: restore floating-point context */ |
421 | /* TODO: restore floating-point context */ |
- | 422 | mov r24=96 + STACK_SCRATCH_AREA_SIZE |
|
- | 423 | mov r25=112 + STACK_SCRATCH_AREA_SIZE |
|
- | 424 | mov r26=0 + STACK_SCRATCH_AREA_SIZE |
|
- | 425 | mov r27=16 + STACK_SCRATCH_AREA_SIZE |
|
- | 426 | mov r28=32 + STACK_SCRATCH_AREA_SIZE |
|
- | 427 | mov r29=48 + STACK_SCRATCH_AREA_SIZE |
|
- | 428 | mov r30=64 + STACK_SCRATCH_AREA_SIZE |
|
- | 429 | mov r31=80 + STACK_SCRATCH_AREA_SIZE;; |
|
- | 430 | add r24=r12,r24 |
|
- | 431 | add r25=r12,r25 |
|
- | 432 | add r26=r12,r26 |
|
- | 433 | add r27=r12,r27 |
|
- | 434 | add r28=r12,r28 |
|
- | 435 | add r29=r12,r29 |
|
- | 436 | add r30=r12,r30 |
|
- | 437 | add r31=r12,r31;; |
|
- | 438 | ||
- | 439 | ||
- | 440 | ldf.fill f2=[r26],0x80 |
|
- | 441 | ldf.fill f3=[r27],0x80 |
|
- | 442 | ldf.fill f4=[r28],0x80 |
|
- | 443 | ldf.fill f5=[r29],0x80 |
|
- | 444 | ldf.fill f6=[r30],0x80 |
|
- | 445 | ldf.fill f7=[r31],0x80;; |
|
- | 446 | ||
- | 447 | ldf.fill f8=[r24],0x80 |
|
- | 448 | ldf.fill f9=[r25],0x80 |
|
- | 449 | ldf.fill f10=[r26],0x80 |
|
- | 450 | ldf.fill f11=[r27],0x80 |
|
- | 451 | ldf.fill f12=[r28],0x80 |
|
- | 452 | ldf.fill f13=[r29],0x80 |
|
- | 453 | ldf.fill f14=[r30],0x80 |
|
- | 454 | ldf.fill f15=[r31],0x80;; |
|
- | 455 | ||
- | 456 | ldf.fill f16=[r24],0x80 |
|
- | 457 | ldf.fill f17=[r25],0x80 |
|
- | 458 | ldf.fill f18=[r26],0x80 |
|
- | 459 | ldf.fill f19=[r27],0x80 |
|
- | 460 | ldf.fill f20=[r28],0x80 |
|
- | 461 | ldf.fill f21=[r29],0x80 |
|
- | 462 | ldf.fill f22=[r30],0x80 |
|
- | 463 | ldf.fill f23=[r31],0x80;; |
|
- | 464 | ||
- | 465 | ldf.fill f24=[r24],0x80 |
|
- | 466 | ldf.fill f25=[r25],0x80 |
|
- | 467 | ldf.fill f26=[r26],0x80 |
|
- | 468 | ldf.fill f27=[r27],0x80 |
|
- | 469 | ldf.fill f28=[r28],0x80 |
|
- | 470 | ldf.fill f29=[r29],0x80 |
|
- | 471 | ldf.fill f30=[r30],0x80 |
|
- | 472 | ldf.fill f31=[r31],0x80;; |
|
- | 473 | ||
- | 474 | ||
346 | mov r1 = loc17 |
475 | mov r1 = loc17 |
347 | mov r2 = loc18 |
476 | mov r2 = loc18 |
348 | mov r3 = loc19 |
477 | mov r3 = loc19 |
349 | mov r4 = loc20 |
478 | mov r4 = loc20 |
350 | mov r5 = loc21 |
479 | mov r5 = loc21 |
351 | mov r6 = loc22 |
480 | mov r6 = loc22 |
352 | mov r7 = loc23 |
481 | mov r7 = loc23 |
353 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */ |
482 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */ |
354 | mov r9 = loc25 |
483 | mov r9 = loc25 |
355 | mov r10 = loc26 |
484 | mov r10 = loc26 |
356 | mov r11 = loc27 |
485 | mov r11 = loc27 |
357 | /* skip r12 (stack pointer) */ |
486 | /* skip r12 (stack pointer) */ |
358 | mov r13 = loc28 |
487 | mov r13 = loc28 |
359 | mov r14 = loc29 |
488 | mov r14 = loc29 |
360 | mov r15 = loc30 |
489 | mov r15 = loc30 |
361 | mov r16 = loc31 |
490 | mov r16 = loc31 |
362 | mov r17 = loc32 |
491 | mov r17 = loc32 |
363 | mov r18 = loc33 |
492 | mov r18 = loc33 |
364 | mov r19 = loc34 |
493 | mov r19 = loc34 |
365 | mov r20 = loc35 |
494 | mov r20 = loc35 |
366 | mov r21 = loc36 |
495 | mov r21 = loc36 |
367 | mov r22 = loc37 |
496 | mov r22 = loc37 |
368 | mov r23 = loc38 |
497 | mov r23 = loc38 |
369 | mov r24 = loc39 |
498 | mov r24 = loc39 |
370 | mov r25 = loc40 |
499 | mov r25 = loc40 |
371 | mov r26 = loc41 |
500 | mov r26 = loc41 |
372 | mov r27 = loc42 |
501 | mov r27 = loc42 |
373 | mov r28 = loc43 |
502 | mov r28 = loc43 |
374 | mov r29 = loc44 |
503 | mov r29 = loc44 |
375 | mov r30 = loc45 |
504 | mov r30 = loc45 |
376 | mov r31 = loc46 |
505 | mov r31 = loc46 |
377 | 506 | ||
378 | /* restore Floating point status register */ |
507 | /* restore Floating point status register */ |
379 | mov ar.fpsr = loc47 |
508 | mov ar.fpsr = loc47 |
380 | 509 | ||
381 | /* 14. restore branch and application registers */ |
510 | /* 14. restore branch and application registers */ |
382 | mov ar.unat = loc3 |
511 | mov ar.unat = loc3 |
383 | mov ar.lc = loc4 |
512 | mov ar.lc = loc4 |
384 | mov ar.ec = loc5 |
513 | mov ar.ec = loc5 |
385 | mov ar.ccv = loc6 |
514 | mov ar.ccv = loc6 |
386 | mov ar.csd = loc7 |
515 | mov ar.csd = loc7 |
387 | mov ar.ssd = loc8 |
516 | mov ar.ssd = loc8 |
388 | 517 | ||
389 | mov b0 = loc9 |
518 | mov b0 = loc9 |
390 | mov b1 = loc10 |
519 | mov b1 = loc10 |
391 | mov b2 = loc11 |
520 | mov b2 = loc11 |
392 | mov b3 = loc12 |
521 | mov b3 = loc12 |
393 | mov b4 = loc13 |
522 | mov b4 = loc13 |
394 | mov b5 = loc14 |
523 | mov b5 = loc14 |
395 | mov b6 = loc15 |
524 | mov b6 = loc15 |
396 | mov b7 = loc16 |
525 | mov b7 = loc16 |
397 | 526 | ||
398 | /* 15. disable PSR.ic and switch to bank 0 */ |
527 | /* 15. disable PSR.ic and switch to bank 0 */ |
399 | rsm PSR_IC_MASK |
528 | rsm PSR_IC_MASK |
400 | bsw.0 ;; |
529 | bsw.0 ;; |
401 | srlz.d |
530 | srlz.d |
402 | 531 | ||
403 | mov R_RET = loc1 |
532 | mov R_RET = loc1 |
404 | mov ar.pfs = loc0 |
533 | mov ar.pfs = loc0 |
405 | br.ret.sptk.many b0 |
534 | br.ret.sptk.many b0 |
406 | 535 | ||
407 | .global ivt |
536 | .global ivt |
408 | .align 32768 |
537 | .align 32768 |
409 | ivt: |
538 | ivt: |
410 | HEAVYWEIGHT_HANDLER 0x0000 |
539 | HEAVYWEIGHT_HANDLER 0x0000 |
411 | HEAVYWEIGHT_HANDLER 0x0400 |
540 | HEAVYWEIGHT_HANDLER 0x0400 |
412 | HEAVYWEIGHT_HANDLER 0x0800 |
541 | HEAVYWEIGHT_HANDLER 0x0800 |
413 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault |
542 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault |
414 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault |
543 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault |
415 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault |
544 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault |
416 | HEAVYWEIGHT_HANDLER 0x1800 |
545 | HEAVYWEIGHT_HANDLER 0x1800 |
417 | HEAVYWEIGHT_HANDLER 0x1c00 |
546 | HEAVYWEIGHT_HANDLER 0x1c00 |
418 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault |
547 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault |
419 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault |
548 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault |
420 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault |
549 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault |
421 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction |
550 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction |
422 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
551 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
423 | HEAVYWEIGHT_HANDLER 0x3400 |
552 | HEAVYWEIGHT_HANDLER 0x3400 |
424 | HEAVYWEIGHT_HANDLER 0x3800 |
553 | HEAVYWEIGHT_HANDLER 0x3800 |
425 | HEAVYWEIGHT_HANDLER 0x3c00 |
554 | HEAVYWEIGHT_HANDLER 0x3c00 |
426 | HEAVYWEIGHT_HANDLER 0x4000 |
555 | HEAVYWEIGHT_HANDLER 0x4000 |
427 | HEAVYWEIGHT_HANDLER 0x4400 |
556 | HEAVYWEIGHT_HANDLER 0x4400 |
428 | HEAVYWEIGHT_HANDLER 0x4800 |
557 | HEAVYWEIGHT_HANDLER 0x4800 |
429 | HEAVYWEIGHT_HANDLER 0x4c00 |
558 | HEAVYWEIGHT_HANDLER 0x4c00 |
430 | 559 | ||
431 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present |
560 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present |
432 | HEAVYWEIGHT_HANDLER 0x5100 |
561 | HEAVYWEIGHT_HANDLER 0x5100 |
433 | HEAVYWEIGHT_HANDLER 0x5200 |
562 | HEAVYWEIGHT_HANDLER 0x5200 |
434 | HEAVYWEIGHT_HANDLER 0x5300 |
563 | HEAVYWEIGHT_HANDLER 0x5300 |
435 | HEAVYWEIGHT_HANDLER 0x5400 general_exception |
564 | HEAVYWEIGHT_HANDLER 0x5400 general_exception |
436 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register |
565 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register |
437 | HEAVYWEIGHT_HANDLER 0x5600 |
566 | HEAVYWEIGHT_HANDLER 0x5600 |
438 | HEAVYWEIGHT_HANDLER 0x5700 |
567 | HEAVYWEIGHT_HANDLER 0x5700 |
439 | HEAVYWEIGHT_HANDLER 0x5800 |
568 | HEAVYWEIGHT_HANDLER 0x5800 |
440 | HEAVYWEIGHT_HANDLER 0x5900 |
569 | HEAVYWEIGHT_HANDLER 0x5900 |
441 | HEAVYWEIGHT_HANDLER 0x5a00 |
570 | HEAVYWEIGHT_HANDLER 0x5a00 |
442 | HEAVYWEIGHT_HANDLER 0x5b00 |
571 | HEAVYWEIGHT_HANDLER 0x5b00 |
443 | HEAVYWEIGHT_HANDLER 0x5c00 |
572 | HEAVYWEIGHT_HANDLER 0x5c00 |
444 | HEAVYWEIGHT_HANDLER 0x5d00 |
573 | HEAVYWEIGHT_HANDLER 0x5d00 |
445 | HEAVYWEIGHT_HANDLER 0x5e00 |
574 | HEAVYWEIGHT_HANDLER 0x5e00 |
446 | HEAVYWEIGHT_HANDLER 0x5f00 |
575 | HEAVYWEIGHT_HANDLER 0x5f00 |
447 | 576 | ||
448 | HEAVYWEIGHT_HANDLER 0x6000 |
577 | HEAVYWEIGHT_HANDLER 0x6000 |
449 | HEAVYWEIGHT_HANDLER 0x6100 |
578 | HEAVYWEIGHT_HANDLER 0x6100 |
450 | HEAVYWEIGHT_HANDLER 0x6200 |
579 | HEAVYWEIGHT_HANDLER 0x6200 |
451 | HEAVYWEIGHT_HANDLER 0x6300 |
580 | HEAVYWEIGHT_HANDLER 0x6300 |
452 | HEAVYWEIGHT_HANDLER 0x6400 |
581 | HEAVYWEIGHT_HANDLER 0x6400 |
453 | HEAVYWEIGHT_HANDLER 0x6500 |
582 | HEAVYWEIGHT_HANDLER 0x6500 |
454 | HEAVYWEIGHT_HANDLER 0x6600 |
583 | HEAVYWEIGHT_HANDLER 0x6600 |
455 | HEAVYWEIGHT_HANDLER 0x6700 |
584 | HEAVYWEIGHT_HANDLER 0x6700 |
456 | HEAVYWEIGHT_HANDLER 0x6800 |
585 | HEAVYWEIGHT_HANDLER 0x6800 |
457 | HEAVYWEIGHT_HANDLER 0x6900 |
586 | HEAVYWEIGHT_HANDLER 0x6900 |
458 | HEAVYWEIGHT_HANDLER 0x6a00 |
587 | HEAVYWEIGHT_HANDLER 0x6a00 |
459 | HEAVYWEIGHT_HANDLER 0x6b00 |
588 | HEAVYWEIGHT_HANDLER 0x6b00 |
460 | HEAVYWEIGHT_HANDLER 0x6c00 |
589 | HEAVYWEIGHT_HANDLER 0x6c00 |
461 | HEAVYWEIGHT_HANDLER 0x6d00 |
590 | HEAVYWEIGHT_HANDLER 0x6d00 |
462 | HEAVYWEIGHT_HANDLER 0x6e00 |
591 | HEAVYWEIGHT_HANDLER 0x6e00 |
463 | HEAVYWEIGHT_HANDLER 0x6f00 |
592 | HEAVYWEIGHT_HANDLER 0x6f00 |
464 | 593 | ||
465 | HEAVYWEIGHT_HANDLER 0x7000 |
594 | HEAVYWEIGHT_HANDLER 0x7000 |
466 | HEAVYWEIGHT_HANDLER 0x7100 |
595 | HEAVYWEIGHT_HANDLER 0x7100 |
467 | HEAVYWEIGHT_HANDLER 0x7200 |
596 | HEAVYWEIGHT_HANDLER 0x7200 |
468 | HEAVYWEIGHT_HANDLER 0x7300 |
597 | HEAVYWEIGHT_HANDLER 0x7300 |
469 | HEAVYWEIGHT_HANDLER 0x7400 |
598 | HEAVYWEIGHT_HANDLER 0x7400 |
470 | HEAVYWEIGHT_HANDLER 0x7500 |
599 | HEAVYWEIGHT_HANDLER 0x7500 |
471 | HEAVYWEIGHT_HANDLER 0x7600 |
600 | HEAVYWEIGHT_HANDLER 0x7600 |
472 | HEAVYWEIGHT_HANDLER 0x7700 |
601 | HEAVYWEIGHT_HANDLER 0x7700 |
473 | HEAVYWEIGHT_HANDLER 0x7800 |
602 | HEAVYWEIGHT_HANDLER 0x7800 |
474 | HEAVYWEIGHT_HANDLER 0x7900 |
603 | HEAVYWEIGHT_HANDLER 0x7900 |
475 | HEAVYWEIGHT_HANDLER 0x7a00 |
604 | HEAVYWEIGHT_HANDLER 0x7a00 |
476 | HEAVYWEIGHT_HANDLER 0x7b00 |
605 | HEAVYWEIGHT_HANDLER 0x7b00 |
477 | HEAVYWEIGHT_HANDLER 0x7c00 |
606 | HEAVYWEIGHT_HANDLER 0x7c00 |
478 | HEAVYWEIGHT_HANDLER 0x7d00 |
607 | HEAVYWEIGHT_HANDLER 0x7d00 |
479 | HEAVYWEIGHT_HANDLER 0x7e00 |
608 | HEAVYWEIGHT_HANDLER 0x7e00 |
480 | HEAVYWEIGHT_HANDLER 0x7f00 |
609 | HEAVYWEIGHT_HANDLER 0x7f00 |
- | 610 | ||
- | 611 | ||
- | 612 | ||
- | 613 | ||
481 | 614 |