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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch.h> |
29 | #include <arch.h> |
30 | #include <arch/ski/ski.h> |
30 | #include <arch/ski/ski.h> |
31 | #include <arch/drivers/it.h> |
31 | #include <arch/drivers/it.h> |
32 | #include <arch/interrupt.h> |
32 | #include <arch/interrupt.h> |
33 | #include <arch/barrier.h> |
33 | #include <arch/barrier.h> |
34 | #include <arch/asm.h> |
34 | #include <arch/asm.h> |
35 | #include <arch/register.h> |
35 | #include <arch/register.h> |
36 | #include <arch/types.h> |
36 | #include <arch/types.h> |
37 | #include <arch/context.h> |
37 | #include <arch/context.h> |
38 | #include <arch/stack.h> |
38 | #include <arch/stack.h> |
39 | #include <arch/mm/page.h> |
39 | #include <arch/mm/page.h> |
40 | #include <mm/as.h> |
40 | #include <mm/as.h> |
41 | #include <config.h> |
41 | #include <config.h> |
42 | #include <userspace.h> |
42 | #include <userspace.h> |
43 | #include <console/console.h> |
43 | #include <console/console.h> |
44 | 44 | ||
45 | void arch_pre_mm_init(void) |
45 | void arch_pre_mm_init(void) |
46 | { |
46 | { |
47 | /* Set Interruption Vector Address (i.e. location of interruption vector table). */ |
47 | /* Set Interruption Vector Address (i.e. location of interruption vector table). */ |
48 | iva_write((__address) &ivt); |
48 | iva_write((__address) &ivt); |
49 | srlz_d(); |
49 | srlz_d(); |
50 | 50 | ||
51 | ski_init_console(); |
51 | ski_init_console(); |
52 | it_init(); |
52 | it_init(); |
53 | 53 | ||
54 | /* Setup usermode */ |
54 | /* Setup usermode */ |
55 | init.cnt = 1; |
55 | init.cnt = 2; |
56 | init.tasks[0].addr = INIT_ADDRESS; |
56 | init.tasks[0].addr = INIT0_ADDRESS; |
57 | init.tasks[0].size = INIT_SIZE; |
57 | init.tasks[0].size = INIT0_SIZE; |
- | 58 | init.tasks[1].addr = INIT1_ADDRESS; |
|
- | 59 | init.tasks[1].size = INIT1_SIZE; |
|
58 | } |
60 | } |
59 | 61 | ||
60 | void arch_post_mm_init(void) |
62 | void arch_post_mm_init(void) |
61 | { |
63 | { |
62 | } |
64 | } |
63 | 65 | ||
64 | void arch_pre_smp_init(void) |
66 | void arch_pre_smp_init(void) |
65 | { |
67 | { |
66 | } |
68 | } |
67 | 69 | ||
68 | void arch_post_smp_init(void) |
70 | void arch_post_smp_init(void) |
69 | { |
71 | { |
70 | } |
72 | } |
71 | 73 | ||
72 | /** Enter userspace and never return. */ |
74 | /** Enter userspace and never return. */ |
73 | void userspace(__address entry) |
75 | void userspace(__address entry) |
74 | { |
76 | { |
75 | psr_t psr; |
77 | psr_t psr; |
76 | rsc_t rsc; |
78 | rsc_t rsc; |
77 | 79 | ||
78 | psr.value = psr_read(); |
80 | psr.value = psr_read(); |
79 | psr.cpl = PL_USER; |
81 | psr.cpl = PL_USER; |
80 | psr.i = true; /* start with interrupts enabled */ |
82 | psr.i = true; /* start with interrupts enabled */ |
81 | psr.ic = true; |
83 | psr.ic = true; |
82 | psr.ri = 0; /* start with instruction #0 */ |
84 | psr.ri = 0; /* start with instruction #0 */ |
83 | psr.bn = 1; /* start in bank 0 */ |
85 | psr.bn = 1; /* start in bank 0 */ |
84 | 86 | ||
85 | __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); |
87 | __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); |
86 | rsc.loadrs = 0; |
88 | rsc.loadrs = 0; |
87 | rsc.be = false; |
89 | rsc.be = false; |
88 | rsc.pl = PL_USER; |
90 | rsc.pl = PL_USER; |
89 | rsc.mode = 3; /* eager mode */ |
91 | rsc.mode = 3; /* eager mode */ |
90 | 92 | ||
91 | switch_to_userspace(entry, USTACK_ADDRESS+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), USTACK_ADDRESS, psr.value, rsc.value); |
93 | switch_to_userspace(entry, USTACK_ADDRESS+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), USTACK_ADDRESS, psr.value, rsc.value); |
92 | 94 | ||
93 | while (1) { |
95 | while (1) { |
94 | ; |
96 | ; |
95 | } |
97 | } |
96 | } |
98 | } |
97 | 99 |