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/*
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/*
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 * Copyright (C) 2005 - 2006 Jakub Jermar
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 * Copyright (C) 2005 - 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Vana
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 * Copyright (C) 2006 Jakub Vana
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
11
 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
13
 *   notice, this list of conditions and the following disclaimer in the
13
 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
15
 * - The name of the author may not be used to endorse or promote products
16
 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
17
 *
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
28
 */
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29
 
30
#ifndef __ia64_PAGE_H__
30
#ifndef __ia64_PAGE_H__
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#define __ia64_PAGE_H__
31
#define __ia64_PAGE_H__
32
 
32
 
33
#include <arch/mm/frame.h>
33
#include <arch/mm/frame.h>
34
#include <genarch/mm/page_ht.h>
34
#include <genarch/mm/page_ht.h>
35
#include <arch/mm/asid.h>
35
#include <arch/mm/asid.h>
36
#include <arch/types.h>
36
#include <arch/types.h>
37
#include <typedefs.h>
37
#include <typedefs.h>
38
#include <debug.h>
38
#include <debug.h>
39
 
39
 
40
#define PAGE_SIZE   FRAME_SIZE
40
#define PAGE_SIZE   FRAME_SIZE
41
#define PAGE_WIDTH  FRAME_WIDTH
41
#define PAGE_WIDTH  FRAME_WIDTH
42
 
42
 
43
#define KA2PA(x)    ((__address) (x))
43
#define KA2PA(x)    ((__address) (x))
44
#define PA2KA(x)    ((__address) (x))
44
#define PA2KA(x)    ((__address) (x))
45
 
45
 
46
#define GET_PTL0_ADDRESS_ARCH()         ((pte_t *) 0)
46
#define GET_PTL0_ADDRESS_ARCH()         ((pte_t *) 0)
47
#define SET_PTL0_ADDRESS_ARCH(ptl0)
47
#define SET_PTL0_ADDRESS_ARCH(ptl0)
48
 
48
 
49
/** Implementation of page hash table interface. */
49
/** Implementation of page hash table interface. */
50
#define HT_ENTRIES_ARCH                 (VHPT_SIZE/sizeof(pte_t))
50
#define HT_ENTRIES_ARCH                 (VHPT_SIZE/sizeof(pte_t))
51
#define HT_HASH_ARCH(page, asid)            vhpt_hash((page), (asid))
51
#define HT_HASH_ARCH(page, asid)            vhpt_hash((page), (asid))
52
#define HT_COMPARE_ARCH(page, asid, t)          vhpt_compare((page), (asid), (t))
52
#define HT_COMPARE_ARCH(page, asid, t)          vhpt_compare((page), (asid), (t))
53
#define HT_SLOT_EMPTY_ARCH(t)               ((t)->present.tag.tag_info.ti)
53
#define HT_SLOT_EMPTY_ARCH(t)               ((t)->present.tag.tag_info.ti)
54
#define HT_INVALIDATE_SLOT_ARCH(t)          (t)->present.tag.tag_info.ti = true
54
#define HT_INVALIDATE_SLOT_ARCH(t)          (t)->present.tag.tag_info.ti = true
55
#define HT_GET_NEXT_ARCH(t)             (t)->present.next
55
#define HT_GET_NEXT_ARCH(t)             (t)->present.next
56
#define HT_SET_NEXT_ARCH(t, s)              (t)->present.next = (s)
56
#define HT_SET_NEXT_ARCH(t, s)              (t)->present.next = (s)
57
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
57
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
58
 
58
 
59
#define PPN_SHIFT           12
59
#define PPN_SHIFT           12
60
 
60
 
61
#define VRN_SHIFT           61
61
#define VRN_SHIFT           61
62
#define VRN_MASK            (7LL << VRN_SHIFT)
62
#define VRN_MASK            (7LL << VRN_SHIFT)
63
 
-
 
64
#define VRN_KERNEL          0
63
#define VRN_KERNEL          0
65
#define REGION_REGISTERS        8
64
#define REGION_REGISTERS        8
66
 
65
 
67
#define VHPT_WIDTH          20          /* 1M */
66
#define VHPT_WIDTH          20          /* 1M */
68
#define VHPT_SIZE           (1<<VHPT_WIDTH)
67
#define VHPT_SIZE           (1<<VHPT_WIDTH)
69
 
-
 
70
#define VHPT_BASE           page_ht     /* Must be aligned to VHPT_SIZE */
68
#define VHPT_BASE           page_ht     /* Must be aligned to VHPT_SIZE */
71
 
69
 
-
 
70
#define PTA_BASE_SHIFT          15
-
 
71
 
72
/** Memory Attributes. */
72
/** Memory Attributes. */
73
#define MA_WRITEBACK    0x0
73
#define MA_WRITEBACK    0x0
74
#define MA_UNCACHEABLE  0x4
74
#define MA_UNCACHEABLE  0x4
75
 
75
 
76
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
76
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
77
#define PL_KERNEL   0x0
77
#define PL_KERNEL   0x0
78
#define PL_USER     0x3
78
#define PL_USER     0x3
79
 
79
 
80
/* Access Rigths. Only certain combinations are used by the kernel. */
80
/* Access Rigths. Only certain combinations are used by the kernel. */
81
#define AR_READ     0x0
81
#define AR_READ     0x0
82
#define AR_EXECUTE  0x1
82
#define AR_EXECUTE  0x1
83
#define AR_WRITE    0x2
83
#define AR_WRITE    0x2
84
 
84
 
85
struct vhpt_tag_info {
85
struct vhpt_tag_info {
86
    unsigned long long tag : 63;
86
    unsigned long long tag : 63;
87
    unsigned ti : 1;
87
    unsigned ti : 1;
88
} __attribute__ ((packed));
88
} __attribute__ ((packed));
89
 
89
 
90
union vhpt_tag {
90
union vhpt_tag {
91
    struct vhpt_tag_info tag_info;
91
    struct vhpt_tag_info tag_info;
92
    unsigned tag_word;
92
    unsigned tag_word;
93
};
93
};
94
 
94
 
95
struct vhpt_entry_present {
95
struct vhpt_entry_present {
96
    /* Word 0 */
96
    /* Word 0 */
97
    unsigned p : 1;
97
    unsigned p : 1;
98
    unsigned : 1;
98
    unsigned : 1;
99
    unsigned ma : 3;
99
    unsigned ma : 3;
100
    unsigned a : 1;
100
    unsigned a : 1;
101
    unsigned d : 1;
101
    unsigned d : 1;
102
    unsigned pl : 2;
102
    unsigned pl : 2;
103
    unsigned ar : 3;
103
    unsigned ar : 3;
104
    unsigned long long ppn : 38;
104
    unsigned long long ppn : 38;
105
    unsigned : 2;
105
    unsigned : 2;
106
    unsigned ed : 1;
106
    unsigned ed : 1;
107
    unsigned ig1 : 11;
107
    unsigned ig1 : 11;
108
   
108
   
109
    /* Word 1 */
109
    /* Word 1 */
110
    unsigned : 2;
110
    unsigned : 2;
111
    unsigned ps : 6;
111
    unsigned ps : 6;
112
    unsigned key : 24;
112
    unsigned key : 24;
113
    unsigned : 32;
113
    unsigned : 32;
114
   
114
   
115
    /* Word 2 */
115
    /* Word 2 */
116
    union vhpt_tag tag;
116
    union vhpt_tag tag;
117
   
117
   
118
    /* Word 3 */                                                   
118
    /* Word 3 */                                                   
119
    pte_t *next;            /**< Collision chain next pointer. */
119
    pte_t *next;            /**< Collision chain next pointer. */
120
} __attribute__ ((packed));
120
} __attribute__ ((packed));
121
 
121
 
122
struct vhpt_entry_not_present {
122
struct vhpt_entry_not_present {
123
    /* Word 0 */
123
    /* Word 0 */
124
    unsigned p : 1;
124
    unsigned p : 1;
125
    unsigned long long ig0 : 52;
125
    unsigned long long ig0 : 52;
126
    unsigned ig1 : 11;
126
    unsigned ig1 : 11;
127
   
127
   
128
    /* Word 1 */
128
    /* Word 1 */
129
    unsigned : 2;
129
    unsigned : 2;
130
    unsigned ps : 6;
130
    unsigned ps : 6;
131
    unsigned long long ig2 : 56;
131
    unsigned long long ig2 : 56;
132
 
132
 
133
    /* Word 2 */
133
    /* Word 2 */
134
    union vhpt_tag tag;
134
    union vhpt_tag tag;
135
   
135
   
136
    /* Word 3 */                                                   
136
    /* Word 3 */                                                   
137
    pte_t *next;            /**< Collision chain next pointer. */
137
    pte_t *next;            /**< Collision chain next pointer. */
138
   
138
   
139
} __attribute__ ((packed));
139
} __attribute__ ((packed));
140
 
140
 
141
typedef union vhpt_entry {
141
typedef union vhpt_entry {
142
    struct vhpt_entry_present present;
142
    struct vhpt_entry_present present;
143
    struct vhpt_entry_not_present not_present;
143
    struct vhpt_entry_not_present not_present;
144
    __u64 word[4];
144
    __u64 word[4];
145
} vhpt_entry;
145
} vhpt_entry;
146
 
146
 
147
struct region_register_map {
147
struct region_register_map {
148
    unsigned ve : 1;
148
    unsigned ve : 1;
149
    unsigned : 1;
149
    unsigned : 1;
150
    unsigned ps : 6;
150
    unsigned ps : 6;
151
    unsigned rid : 24;
151
    unsigned rid : 24;
152
    unsigned : 32;
152
    unsigned : 32;
153
} __attribute__ ((packed));
153
} __attribute__ ((packed));
154
 
154
 
155
typedef union region_register {
155
typedef union region_register {
156
    struct region_register_map map;
156
    struct region_register_map map;
157
    unsigned long long word;
157
    unsigned long long word;
158
} region_register;
158
} region_register;
159
 
159
 
160
struct pta_register_map {
160
struct pta_register_map {
161
    unsigned ve : 1;
161
    unsigned ve : 1;
162
    unsigned : 1;
162
    unsigned : 1;
163
    unsigned size : 6;
163
    unsigned size : 6;
164
    unsigned vf : 1;
164
    unsigned vf : 1;
165
    unsigned : 6;
165
    unsigned : 6;
166
    unsigned long long base : 49;
166
    unsigned long long base : 49;
167
} __attribute__ ((packed));
167
} __attribute__ ((packed));
168
 
168
 
169
typedef union pta_register {
169
typedef union pta_register {
170
    struct pta_register_map map;
170
    struct pta_register_map map;
171
    __u64 word;
171
    __u64 word;
172
} pta_register;
172
} pta_register;
173
 
173
 
174
/** Return Translation Hashed Entry Address.
174
/** Return Translation Hashed Entry Address.
175
 *
175
 *
176
 * VRN bits are used to read RID (ASID) from one
176
 * VRN bits are used to read RID (ASID) from one
177
 * of the eight region registers registers.
177
 * of the eight region registers registers.
178
 *
178
 *
179
 * @param va Virtual address including VRN bits.
179
 * @param va Virtual address including VRN bits.
180
 *
180
 *
181
 * @return Address of the head of VHPT collision chain.
181
 * @return Address of the head of VHPT collision chain.
182
 */
182
 */
183
static inline __u64 thash(__u64 va)
183
static inline __u64 thash(__u64 va)
184
{
184
{
185
    __u64 ret;
185
    __u64 ret;
186
 
186
 
187
    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
187
    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
188
 
188
 
189
    return ret;
189
    return ret;
190
}
190
}
191
 
191
 
192
/** Return Translation Hashed Entry Tag.
192
/** Return Translation Hashed Entry Tag.
193
 *
193
 *
194
 * VRN bits are used to read RID (ASID) from one
194
 * VRN bits are used to read RID (ASID) from one
195
 * of the eight region registers.
195
 * of the eight region registers.
196
 *
196
 *
197
 * @param va Virtual address including VRN bits.
197
 * @param va Virtual address including VRN bits.
198
 *
198
 *
199
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
199
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
200
 */
200
 */
201
static inline __u64 ttag(__u64 va)
201
static inline __u64 ttag(__u64 va)
202
{
202
{
203
    __u64 ret;
203
    __u64 ret;
204
 
204
 
205
    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
205
    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
206
 
206
 
207
    return ret;
207
    return ret;
208
}
208
}
209
 
209
 
210
/** Read Region Register.
210
/** Read Region Register.
211
 *
211
 *
212
 * @param i Region register index.
212
 * @param i Region register index.
213
 *
213
 *
214
 * @return Current contents of rr[i].
214
 * @return Current contents of rr[i].
215
 */
215
 */
216
static inline __u64 rr_read(index_t i)
216
static inline __u64 rr_read(index_t i)
217
{
217
{
218
    __u64 ret;
218
    __u64 ret;
219
   
219
   
220
    ASSERT(i < REGION_REGISTERS);
220
    ASSERT(i < REGION_REGISTERS);
221
    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
221
    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
222
   
222
   
223
    return ret;
223
    return ret;
224
}
224
}
225
 
225
 
226
 
226
 
227
/** Write Region Register.
227
/** Write Region Register.
228
 *
228
 *
229
 * @param i Region register index.
229
 * @param i Region register index.
230
 * @param v Value to be written to rr[i].
230
 * @param v Value to be written to rr[i].
231
 */
231
 */
232
static inline void rr_write(index_t i, __u64 v)
232
static inline void rr_write(index_t i, __u64 v)
233
{
233
{
234
    ASSERT(i < REGION_REGISTERS);
234
    ASSERT(i < REGION_REGISTERS);
235
    __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
235
    __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
236
}
236
}
237
 
237
 
238
/** Read Page Table Register.
238
/** Read Page Table Register.
239
 *
239
 *
240
 * @return Current value stored in PTA.
240
 * @return Current value stored in PTA.
241
 */
241
 */
242
static inline __u64 pta_read(void)
242
static inline __u64 pta_read(void)
243
{
243
{
244
    __u64 ret;
244
    __u64 ret;
245
   
245
   
246
    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
246
    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
247
   
247
   
248
    return ret;
248
    return ret;
249
}
249
}
250
 
250
 
251
/** Write Page Table Register.
251
/** Write Page Table Register.
252
 *
252
 *
253
 * @param v New value to be stored in PTA.
253
 * @param v New value to be stored in PTA.
254
 */
254
 */
255
static inline void pta_write(__u64 v)
255
static inline void pta_write(__u64 v)
256
{
256
{
257
    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
257
    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
258
}
258
}
259
 
259
 
260
extern void page_arch_init(void);
260
extern void page_arch_init(void);
261
extern pte_t *vhpt_hash(__address page, asid_t asid);
261
extern pte_t *vhpt_hash(__address page, asid_t asid);
262
extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
262
extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
263
extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
263
extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
264
 
264
 
265
#endif
265
#endif
266
 
266