WebSVN – HelenOS – Diff – /branches/network/kernel/arch/ia32/src/pm.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia32   
 * @{
 */
/** @file
 */
 
#include <arch/pm.h>
#include <config.h>
#include <arch/types.h>
#include <typedefs.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <arch/context.h>
#include <panic.h>
#include <arch/mm/page.h>
#include <mm/slab.h>
#include <memstr.h>
#include <arch/boot/boot.h>
#include <interrupt.h>
 
/*
 * Early ia32 configuration functions and data structures.
 */
 
/*
 * We have no use for segmentation so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 *
 * One is for GS register which holds pointer to the TLS thread
 * structure in it's base.
 */
descriptor_t gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
    /* KDATA descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
    /* UTEXT descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* UDATA descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* TSS descriptor - set up will be completed later */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* TLS descriptor */
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    /* VESA Init descriptor */
#ifdef CONFIG_FB
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
#endif  
};
 
static idescriptor_t idt[IDT_ITEMS];
 
static tss_t tss;
 
tss_t *tss_p = NULL;
 
/* gdtr is changed by kmp before next CPU is initialized */
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
 
void gdt_setbase(descriptor_t *d, uintptr_t base)
{
    d->base_0_15 = base & 0xffff;
    d->base_16_23 = ((base) >> 16) & 0xff;
    d->base_24_31 = ((base) >> 24) & 0xff;
}
 
void gdt_setlimit(descriptor_t *d, uint32_t limit)
{
    d->limit_0_15 = limit & 0xffff;
    d->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16;
}
 
void tss_initialize(tss_t *t)
{
    memsetb((uintptr_t) t, sizeof(struct tss), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    idescriptor_t *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = selector(KTEXT_DES);
 
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
 
        if (i == VECTOR_SYSCALL) {
            /*
             * The syscall interrupt gate must be calleable from userland.
             */
            d->access |= DPL_USER;
        }
       
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
        exc_register(i, "undef", (iroutine) null_interrupt);
    }
    exc_register(13, "gp_fault", (iroutine) gp_fault);
    exc_register( 7, "nm_fault", (iroutine) nm_fault);
    exc_register(12, "ss_fault", (iroutine) ss_fault);
    exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
    __asm__ volatile (
        "pushfl\n"
        "pop %%eax\n"
        "and $0xffff8fff, %%eax\n"
        "push %%eax\n"
        "popfl\n"
        : : : "eax"
    );
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
    __asm__ volatile (
        "mov %%cr0, %%eax\n"
        "and $0xfffbffff, %%eax\n"
        "mov %%eax, %%cr0\n"
        : : : "eax"
    );
}
 
void pm_init(void)
{
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
    ptr_16_32_t idtr;
 
    /*
     * Update addresses in GDT and IDT to their virtual counterparts.
     */
    idtr.limit = sizeof(idt);
    idtr.base = (uintptr_t) idt;
    gdtr_load(&gdtr);
    idtr_load(&idtr);
   
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
 
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
   
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
    gdt_p[TSS_DES].special = 1;
    gdt_p[TSS_DES].granularity = 0;
   
    gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    tr_load(selector(TSS_DES));
   
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
    clean_AM_flag();          /* Disable alignment check */
}
 
void set_tls_desc(uintptr_t tls)
{
    ptr_16_32_t cpugdtr;
    descriptor_t *gdt_p;
 
    gdtr_store(&cpugdtr);
    gdt_p = (descriptor_t *) cpugdtr.base;
    gdt_setbase(&gdt_p[TLS_DES], tls);
    /* Reload gdt register to update GS in CPU */
    gdtr_load(&cpugdtr);
}
 
/** @}
 */
 
 

Rev 1787	Rev 1888
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia32	29	/** @addtogroup ia32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/pm.h>	35	#include <arch/pm.h>
36	#include <config.h>	36	#include <config.h>
37	#include <arch/types.h>	37	#include <arch/types.h>
38	#include <typedefs.h>	38	#include <typedefs.h>
39	#include <arch/interrupt.h>	39	#include <arch/interrupt.h>
40	#include <arch/asm.h>	40	#include <arch/asm.h>
41	#include <arch/context.h>	41	#include <arch/context.h>
42	#include <panic.h>	42	#include <panic.h>
43	#include <arch/mm/page.h>	43	#include <arch/mm/page.h>
44	#include <mm/slab.h>	44	#include <mm/slab.h>
45	#include <memstr.h>	45	#include <memstr.h>
46	#include <arch/boot/boot.h>	46	#include <arch/boot/boot.h>
47	#include <interrupt.h>	47	#include <interrupt.h>
48		48
49	/*	49	/*
50	* Early ia32 configuration functions and data structures.	50	* Early ia32 configuration functions and data structures.
51	*/	51	*/
52		52
53	/*	53	/*
54	* We have no use for segmentation so we set up flat mode. In this	54	* We have no use for segmentation so we set up flat mode. In this
55	* mode, we use, for each privilege level, two segments spanning the	55	* mode, we use, for each privilege level, two segments spanning the
56	* whole memory. One is for code and one is for data.	56	* whole memory. One is for code and one is for data.
57	*	57	*
58	* One is for GS register which holds pointer to the TLS thread	58	* One is for GS register which holds pointer to the TLS thread
59	* structure in it's base.	59	* structure in it's base.
60	*/	60	*/
61	descriptor_t gdt[GDT_ITEMS] = {	61	descriptor_t gdt[GDT_ITEMS] = {
62	/* NULL descriptor */	62	/* NULL descriptor */
63	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	63	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
64	/* KTEXT descriptor */	64	/* KTEXT descriptor */
65	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },	65	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
66	/* KDATA descriptor */	66	/* KDATA descriptor */
67	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },	67	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
68	/* UTEXT descriptor */	68	/* UTEXT descriptor */
69	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	69	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
70	/* UDATA descriptor */	70	/* UDATA descriptor */
71	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	71	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
72	/* TSS descriptor - set up will be completed later */	72	/* TSS descriptor - set up will be completed later */
73	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	73	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
74	/* TLS descriptor */	74	/* TLS descriptor */
75	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },	75	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
76	/* VESA Init descriptor */	76	/* VESA Init descriptor */
77	#ifdef CONFIG_FB	77	#ifdef CONFIG_FB
78	{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }	78	{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
79	#endif	79	#endif
80	};	80	};
81		81
82	static idescriptor_t idt[IDT_ITEMS];	82	static idescriptor_t idt[IDT_ITEMS];
83		83
84	static tss_t tss;	84	static tss_t tss;
85		85
86	tss_t *tss_p = NULL;	86	tss_t *tss_p = NULL;
87		87
88	/* gdtr is changed by kmp before next CPU is initialized */	88	/* gdtr is changed by kmp before next CPU is initialized */
89	ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };	89	ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
90	ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };	90	ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
91		91
92	void gdt_setbase(descriptor_t *d, uintptr_t base)	92	void gdt_setbase(descriptor_t *d, uintptr_t base)
93	{	93	{
94	d->base_0_15 = base & 0xffff;	94	d->base_0_15 = base & 0xffff;
95	d->base_16_23 = ((base) >> 16) & 0xff;	95	d->base_16_23 = ((base) >> 16) & 0xff;
96	d->base_24_31 = ((base) >> 24) & 0xff;	96	d->base_24_31 = ((base) >> 24) & 0xff;
97	}	97	}
98		98
99	void gdt_setlimit(descriptor_t *d, uint32_t limit)	99	void gdt_setlimit(descriptor_t *d, uint32_t limit)
100	{	100	{
101	d->limit_0_15 = limit & 0xffff;	101	d->limit_0_15 = limit & 0xffff;
102	d->limit_16_19 = (limit >> 16) & 0xf;	102	d->limit_16_19 = (limit >> 16) & 0xf;
103	}	103	}
104		104
105	void idt_setoffset(idescriptor_t *d, uintptr_t offset)	105	void idt_setoffset(idescriptor_t *d, uintptr_t offset)
106	{	106	{
107	/*	107	/*
108	* Offset is a linear address.	108	* Offset is a linear address.
109	*/	109	*/
110	d->offset_0_15 = offset & 0xffff;	110	d->offset_0_15 = offset & 0xffff;
111	d->offset_16_31 = offset >> 16;	111	d->offset_16_31 = offset >> 16;
112	}	112	}
113		113
114	void tss_initialize(tss_t *t)	114	void tss_initialize(tss_t *t)
115	{	115	{
116	memsetb((uintptr_t) t, sizeof(struct tss), 0);	116	memsetb((uintptr_t) t, sizeof(struct tss), 0);
117	}	117	}
118		118
119	/*	119	/*
120	* This function takes care of proper setup of IDT and IDTR.	120	* This function takes care of proper setup of IDT and IDTR.
121	*/	121	*/
122	void idt_init(void)	122	void idt_init(void)
123	{	123	{
124	idescriptor_t *d;	124	idescriptor_t *d;
125	int i;	125	int i;
126		126
127	for (i = 0; i < IDT_ITEMS; i++) {	127	for (i = 0; i < IDT_ITEMS; i++) {
128	d = &idt[i];	128	d = &idt[i];
129		129
130	d->unused = 0;	130	d->unused = 0;
131	d->selector = selector(KTEXT_DES);	131	d->selector = selector(KTEXT_DES);
132		132
133	d->access = AR_PRESENT \| AR_INTERRUPT; /* masking interrupt */	133	d->access = AR_PRESENT \| AR_INTERRUPT; /* masking interrupt */
134		134
135	if (i == VECTOR_SYSCALL) {	135	if (i == VECTOR_SYSCALL) {
136	/*	136	/*
137	* The syscall interrupt gate must be calleable from userland.	137	* The syscall interrupt gate must be calleable from userland.
138	*/	138	*/
139	d->access \|= DPL_USER;	139	d->access \|= DPL_USER;
140	}	140	}
141		141
142	idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);	142	idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
143	exc_register(i, "undef", (iroutine) null_interrupt);	143	exc_register(i, "undef", (iroutine) null_interrupt);
144	}	144	}
145	exc_register(13, "gp_fault", (iroutine) gp_fault);	145	exc_register(13, "gp_fault", (iroutine) gp_fault);
146	exc_register( 7, "nm_fault", (iroutine) nm_fault);	146	exc_register( 7, "nm_fault", (iroutine) nm_fault);
147	exc_register(12, "ss_fault", (iroutine) ss_fault);	147	exc_register(12, "ss_fault", (iroutine) ss_fault);
148	exc_register(19, "simd_fp", (iroutine) simd_fp_exception);	148	exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
149	}	149	}
150		150
151		151
152	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */	152	/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
153	static void clean_IOPL_NT_flags(void)	153	static void clean_IOPL_NT_flags(void)
154	{	154	{
155	__asm__ volatile (	155	__asm__ volatile (
156	"pushfl\n"	156	"pushfl\n"
157	"pop %%eax\n"	157	"pop %%eax\n"
158	"and $0xffff8fff, %%eax\n"	158	"and $0xffff8fff, %%eax\n"
159	"push %%eax\n"	159	"push %%eax\n"
160	"popfl\n"	160	"popfl\n"
161	: : : "eax"	161	: : : "eax"
162	);	162	);
163	}	163	}
164		164
165	/* Clean AM(18) flag in CR0 register */	165	/* Clean AM(18) flag in CR0 register */
166	static void clean_AM_flag(void)	166	static void clean_AM_flag(void)
167	{	167	{
168	__asm__ volatile (	168	__asm__ volatile (
169	"mov %%cr0, %%eax\n"	169	"mov %%cr0, %%eax\n"
170	"and $0xfffbffff, %%eax\n"	170	"and $0xfffbffff, %%eax\n"
171	"mov %%eax, %%cr0\n"	171	"mov %%eax, %%cr0\n"
172	: : : "eax"	172	: : : "eax"
173	);	173	);
174	}	174	}
175		175
176	void pm_init(void)	176	void pm_init(void)
177	{	177	{
178	descriptor_t gdt_p = (descriptor_t ) gdtr.base;	178	descriptor_t gdt_p = (descriptor_t ) gdtr.base;
179	ptr_16_32_t idtr;	179	ptr_16_32_t idtr;
180		180
181	/*	181	/*
182	* Update addresses in GDT and IDT to their virtual counterparts.	182	* Update addresses in GDT and IDT to their virtual counterparts.
183	*/	183	*/
184	idtr.limit = sizeof(idt);	184	idtr.limit = sizeof(idt);
185	idtr.base = (uintptr_t) idt;	185	idtr.base = (uintptr_t) idt;
186	gdtr_load(&gdtr);	186	gdtr_load(&gdtr);
187	idtr_load(&idtr);	187	idtr_load(&idtr);
188		188
189	/*	189	/*
190	* Each CPU has its private GDT and TSS.	190	* Each CPU has its private GDT and TSS.
191	* All CPUs share one IDT.	191	* All CPUs share one IDT.
192	*/	192	*/
193		193
194	if (config.cpu_active == 1) {	194	if (config.cpu_active == 1) {
195	idt_init();	195	idt_init();
196	/*	196	/*
197	* NOTE: bootstrap CPU has statically allocated TSS, because	197	* NOTE: bootstrap CPU has statically allocated TSS, because
198	* the heap hasn't been initialized so far.	198	* the heap hasn't been initialized so far.
199	*/	199	*/
200	tss_p = &tss;	200	tss_p = &tss;
201	}	201	}
202	else {	202	else {
203	tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);	203	tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
204	if (!tss_p)	204	if (!tss_p)
205	panic("could not allocate TSS\n");	205	panic("could not allocate TSS\n");
206	}	206	}
207		207
208	tss_initialize(tss_p);	208	tss_initialize(tss_p);
209		209
210	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;	210	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;
211	gdt_p[TSS_DES].special = 1;	211	gdt_p[TSS_DES].special = 1;
212	gdt_p[TSS_DES].granularity = 0;	212	gdt_p[TSS_DES].granularity = 0;
213		213
214	gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);	214	gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
215	gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);	215	gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
216		216
217	/*	217	/*
218	* As of this moment, the current CPU has its own GDT pointing	218	* As of this moment, the current CPU has its own GDT pointing
219	* to its own TSS. We just need to load the TR register.	219	* to its own TSS. We just need to load the TR register.
220	*/	220	*/
221	tr_load(selector(TSS_DES));	221	tr_load(selector(TSS_DES));
222		222
223	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */	223	clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
224	clean_AM_flag(); /* Disable alignment check */	224	clean_AM_flag(); /* Disable alignment check */
225	}	225	}
226		226
227	void set_tls_desc(uintptr_t tls)	227	void set_tls_desc(uintptr_t tls)
228	{	228	{
229	ptr_16_32_t cpugdtr;	229	ptr_16_32_t cpugdtr;
230	descriptor_t *gdt_p;	230	descriptor_t *gdt_p;
231		231
232	gdtr_store(&cpugdtr);	232	gdtr_store(&cpugdtr);
233	gdt_p = (descriptor_t *) cpugdtr.base;	233	gdt_p = (descriptor_t *) cpugdtr.base;
234	gdt_setbase(&gdt_p[TLS_DES], tls);	234	gdt_setbase(&gdt_p[TLS_DES], tls);
235	/* Reload gdt register to update GS in CPU */	235	/* Reload gdt register to update GS in CPU */
236	gdtr_load(&cpugdtr);	236	gdtr_load(&cpugdtr);
237	}	237	}
238		238
239	/** @}	239	/** @}
240	*/	240	*/
241		-
242		241

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(root)/branches/network/kernel/arch/ia32/src/pm.c @ 4717 – Rev 1787 → 1888