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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
- | 3 | * Copyright (C) 2005 Sergey Bondari |
|
3 | * All rights reserved. |
4 | * All rights reserved. |
4 | * |
5 | * |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
7 | * are met: |
8 | * are met: |
8 | * |
9 | * |
9 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
16 | * |
17 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
28 | */ |
28 | 29 | ||
29 | #ifndef __ia32_ASM_H__ |
30 | #ifndef __ia32_ASM_H__ |
30 | #define __ia32_ASM_H__ |
31 | #define __ia32_ASM_H__ |
31 | 32 | ||
32 | #include <arch/types.h> |
33 | #include <arch/types.h> |
33 | #include <config.h> |
34 | #include <config.h> |
34 | 35 | ||
35 | extern __u32 interrupt_handler_size; |
36 | extern __u32 interrupt_handler_size; |
36 | 37 | ||
37 | extern void paging_on(void); |
38 | extern void paging_on(void); |
38 | 39 | ||
39 | extern void interrupt_handlers(void); |
40 | extern void interrupt_handlers(void); |
40 | 41 | ||
41 | extern void enable_l_apic_in_msr(void); |
42 | extern void enable_l_apic_in_msr(void); |
42 | 43 | ||
43 | 44 | ||
44 | void asm_delay_loop(__u32 t); |
45 | void asm_delay_loop(__u32 t); |
45 | void asm_fake_loop(__u32 t); |
46 | void asm_fake_loop(__u32 t); |
46 | 47 | ||
47 | 48 | ||
48 | /** Halt CPU |
49 | /** Halt CPU |
49 | * |
50 | * |
50 | * Halt the current CPU until interrupt event. |
51 | * Halt the current CPU until interrupt event. |
51 | */ |
52 | */ |
52 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
53 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
53 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
54 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
54 | 55 | ||
55 | /** Read CR2 |
56 | /** Read CR2 |
56 | * |
57 | * |
57 | * Return value in CR2 |
58 | * Return value in CR2 |
58 | * |
59 | * |
59 | * @return Value read. |
60 | * @return Value read. |
60 | */ |
61 | */ |
61 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; } |
62 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; } |
62 | 63 | ||
63 | /** Write CR3 |
64 | /** Write CR3 |
64 | * |
65 | * |
65 | * Write value to CR3. |
66 | * Write value to CR3. |
66 | * |
67 | * |
67 | * @param v Value to be written. |
68 | * @param v Value to be written. |
68 | */ |
69 | */ |
69 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
70 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
70 | 71 | ||
71 | /** Read CR3 |
72 | /** Read CR3 |
72 | * |
73 | * |
73 | * Return value in CR3 |
74 | * Return value in CR3 |
74 | * |
75 | * |
75 | * @return Value read. |
76 | * @return Value read. |
76 | */ |
77 | */ |
77 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; } |
78 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; } |
78 | 79 | ||
79 | /** Byte to port |
80 | /** Byte to port |
80 | * |
81 | * |
81 | * Output byte to port |
82 | * Output byte to port |
82 | * |
83 | * |
83 | * @param port Port to write to |
84 | * @param port Port to write to |
84 | * @param val Value to write |
85 | * @param val Value to write |
85 | */ |
86 | */ |
86 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
87 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
87 | 88 | ||
88 | /** Word to port |
89 | /** Word to port |
89 | * |
90 | * |
90 | * Output word to port |
91 | * Output word to port |
91 | * |
92 | * |
92 | * @param port Port to write to |
93 | * @param port Port to write to |
93 | * @param val Value to write |
94 | * @param val Value to write |
94 | */ |
95 | */ |
95 | static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
96 | static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
96 | 97 | ||
97 | /** Double word to port |
98 | /** Double word to port |
98 | * |
99 | * |
99 | * Output double word to port |
100 | * Output double word to port |
100 | * |
101 | * |
101 | * @param port Port to write to |
102 | * @param port Port to write to |
102 | * @param val Value to write |
103 | * @param val Value to write |
103 | */ |
104 | */ |
104 | static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
105 | static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
105 | 106 | ||
106 | /** Byte from port |
107 | /** Byte from port |
107 | * |
108 | * |
108 | * Get byte from port |
109 | * Get byte from port |
109 | * |
110 | * |
110 | * @param port Port to read from |
111 | * @param port Port to read from |
111 | * @return Value read |
112 | * @return Value read |
112 | */ |
113 | */ |
113 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
114 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
114 | 115 | ||
115 | /** Word from port |
116 | /** Word from port |
116 | * |
117 | * |
117 | * Get word from port |
118 | * Get word from port |
118 | * |
119 | * |
119 | * @param port Port to read from |
120 | * @param port Port to read from |
120 | * @return Value read |
121 | * @return Value read |
121 | */ |
122 | */ |
122 | static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
123 | static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
123 | 124 | ||
124 | /** Double word from port |
125 | /** Double word from port |
125 | * |
126 | * |
126 | * Get double word from port |
127 | * Get double word from port |
127 | * |
128 | * |
128 | * @param port Port to read from |
129 | * @param port Port to read from |
129 | * @return Value read |
130 | * @return Value read |
130 | */ |
131 | */ |
131 | static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
132 | static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
132 | 133 | ||
133 | /** Set priority level low |
134 | /** Set priority level low |
134 | * |
135 | * |
135 | * Enable interrupts and return previous |
136 | * Enable interrupts and return previous |
136 | * value of EFLAGS. |
137 | * value of EFLAGS. |
137 | */ |
138 | */ |
138 | static inline pri_t cpu_priority_low(void) { |
139 | static inline pri_t cpu_priority_low(void) { |
139 | pri_t v; |
140 | pri_t v; |
140 | __asm__ volatile ( |
141 | __asm__ volatile ( |
141 | "pushf\n\t" |
142 | "pushf\n\t" |
142 | "popl %0\n\t" |
143 | "popl %0\n\t" |
143 | "sti\n" |
144 | "sti\n" |
144 | : "=r" (v) |
145 | : "=r" (v) |
145 | ); |
146 | ); |
146 | return v; |
147 | return v; |
147 | } |
148 | } |
148 | 149 | ||
149 | /** Set priority level high |
150 | /** Set priority level high |
150 | * |
151 | * |
151 | * Disable interrupts and return previous |
152 | * Disable interrupts and return previous |
152 | * value of EFLAGS. |
153 | * value of EFLAGS. |
153 | */ |
154 | */ |
154 | static inline pri_t cpu_priority_high(void) { |
155 | static inline pri_t cpu_priority_high(void) { |
155 | pri_t v; |
156 | pri_t v; |
156 | __asm__ volatile ( |
157 | __asm__ volatile ( |
157 | "pushf\n\t" |
158 | "pushf\n\t" |
158 | "popl %0\n\t" |
159 | "popl %0\n\t" |
159 | "cli\n" |
160 | "cli\n" |
160 | : "=r" (v) |
161 | : "=r" (v) |
161 | ); |
162 | ); |
162 | return v; |
163 | return v; |
163 | } |
164 | } |
164 | 165 | ||
165 | /** Restore priority level |
166 | /** Restore priority level |
166 | * |
167 | * |
167 | * Restore EFLAGS. |
168 | * Restore EFLAGS. |
168 | */ |
169 | */ |
169 | static inline void cpu_priority_restore(pri_t pri) { |
170 | static inline void cpu_priority_restore(pri_t pri) { |
170 | __asm__ volatile ( |
171 | __asm__ volatile ( |
171 | "pushl %0\n\t" |
172 | "pushl %0\n\t" |
172 | "popf\n" |
173 | "popf\n" |
173 | : : "r" (pri) |
174 | : : "r" (pri) |
174 | ); |
175 | ); |
175 | } |
176 | } |
176 | 177 | ||
177 | /** Return raw priority level |
178 | /** Return raw priority level |
178 | * |
179 | * |
179 | * Return EFLAFS. |
180 | * Return EFLAFS. |
180 | */ |
181 | */ |
181 | static inline pri_t cpu_priority_read(void) { |
182 | static inline pri_t cpu_priority_read(void) { |
182 | pri_t v; |
183 | pri_t v; |
183 | __asm__ volatile ( |
184 | __asm__ volatile ( |
184 | "pushf\n\t" |
185 | "pushf\n\t" |
185 | "popl %0\n" |
186 | "popl %0\n" |
186 | : "=r" (v) |
187 | : "=r" (v) |
187 | ); |
188 | ); |
188 | return v; |
189 | return v; |
189 | } |
190 | } |
190 | 191 | ||
191 | /** Return base address of current stack |
192 | /** Return base address of current stack |
192 | * |
193 | * |
193 | * Return the base address of the current stack. |
194 | * Return the base address of the current stack. |
194 | * The stack is assumed to be STACK_SIZE bytes long. |
195 | * The stack is assumed to be STACK_SIZE bytes long. |
195 | * The stack must start on page boundary. |
196 | * The stack must start on page boundary. |
196 | */ |
197 | */ |
197 | static inline __address get_stack_base(void) |
198 | static inline __address get_stack_base(void) |
198 | { |
199 | { |
199 | __address v; |
200 | __address v; |
200 | 201 | ||
201 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
202 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
202 | 203 | ||
203 | return v; |
204 | return v; |
204 | } |
205 | } |
205 | 206 | ||
206 | static inline __u64 rdtsc(void) |
207 | static inline __u64 rdtsc(void) |
207 | { |
208 | { |
208 | __u64 v; |
209 | __u64 v; |
209 | 210 | ||
210 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
211 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
211 | 212 | ||
212 | return v; |
213 | return v; |
213 | } |
214 | } |
214 | 215 | ||
215 | #endif |
216 | #endif |
216 | 217 |