WebSVN – HelenOS – Diff – /branches/network/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
    @brief  Exception handlers and exception initialization routines.
 */
 
#include <arch/exception.h>
#include <arch/debug_print/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/drivers/gxemul.h>
#include <arch/mm/page.h>
 
#define PREFETCH_OFFSET     0x8
#define BRANCH_OPCODE       0xea000000
#define LDR_OPCODE      0xe59ff000
#define VALID_BRANCH_MASK   0xff000000
#define EXC_VECTORS_SIZE    0x20
#define EXC_VECTORS     0x8
 
 
#define SAVE_REGS_TO_STACK          \
    asm("stmfd sp!, {r0-r12, sp, lr}");     \
    asm("mrs r14, spsr");           \
    asm("stmfd sp!, {r14}");
 
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, sp");          \
    asm("bl exc_dispatch");     
 
/**Loads registers from the stack and resets SPSR before exitting exception
 * handler.
 */
#define LOAD_REGS_FROM_STACK            \
    asm("ldmfd sp!, {r14}");        \
    asm("msr spsr, r14");           \
    asm("ldmfd sp!, {r0-r12, sp, pc}^");
   
/** General exception handler.
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 */
#define PROCESS_EXCEPTION(exception)        \
    SAVE_REGS_TO_STACK          \
    CALL_EXC_DISPATCH(exception)        \
    LOAD_REGS_FROM_STACK            
 
/** Updates specified exception vector to jump to given handler.
 * Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler (unsigned handler_addr, unsigned* vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
}
 
static void reset_exception_entry()
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
/** Low-level Software Interrupt Exception handler */
static void swi_exception_entry()
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
/** Low-level Undefined Instruction Exception handler */
static void undef_instr_exception_entry()
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
/** Low-level Fast Interrupt Exception handler */
static void fiq_exception_entry()
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
/** Low-level Prefetch Abort Exception handler */
static void prefetch_abort_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
/** Low-level Data Abort Exception handler */
static void data_abort_exception_entry()
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
 
/** Low-level Interrupt Exception handler */
static void irq_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_IRQ);
}
 
 
 
 
 
 
 
/** Interrupt Exception handler.
 * Determines the sources of interrupt, and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t* istate)
{
// TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar
// name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM
#if MACHINE == MACHINE_GXEMUL_TESTARM
    uint32_t sources = gxemul_irqc_get_sources();
    int i = 0;
    for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {
        if (sources & (1 << i)) {
            irq_t *irq = irq_dispatch_and_lock(i);
            if (irq) {
                /* The IRQ handler was found. */
                irq->handler(irq, irq->arg);
                spinlock_unlock(&irq->lock);
            } else {
                /* Spurious interrupt.*/
                dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);
            }
        }
    }
#endif
/* TODO remove after testing the above code
            noirq = 0;
            if (i == CONSOLE_IRQ) {
                char readchar = *(char*)0x10000000;
                if (readchar == 0) {
                    aux_puts("?");
                }
                else {
                    dprintf("%c", readchar);
                }
               
            }
            else if (i == TIMER_IRQ) {
                dprintf("\n.\n");
                //acknowledge
                *(uint32_t*)0x15000110 = 0;
            }
        }
    }
 
    if (noirq)
    aux_puts("IRQ exception without source\n");*/
}
 
/** Fills exception vectors with appropriate exception handlers.
*/
void install_exception_handlers(void)
{
    install_handler((unsigned)reset_exception_entry,
             (unsigned*)EXC_RESET_VEC);
   
    install_handler((unsigned)undef_instr_exception_entry,
             (unsigned*)EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned)swi_exception_entry,
             (unsigned*)EXC_SWI_VEC);
   
    install_handler((unsigned)prefetch_abort_exception_entry,
             (unsigned*)EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned)data_abort_exception_entry,
             (unsigned*)EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned)irq_exception_entry,  
             (unsigned*)EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
             (unsigned*)EXC_FIQ_VEC);
}
 
/** Activates using high exception vectors addresses. */
 static void high_vectors()
{
    uint32_t control_reg;
   
    asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
   
    //switch on the high vectors bit
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
 
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
 
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    /* TODO add next */
}
 
/* TODO change soon, temporary hack. */
void setup_exception_stacks()
{
    /* switch to particular mode and set "sp" there */
 
    uint32_t cspr = current_status_reg_read();
 
    /* IRQ stack */
    current_status_reg_control_write(
            (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE
    );
    asm("ldr sp, =irq_stack");
 
    /* abort stack */
    current_status_reg_control_write(
            (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE
    );
    asm("ldr sp, =abort_stack");
 
    /* TODO if you want to test other exceptions than IRQ,
    make stack analogous to irq_stack (in start.S),
    and then set stack pointer here */
 
    current_status_reg_control_write( cspr);
 
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/network/kernel/arch/arm32/src/exception.c @ 4718 – Rev 2274 → 2277

Rev 2274		Rev 2277
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	@brief Exception handlers and exception initialization routines.	33	@brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36	#include <arch/exception.h>	36	#include <arch/exception.h>
37	#include <arch/debug_print/print.h>	37	#include <arch/debug_print/print.h>
38	#include <arch/memstr.h>	38	#include <arch/memstr.h>
39	#include <arch/regutils.h>	39	#include <arch/regutils.h>
40	#include <interrupt.h>	40	#include <interrupt.h>
41	#include <arch/drivers/gxemul.h>	41	#include <arch/drivers/gxemul.h>
-		42	#include <arch/mm/page.h>
42		43
43	#define PREFETCH_OFFSET 0x8	44	#define PREFETCH_OFFSET 0x8
44	#define BRANCH_OPCODE 0xea000000	45	#define BRANCH_OPCODE 0xea000000
45	#define LDR_OPCODE 0xe59ff000	46	#define LDR_OPCODE 0xe59ff000
46	#define VALID_BRANCH_MASK 0xff000000	47	#define VALID_BRANCH_MASK 0xff000000
47	#define EXC_VECTORS_SIZE 0x20	48	#define EXC_VECTORS_SIZE 0x20
48	#define EXC_VECTORS 0x8	49	#define EXC_VECTORS 0x8
49		50
50		51
51	#define SAVE_REGS_TO_STACK \	52	#define SAVE_REGS_TO_STACK \
52	asm("stmfd sp!, {r0-r12, sp, lr}"); \	53	asm("stmfd sp!, {r0-r12, sp, lr}"); \
53	asm("mrs r14, spsr"); \	54	asm("mrs r14, spsr"); \
54	asm("stmfd sp!, {r14}");	55	asm("stmfd sp!, {r14}");
55		56
56	#define CALL_EXC_DISPATCH(exception) \	57	#define CALL_EXC_DISPATCH(exception) \
57	asm("mov r0, %0" : : "i" (exception)); \	58	asm("mov r0, %0" : : "i" (exception)); \
58	asm("mov r1, sp"); \	59	asm("mov r1, sp"); \
59	asm("bl exc_dispatch");	60	asm("bl exc_dispatch");
60		61
61	/**Loads registers from the stack and resets SPSR before exitting exception	62	/**Loads registers from the stack and resets SPSR before exitting exception
62	* handler.	63	* handler.
63	*/	64	*/
64	#define LOAD_REGS_FROM_STACK \	65	#define LOAD_REGS_FROM_STACK \
65	asm("ldmfd sp!, {r14}"); \	66	asm("ldmfd sp!, {r14}"); \
66	asm("msr spsr, r14"); \	67	asm("msr spsr, r14"); \
67	asm("ldmfd sp!, {r0-r12, sp, pc}^");	68	asm("ldmfd sp!, {r0-r12, sp, pc}^");
68		69
69	/** General exception handler.	70	/** General exception handler.
70	* Stores registers, dispatches the exception,	71	* Stores registers, dispatches the exception,
71	* and finally restores registers and returns from exception processing.	72	* and finally restores registers and returns from exception processing.
72	*/	73	*/
73	#define PROCESS_EXCEPTION(exception) \	74	#define PROCESS_EXCEPTION(exception) \
74	SAVE_REGS_TO_STACK \	75	SAVE_REGS_TO_STACK \
75	CALL_EXC_DISPATCH(exception) \	76	CALL_EXC_DISPATCH(exception) \
76	LOAD_REGS_FROM_STACK	77	LOAD_REGS_FROM_STACK
77		78
78	/** Updates specified exception vector to jump to given handler.	79	/** Updates specified exception vector to jump to given handler.
79	* Addresses of handlers are stored in memory following exception vectors.	80	* Addresses of handlers are stored in memory following exception vectors.
80	*/	81	*/
81	static void install_handler (unsigned handler_addr, unsigned* vector)	82	static void install_handler (unsigned handler_addr, unsigned* vector)
82	{	83	{
83	/* relative address (related to exc. vector) of the word	84	/* relative address (related to exc. vector) of the word
84	* where handler's address is stored	85	* where handler's address is stored
85	*/	86	*/
86	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;	87	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
87		88
88	/* make it LDR instruction and store at exception vector */	89	/* make it LDR instruction and store at exception vector */
89	*vector = handler_address_ptr \| LDR_OPCODE;	90	*vector = handler_address_ptr \| LDR_OPCODE;
90		91
91	/* store handler's address */	92	/* store handler's address */
92	*(vector + EXC_VECTORS) = handler_addr;	93	*(vector + EXC_VECTORS) = handler_addr;
93	}	94	}
94		95
95	static void reset_exception_entry()	96	static void reset_exception_entry()
96	{	97	{
97	PROCESS_EXCEPTION(EXC_RESET);	98	PROCESS_EXCEPTION(EXC_RESET);
98	}	99	}
99		100
100	/** Low-level Software Interrupt Exception handler */	101	/** Low-level Software Interrupt Exception handler */
101	static void swi_exception_entry()	102	static void swi_exception_entry()
102	{	103	{
103	PROCESS_EXCEPTION(EXC_SWI);	104	PROCESS_EXCEPTION(EXC_SWI);
104	}	105	}
105		106
106	/** Low-level Undefined Instruction Exception handler */	107	/** Low-level Undefined Instruction Exception handler */
107	static void undef_instr_exception_entry()	108	static void undef_instr_exception_entry()
108	{	109	{
109	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	110	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
110	}	111	}
111		112
112	/** Low-level Fast Interrupt Exception handler */	113	/** Low-level Fast Interrupt Exception handler */
113	static void fiq_exception_entry()	114	static void fiq_exception_entry()
114	{	115	{
115	PROCESS_EXCEPTION(EXC_FIQ);	116	PROCESS_EXCEPTION(EXC_FIQ);
116	}	117	}
117		118
118	/** Low-level Prefetch Abort Exception handler */	119	/** Low-level Prefetch Abort Exception handler */
119	static void prefetch_abort_exception_entry()	120	static void prefetch_abort_exception_entry()
120	{	121	{
121	asm("sub lr, lr, #4");	122	asm("sub lr, lr, #4");
122	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	123	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
123	}	124	}
124		125
125	/** Low-level Data Abort Exception handler */	126	/** Low-level Data Abort Exception handler */
126	static void data_abort_exception_entry()	127	static void data_abort_exception_entry()
127	{	128	{
128	asm("sub lr, lr, #8");	129	asm("sub lr, lr, #8");
129	PROCESS_EXCEPTION(EXC_DATA_ABORT);	130	PROCESS_EXCEPTION(EXC_DATA_ABORT);
130	}	131	}
131		132
132		133
133	/** Low-level Interrupt Exception handler */	134	/** Low-level Interrupt Exception handler */
134	static void irq_exception_entry()	135	static void irq_exception_entry()
135	{	136	{
136	asm("sub lr, lr, #4");	137	asm("sub lr, lr, #4");
137	PROCESS_EXCEPTION(EXC_IRQ);	138	PROCESS_EXCEPTION(EXC_IRQ);
138	}	139	}
139		140
140	static void prefetch_abort_exception(int exc_no, istate_t* istate)	-
141	{	-
142	//aux_puts("(PREFETCH\|DATA) ABORT exception caught, not processed.\n");	-
143	}	-
144		-
145		141
146	/** Interrupt Exception handler.	142	/** Interrupt Exception handler.
147	* Determines the sources of interrupt, and calls their handlers.	143	* Determines the sources of interrupt, and calls their handlers.
148	*/	144	*/
149	static void irq_exception(int exc_no, istate_t* istate)	145	static void irq_exception(int exc_no, istate_t* istate)
150	{	146	{
151	// TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar	147	// TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar
152	// name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM	148	// name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM
153	#if MACHINE == MACHINE_GXEMUL_TESTARM	149	#if MACHINE == MACHINE_GXEMUL_TESTARM
154	uint32_t sources = gxemul_irqc_get_sources();	150	uint32_t sources = gxemul_irqc_get_sources();
155	int i = 0;	151	int i = 0;
156	for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {	152	for (; i < GXEMUL_IRQC_MAX_IRQ; i++) {
157	if (sources & (1 << i)) {	153	if (sources & (1 << i)) {
158	irq_t *irq = irq_dispatch_and_lock(i);	154	irq_t *irq = irq_dispatch_and_lock(i);
159	if (irq) {	155	if (irq) {
160	/* The IRQ handler was found. */	156	/* The IRQ handler was found. */
161	irq->handler(irq, irq->arg);	157	irq->handler(irq, irq->arg);
162	spinlock_unlock(&irq->lock);	158	spinlock_unlock(&irq->lock);
163	} else {	159	} else {
164	/* Spurious interrupt.*/	160	/* Spurious interrupt.*/
165	dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);	161	dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i);
166	}	162	}
167	}	163	}
168	}	164	}
169	#endif	165	#endif
170	/* TODO remove after testing the above code	166	/* TODO remove after testing the above code
171	noirq = 0;	167	noirq = 0;
172	if (i == CONSOLE_IRQ) {	168	if (i == CONSOLE_IRQ) {
173	char readchar = (char)0x10000000;	169	char readchar = (char)0x10000000;
174	if (readchar == 0) {	170	if (readchar == 0) {
175	aux_puts("?");	171	aux_puts("?");
176	}	172	}
177	else {	173	else {
178	dprintf("%c", readchar);	174	dprintf("%c", readchar);
179	}	175	}
180		176
181	}	177	}
182	else if (i == TIMER_IRQ) {	178	else if (i == TIMER_IRQ) {
183	dprintf("\n.\n");	179	dprintf("\n.\n");
184	//acknowledge	180	//acknowledge
185	(uint32_t)0x15000110 = 0;	181	(uint32_t)0x15000110 = 0;
186	}	182	}
187	}	183	}
188	}	184	}
189		185
190	if (noirq)	186	if (noirq)
191	aux_puts("IRQ exception without source\n");*/	187	aux_puts("IRQ exception without source\n");*/
192	}	188	}
193		189
194	/** Fills exception vectors with appropriate exception handlers.	190	/** Fills exception vectors with appropriate exception handlers.
195	*/	191	*/
196	void install_exception_handlers(void)	192	void install_exception_handlers(void)
197	{	193	{
198	install_handler((unsigned)reset_exception_entry,	194	install_handler((unsigned)reset_exception_entry,
199	(unsigned*)EXC_RESET_VEC);	195	(unsigned*)EXC_RESET_VEC);
200		196
201	install_handler((unsigned)undef_instr_exception_entry,	197	install_handler((unsigned)undef_instr_exception_entry,
202	(unsigned*)EXC_UNDEF_INSTR_VEC);	198	(unsigned*)EXC_UNDEF_INSTR_VEC);
203		199
204	install_handler((unsigned)swi_exception_entry,	200	install_handler((unsigned)swi_exception_entry,
205	(unsigned*)EXC_SWI_VEC);	201	(unsigned*)EXC_SWI_VEC);
206		202
207	install_handler((unsigned)prefetch_abort_exception_entry,	203	install_handler((unsigned)prefetch_abort_exception_entry,
208	(unsigned*)EXC_PREFETCH_ABORT_VEC);	204	(unsigned*)EXC_PREFETCH_ABORT_VEC);
209		205
210	install_handler((unsigned)data_abort_exception_entry,	206	install_handler((unsigned)data_abort_exception_entry,
211	(unsigned*)EXC_DATA_ABORT_VEC);	207	(unsigned*)EXC_DATA_ABORT_VEC);
212		208
213	install_handler((unsigned)irq_exception_entry,	209	install_handler((unsigned)irq_exception_entry,
214	(unsigned*)EXC_IRQ_VEC);	210	(unsigned*)EXC_IRQ_VEC);
215		211
216	install_handler((unsigned)fiq_exception_entry,	212	install_handler((unsigned)fiq_exception_entry,
217	(unsigned*)EXC_FIQ_VEC);	213	(unsigned*)EXC_FIQ_VEC);
218	}	214	}
219		215
220	/** Activates using high exception vectors addresses. */	216	/** Activates using high exception vectors addresses. */
221	static void high_vectors()	217	static void high_vectors()
222	{	218	{
223	uint32_t control_reg;	219	uint32_t control_reg;
224		220
225	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));	221	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
226		222
227	//switch on the high vectors bit	223	//switch on the high vectors bit
228	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	224	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
229		225
230	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	226	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
231	}	227	}
232		228
233		229
234	/** Initializes exception handling.	230	/** Initializes exception handling.
235	*	231	*
236	* Installs low-level exception handlers and then registers	232	* Installs low-level exception handlers and then registers
237	* exceptions and their handlers to kernel exception dispatcher.	233	* exceptions and their handlers to kernel exception dispatcher.
238	*/	234	*/
239	void exception_init(void)	235	void exception_init(void)
240	{	236	{
241	#ifdef HIGH_EXCEPTION_VECTORS	237	#ifdef HIGH_EXCEPTION_VECTORS
242	high_vectors();	238	high_vectors();
243	#endif	239	#endif
244		240
245	install_exception_handlers();	241	install_exception_handlers();
246		242
247	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	243	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
248	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort_exception);	244	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
249	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) prefetch_abort_exception);	245	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
250	/* TODO add next */	246	/* TODO add next */
251	}	247	}
252		248
253	/* TODO change soon, temporary hack. */	249	/* TODO change soon, temporary hack. */
254	void setup_exception_stacks()	250	void setup_exception_stacks()
255	{	251	{
256	/* switch to particular mode and set "sp" there */	252	/* switch to particular mode and set "sp" there */
257		253
258	uint32_t cspr = current_status_reg_read();	254	uint32_t cspr = current_status_reg_read();
259		255
260	/* IRQ stack */	256	/* IRQ stack */
261	current_status_reg_control_write(	257	current_status_reg_control_write(
262	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE	258	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE
263	);	259	);
264	asm("ldr sp, =irq_stack");	260	asm("ldr sp, =irq_stack");
265		261
266	/* abort stack */	262	/* abort stack */
267	current_status_reg_control_write(	263	current_status_reg_control_write(
268	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE	264	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE
269	);	265	);
270	asm("ldr sp, =abort_stack");	266	asm("ldr sp, =abort_stack");
271		267
272	/* TODO if you want to test other exceptions than IRQ,	268	/* TODO if you want to test other exceptions than IRQ,
273	make stack analogous to irq_stack (in start.S),	269	make stack analogous to irq_stack (in start.S),
274	and then set stack pointer here */	270	and then set stack pointer here */
275		271
276	current_status_reg_control_write( cspr);	272	current_status_reg_control_write( cspr);
277		273
278	}	274	}
279		275
280	/** @}	276	/** @}
281	*/	277	*/
282		278