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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Ondrej Palkovsky |
2 | * Copyright (C) 2006 Ondrej Palkovsky |
- | 3 | * Copyright (C) 2006 Jakub Jermar |
|
3 | * All rights reserved. |
4 | * All rights reserved. |
4 | * |
5 | * |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
7 | * are met: |
8 | * are met: |
8 | * |
9 | * |
9 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
16 | * |
17 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
28 | */ |
28 | 29 | ||
29 | /** @addtogroup genericipc |
30 | /** @addtogroup genericipc |
30 | * @{ |
31 | * @{ |
31 | */ |
32 | */ |
32 | /** |
33 | /** |
33 | * @file |
34 | * @file |
34 | * @brief IRQ notification framework. |
35 | * @brief IRQ notification framework. |
35 | * |
36 | * |
36 | * This framework allows applications to register to receive a notification |
37 | * This framework allows applications to register to receive a notification |
37 | * when interrupt is detected. The application may provide a simple 'top-half' |
38 | * when interrupt is detected. The application may provide a simple 'top-half' |
38 | * handler as part of its registration, which can perform simple operations |
39 | * handler as part of its registration, which can perform simple operations |
39 | * (read/write port/memory, add information to notification ipc message). |
40 | * (read/write port/memory, add information to notification ipc message). |
40 | * |
41 | * |
41 | * The structure of a notification message is as follows: |
42 | * The structure of a notification message is as follows: |
42 | * - METHOD: interrupt number |
43 | * - METHOD: method as registered by the SYS_IPC_REGISTER_IRQ syscall |
43 | * - ARG1: payload modified by a 'top-half' handler |
44 | * - ARG1: payload modified by a 'top-half' handler |
44 | * - ARG2: payload |
45 | * - ARG2: payload modified by a 'top-half' handler |
45 | * - ARG3: payload |
46 | * - ARG3: payload modified by a 'top-half' handler |
46 | * - in_phone_hash: interrupt counter (may be needed to assure correct order |
47 | * - in_phone_hash: interrupt counter (may be needed to assure correct order |
47 | * in multithreaded drivers) |
48 | * in multithreaded drivers) |
48 | */ |
49 | */ |
49 | 50 | ||
50 | #include <arch.h> |
51 | #include <arch.h> |
51 | #include <mm/slab.h> |
52 | #include <mm/slab.h> |
52 | #include <errno.h> |
53 | #include <errno.h> |
- | 54 | #include <ddi/irq.h> |
|
53 | #include <ipc/ipc.h> |
55 | #include <ipc/ipc.h> |
54 | #include <ipc/irq.h> |
56 | #include <ipc/irq.h> |
55 | #include <atomic.h> |
- | |
56 | #include <syscall/copy.h> |
57 | #include <syscall/copy.h> |
57 | #include <console/console.h> |
58 | #include <console/console.h> |
58 | #include <print.h> |
59 | #include <print.h> |
59 | 60 | ||
60 | typedef struct { |
- | |
61 | SPINLOCK_DECLARE(lock); |
- | |
62 | answerbox_t *box; |
- | |
63 | irq_code_t *code; |
- | |
64 | atomic_t counter; |
61 | /** Execute code associated with IRQ notification. |
65 | } ipc_irq_t; |
- | |
66 | 62 | * |
|
67 | - | ||
68 | static ipc_irq_t *irq_conns = NULL; |
63 | * @param call Notification call. |
69 | static int irq_conns_size; |
64 | * @param code Top-half pseudocode. |
70 | - | ||
71 | 65 | */ |
|
72 | /* Execute code associated with IRQ notification */ |
- | |
73 | static void code_execute(call_t *call, irq_code_t *code) |
66 | static void code_execute(call_t *call, irq_code_t *code) |
74 | { |
67 | { |
75 | int i; |
68 | int i; |
76 | unative_t dstval = 0; |
69 | unative_t dstval = 0; |
77 | 70 | ||
78 | if (!code) |
71 | if (!code) |
79 | return; |
72 | return; |
80 | 73 | ||
81 | for (i=0; i < code->cmdcount;i++) { |
74 | for (i=0; i < code->cmdcount;i++) { |
82 | switch (code->cmds[i].cmd) { |
75 | switch (code->cmds[i].cmd) { |
83 | case CMD_MEM_READ_1: |
76 | case CMD_MEM_READ_1: |
84 | dstval = *((uint8_t *)code->cmds[i].addr); |
77 | dstval = *((uint8_t *)code->cmds[i].addr); |
85 | break; |
78 | break; |
86 | case CMD_MEM_READ_2: |
79 | case CMD_MEM_READ_2: |
87 | dstval = *((uint16_t *)code->cmds[i].addr); |
80 | dstval = *((uint16_t *)code->cmds[i].addr); |
88 | break; |
81 | break; |
89 | case CMD_MEM_READ_4: |
82 | case CMD_MEM_READ_4: |
90 | dstval = *((uint32_t *)code->cmds[i].addr); |
83 | dstval = *((uint32_t *)code->cmds[i].addr); |
91 | break; |
84 | break; |
92 | case CMD_MEM_READ_8: |
85 | case CMD_MEM_READ_8: |
93 | dstval = *((uint64_t *)code->cmds[i].addr); |
86 | dstval = *((uint64_t *)code->cmds[i].addr); |
94 | break; |
87 | break; |
95 | case CMD_MEM_WRITE_1: |
88 | case CMD_MEM_WRITE_1: |
96 | *((uint8_t *)code->cmds[i].addr) = code->cmds[i].value; |
89 | *((uint8_t *)code->cmds[i].addr) = code->cmds[i].value; |
97 | break; |
90 | break; |
98 | case CMD_MEM_WRITE_2: |
91 | case CMD_MEM_WRITE_2: |
99 | *((uint16_t *)code->cmds[i].addr) = code->cmds[i].value; |
92 | *((uint16_t *)code->cmds[i].addr) = code->cmds[i].value; |
100 | break; |
93 | break; |
101 | case CMD_MEM_WRITE_4: |
94 | case CMD_MEM_WRITE_4: |
102 | *((uint32_t *)code->cmds[i].addr) = code->cmds[i].value; |
95 | *((uint32_t *)code->cmds[i].addr) = code->cmds[i].value; |
103 | break; |
96 | break; |
104 | case CMD_MEM_WRITE_8: |
97 | case CMD_MEM_WRITE_8: |
105 | *((uint64_t *)code->cmds[i].addr) = code->cmds[i].value; |
98 | *((uint64_t *)code->cmds[i].addr) = code->cmds[i].value; |
106 | break; |
99 | break; |
107 | #if defined(ia32) || defined(amd64) |
100 | #if defined(ia32) || defined(amd64) |
108 | case CMD_PORT_READ_1: |
101 | case CMD_PORT_READ_1: |
109 | dstval = inb((long)code->cmds[i].addr); |
102 | dstval = inb((long)code->cmds[i].addr); |
110 | break; |
103 | break; |
111 | case CMD_PORT_WRITE_1: |
104 | case CMD_PORT_WRITE_1: |
112 | outb((long)code->cmds[i].addr, code->cmds[i].value); |
105 | outb((long)code->cmds[i].addr, code->cmds[i].value); |
113 | break; |
106 | break; |
114 | #endif |
107 | #endif |
115 | #if defined(ia64) |
108 | #if defined(ia64) |
116 | case CMD_IA64_GETCHAR: |
109 | case CMD_IA64_GETCHAR: |
117 | dstval = _getc(&ski_uconsole); |
110 | dstval = _getc(&ski_uconsole); |
118 | break; |
111 | break; |
119 | #endif |
112 | #endif |
120 | #if defined(ppc32) |
113 | #if defined(ppc32) |
121 | case CMD_PPC32_GETCHAR: |
114 | case CMD_PPC32_GETCHAR: |
122 | dstval = cuda_get_scancode(); |
115 | dstval = cuda_get_scancode(); |
123 | break; |
116 | break; |
124 | #endif |
117 | #endif |
125 | default: |
118 | default: |
126 | break; |
119 | break; |
127 | } |
120 | } |
128 | if (code->cmds[i].dstarg && code->cmds[i].dstarg < 4) { |
121 | if (code->cmds[i].dstarg && code->cmds[i].dstarg < 4) { |
129 | call->data.args[code->cmds[i].dstarg] = dstval; |
122 | call->data.args[code->cmds[i].dstarg] = dstval; |
130 | } |
123 | } |
131 | } |
124 | } |
132 | } |
125 | } |
133 | 126 | ||
134 | static void code_free(irq_code_t *code) |
127 | static void code_free(irq_code_t *code) |
135 | { |
128 | { |
136 | if (code) { |
129 | if (code) { |
137 | free(code->cmds); |
130 | free(code->cmds); |
138 | free(code); |
131 | free(code); |
139 | } |
132 | } |
140 | } |
133 | } |
141 | 134 | ||
142 | static irq_code_t * code_from_uspace(irq_code_t *ucode) |
135 | static irq_code_t * code_from_uspace(irq_code_t *ucode) |
143 | { |
136 | { |
144 | irq_code_t *code; |
137 | irq_code_t *code; |
145 | irq_cmd_t *ucmds; |
138 | irq_cmd_t *ucmds; |
146 | int rc; |
139 | int rc; |
147 | 140 | ||
148 | code = malloc(sizeof(*code), 0); |
141 | code = malloc(sizeof(*code), 0); |
149 | rc = copy_from_uspace(code, ucode, sizeof(*code)); |
142 | rc = copy_from_uspace(code, ucode, sizeof(*code)); |
150 | if (rc != 0) { |
143 | if (rc != 0) { |
151 | free(code); |
144 | free(code); |
152 | return NULL; |
145 | return NULL; |
153 | } |
146 | } |
154 | 147 | ||
155 | if (code->cmdcount > IRQ_MAX_PROG_SIZE) { |
148 | if (code->cmdcount > IRQ_MAX_PROG_SIZE) { |
156 | free(code); |
149 | free(code); |
157 | return NULL; |
150 | return NULL; |
158 | } |
151 | } |
159 | ucmds = code->cmds; |
152 | ucmds = code->cmds; |
160 | code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0); |
153 | code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0); |
161 | rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount)); |
154 | rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount)); |
162 | if (rc != 0) { |
155 | if (rc != 0) { |
163 | free(code->cmds); |
156 | free(code->cmds); |
164 | free(code); |
157 | free(code); |
165 | return NULL; |
158 | return NULL; |
166 | } |
159 | } |
167 | 160 | ||
168 | return code; |
161 | return code; |
169 | } |
162 | } |
170 | 163 | ||
171 | /** Unregister task from irq */ |
164 | /** Unregister task from IRQ notification. |
- | 165 | * |
|
- | 166 | * @param box Answerbox associated with the notification. |
|
- | 167 | * @param inr IRQ numbe. |
|
- | 168 | * @param devno Device number. |
|
- | 169 | */ |
|
172 | void ipc_irq_unregister(answerbox_t *box, int irq) |
170 | void ipc_irq_unregister(answerbox_t *box, inr_t inr, devno_t devno) |
173 | { |
171 | { |
174 | ipl_t ipl; |
172 | ipl_t ipl; |
175 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL; |
173 | irq_t *irq; |
176 | 174 | ||
177 | ipl = interrupts_disable(); |
175 | ipl = interrupts_disable(); |
178 | spinlock_lock(&irq_conns[mq].lock); |
176 | irq = irq_find_and_lock(inr, devno); |
- | 177 | if (irq) { |
|
179 | if (irq_conns[mq].box == box) { |
178 | if (irq->notif_cfg.answerbox == box) { |
- | 179 | code_free(irq->notif_cfg.code); |
|
180 | irq_conns[mq].box = NULL; |
180 | irq->notif_cfg.code = NULL; |
- | 181 | irq->notif_cfg.answerbox = NULL; |
|
181 | code_free(irq_conns[mq].code); |
182 | irq->notif_cfg.method = 0; |
182 | irq_conns[mq].code = NULL; |
183 | irq->notif_cfg.counter = 0; |
- | 184 | spinlock_unlock(&irq->lock); |
|
- | 185 | } |
|
183 | } |
186 | } |
184 | - | ||
185 | spinlock_unlock(&irq_conns[mq].lock); |
- | |
186 | interrupts_restore(ipl); |
187 | interrupts_restore(ipl); |
187 | } |
188 | } |
188 | 189 | ||
189 | /** Register an answerbox as a receiving end of interrupts notifications */ |
190 | /** Register an answerbox as a receiving end for IRQ notifications. |
- | 191 | * |
|
- | 192 | * @param box Receiving answerbox. |
|
- | 193 | * @param inr IRQ number. |
|
- | 194 | * @param devno Device number. |
|
- | 195 | * @param method Method to be associated with the notification. |
|
- | 196 | * @param ucode Uspace pointer to top-half pseudocode. |
|
- | 197 | * |
|
- | 198 | * @return EBADMEM, ENOENT or EEXISTS on failure or 0 on success. |
|
- | 199 | */ |
|
- | 200 | int |
|
190 | int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode) |
201 | ipc_irq_register(answerbox_t *box, inr_t inr, devno_t devno, unative_t method, irq_code_t *ucode) |
191 | { |
202 | { |
192 | ipl_t ipl; |
203 | ipl_t ipl; |
193 | irq_code_t *code; |
204 | irq_code_t *code; |
194 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL; |
- | |
195 | - | ||
196 | ASSERT(irq_conns); |
205 | irq_t *irq; |
197 | 206 | ||
198 | if (ucode) { |
207 | if (ucode) { |
199 | code = code_from_uspace(ucode); |
208 | code = code_from_uspace(ucode); |
200 | if (!code) |
209 | if (!code) |
201 | return EBADMEM; |
210 | return EBADMEM; |
202 | } else |
211 | } else |
203 | code = NULL; |
212 | code = NULL; |
204 | 213 | ||
205 | ipl = interrupts_disable(); |
214 | ipl = interrupts_disable(); |
206 | spinlock_lock(&irq_conns[mq].lock); |
215 | irq = irq_find_and_lock(inr, devno); |
- | 216 | if (!irq) { |
|
- | 217 | interrupts_restore(ipl); |
|
- | 218 | code_free(code); |
|
- | 219 | return ENOENT; |
|
- | 220 | } |
|
207 | 221 | ||
208 | if (irq_conns[mq].box) { |
222 | if (irq->notif_cfg.answerbox) { |
209 | spinlock_unlock(&irq_conns[mq].lock); |
223 | spinlock_unlock(&irq->lock); |
210 | interrupts_restore(ipl); |
224 | interrupts_restore(ipl); |
211 | code_free(code); |
225 | code_free(code); |
212 | return EEXISTS; |
226 | return EEXISTS; |
213 | } |
227 | } |
- | 228 | ||
214 | irq_conns[mq].box = box; |
229 | irq->notif_cfg.answerbox = box; |
- | 230 | irq->notif_cfg.method = method; |
|
215 | irq_conns[mq].code = code; |
231 | irq->notif_cfg.code = code; |
216 | atomic_set(&irq_conns[mq].counter, 0); |
232 | irq->notif_cfg.counter = 0; |
217 | spinlock_unlock(&irq_conns[mq].lock); |
233 | spinlock_unlock(&irq->lock); |
218 | interrupts_restore(ipl); |
234 | interrupts_restore(ipl); |
219 | 235 | ||
220 | return 0; |
236 | return 0; |
221 | } |
237 | } |
222 | 238 | ||
223 | /** Add call to proper answerbox queue |
239 | /** Add call to proper answerbox queue. |
- | 240 | * |
|
- | 241 | * Assume irq->lock is locked. |
|
224 | * |
242 | * |
225 | * Assume irq_conns[mq].lock is locked */ |
243 | */ |
226 | static void send_call(int mq, call_t *call) |
244 | static void send_call(irq_t *irq, call_t *call) |
227 | { |
245 | { |
228 | spinlock_lock(&irq_conns[mq].box->irq_lock); |
246 | spinlock_lock(&irq->notif_cfg.answerbox->irq_lock); |
229 | list_append(&call->link, &irq_conns[mq].box->irq_notifs); |
247 | list_append(&call->link, &irq->notif_cfg.answerbox->irq_notifs); |
230 | spinlock_unlock(&irq_conns[mq].box->irq_lock); |
248 | spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock); |
231 | 249 | ||
232 | waitq_wakeup(&irq_conns[mq].box->wq, 0); |
250 | waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST); |
233 | } |
251 | } |
234 | 252 | ||
235 | /** Send notification message |
253 | /** Send notification message |
236 | * |
254 | * |
237 | */ |
255 | */ |
238 | void ipc_irq_send_msg(int irq, unative_t a1, unative_t a2, unative_t a3) |
256 | void ipc_irq_send_msg(irq_t *irq, unative_t a1, unative_t a2, unative_t a3) |
239 | { |
257 | { |
240 | call_t *call; |
258 | call_t *call; |
241 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL; |
- | |
242 | 259 | ||
243 | spinlock_lock(&irq_conns[mq].lock); |
260 | spinlock_lock(&irq->lock); |
244 | 261 | ||
245 | if (irq_conns[mq].box) { |
262 | if (irq->notif_cfg.answerbox) { |
246 | call = ipc_call_alloc(FRAME_ATOMIC); |
263 | call = ipc_call_alloc(FRAME_ATOMIC); |
247 | if (!call) { |
264 | if (!call) { |
248 | spinlock_unlock(&irq_conns[mq].lock); |
265 | spinlock_unlock(&irq->lock); |
249 | return; |
266 | return; |
250 | } |
267 | } |
251 | call->flags |= IPC_CALL_NOTIF; |
268 | call->flags |= IPC_CALL_NOTIF; |
252 | IPC_SET_METHOD(call->data, irq); |
269 | IPC_SET_METHOD(call->data, irq->notif_cfg.method); |
253 | IPC_SET_ARG1(call->data, a1); |
270 | IPC_SET_ARG1(call->data, a1); |
254 | IPC_SET_ARG2(call->data, a2); |
271 | IPC_SET_ARG2(call->data, a2); |
255 | IPC_SET_ARG3(call->data, a3); |
272 | IPC_SET_ARG3(call->data, a3); |
256 | /* Put a counter to the message */ |
273 | /* Put a counter to the message */ |
257 | call->private = atomic_preinc(&irq_conns[mq].counter); |
274 | call->private = ++irq->notif_cfg.counter; |
258 | 275 | ||
259 | send_call(mq, call); |
276 | send_call(irq, call); |
260 | } |
277 | } |
261 | spinlock_unlock(&irq_conns[mq].lock); |
278 | spinlock_unlock(&irq->lock); |
262 | } |
279 | } |
263 | 280 | ||
264 | /** Notify task that an irq had occurred. |
281 | /** Notify task that an irq had occurred. |
265 | * |
282 | * |
266 | * We expect interrupts to be disabled |
283 | * We expect interrupts to be disabled and the irq->lock already held. |
267 | */ |
284 | */ |
268 | void ipc_irq_send_notif(int irq) |
285 | void ipc_irq_send_notif(irq_t *irq) |
269 | { |
286 | { |
270 | call_t *call; |
287 | call_t *call; |
271 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL; |
- | |
272 | 288 | ||
273 | ASSERT(irq_conns); |
289 | ASSERT(irq); |
274 | spinlock_lock(&irq_conns[mq].lock); |
- | |
275 | 290 | ||
276 | if (irq_conns[mq].box) { |
291 | if (irq->notif_cfg.answerbox) { |
277 | call = ipc_call_alloc(FRAME_ATOMIC); |
292 | call = ipc_call_alloc(FRAME_ATOMIC); |
278 | if (!call) { |
293 | if (!call) { |
279 | spinlock_unlock(&irq_conns[mq].lock); |
- | |
280 | return; |
294 | return; |
281 | } |
295 | } |
282 | call->flags |= IPC_CALL_NOTIF; |
296 | call->flags |= IPC_CALL_NOTIF; |
283 | /* Put a counter to the message */ |
297 | /* Put a counter to the message */ |
284 | call->private = atomic_preinc(&irq_conns[mq].counter); |
298 | call->private = ++irq->notif_cfg.counter; |
285 | /* Set up args */ |
299 | /* Set up args */ |
286 | IPC_SET_METHOD(call->data, irq); |
300 | IPC_SET_METHOD(call->data, irq->notif_cfg.method); |
287 | 301 | ||
288 | /* Execute code to handle irq */ |
302 | /* Execute code to handle irq */ |
289 | code_execute(call, irq_conns[mq].code); |
303 | code_execute(call, irq->notif_cfg.code); |
290 | 304 | ||
291 | send_call(mq, call); |
305 | send_call(irq, call); |
292 | } |
306 | } |
293 | - | ||
294 | spinlock_unlock(&irq_conns[mq].lock); |
- | |
295 | } |
307 | } |
296 | 308 | ||
297 | - | ||
298 | /** Initialize table of interrupt handlers |
309 | /** Disconnect all IRQ notifications from an answerbox. |
299 | * |
310 | * |
300 | * @param irqcount Count of required hardware IRQs to be supported |
- | |
301 | */ |
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302 | void ipc_irq_make_table(int irqcount) |
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303 | { |
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304 | int i; |
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305 | - | ||
306 | irqcount += IPC_IRQ_RESERVED_VIRTUAL; |
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307 | - | ||
308 | irq_conns_size = irqcount; |
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309 | irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0); |
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310 | for (i=0; i < irqcount; i++) { |
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311 | spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock"); |
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312 | irq_conns[i].box = NULL; |
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313 | irq_conns[i].code = NULL; |
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314 | } |
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315 | } |
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316 | - | ||
317 | /** Disconnect all irq's notifications |
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318 | * |
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319 | * @todo It may be better to do some linked list, so that |
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320 | * we wouldn't need to go through whole array every cleanup |
311 | * @param box Answerbox for which we want to carry out the cleanup. |
321 | */ |
312 | */ |
322 | void ipc_irq_cleanup(answerbox_t *box) |
313 | void ipc_irq_cleanup(answerbox_t *box) |
323 | { |
314 | { |
324 | int i; |
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325 | ipl_t ipl; |
315 | /* TODO */ |
326 | - | ||
327 | for (i=0; i < irq_conns_size; i++) { |
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328 | ipl = interrupts_disable(); |
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329 | spinlock_lock(&irq_conns[i].lock); |
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330 | if (irq_conns[i].box == box) |
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331 | irq_conns[i].box = NULL; |
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332 | spinlock_unlock(&irq_conns[i].lock); |
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333 | interrupts_restore(ipl); |
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334 | } |
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335 | } |
316 | } |
336 | 317 | ||
337 | /** @} |
318 | /** @} |
338 | */ |
319 | */ |
339 | 320 |