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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64interrupt |
29 | /** @addtogroup sparc64interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/interrupt.h> |
35 | #include <arch/interrupt.h> |
36 | #include <arch/trap/interrupt.h> |
36 | #include <arch/trap/interrupt.h> |
37 | #include <interrupt.h> |
37 | #include <interrupt.h> |
38 | #include <arch/drivers/fhc.h> |
38 | #include <arch/drivers/fhc.h> |
39 | #include <typedefs.h> |
39 | #include <typedefs.h> |
40 | #include <arch/types.h> |
40 | #include <arch/types.h> |
41 | #include <debug.h> |
41 | #include <debug.h> |
42 | #include <ipc/sysipc.h> |
42 | #include <ipc/sysipc.h> |
43 | #include <arch/asm.h> |
43 | #include <arch/asm.h> |
44 | #include <arch/barrier.h> |
44 | #include <arch/barrier.h> |
45 | 45 | ||
46 | #include <genarch/kbd/z8530.h> |
46 | #include <genarch/kbd/z8530.h> |
47 | 47 | ||
48 | /** Register Interrupt Level Handler. |
48 | /** Register Interrupt Level Handler. |
49 | * |
49 | * |
50 | * @param n Interrupt Level (1 - 15). |
50 | * @param n Interrupt Level (1 - 15). |
51 | * @param name Short descriptive string. |
51 | * @param name Short descriptive string. |
52 | * @param f Handler. |
52 | * @param f Handler. |
53 | */ |
53 | */ |
54 | void interrupt_register(int n, const char *name, iroutine f) |
54 | void interrupt_register(int n, const char *name, iroutine f) |
55 | { |
55 | { |
56 | ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS); |
56 | ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS); |
57 | 57 | ||
58 | exc_register(n - 1, name, f); |
58 | exc_register(n - 1, name, f); |
59 | } |
59 | } |
60 | 60 | ||
61 | /* Reregister irq to be IPC-ready */ |
61 | /* Reregister irq to be IPC-ready */ |
62 | void irq_ipc_bind_arch(unative_t irq) |
62 | void irq_ipc_bind_arch(unative_t irq) |
63 | { |
63 | { |
64 | panic("not implemented\n"); |
- | |
65 | /* TODO */ |
64 | /* TODO */ |
66 | } |
65 | } |
67 | 66 | ||
68 | void interrupt(int n, istate_t *istate) |
67 | void interrupt(int n, istate_t *istate) |
69 | { |
68 | { |
70 | uint64_t intrcv; |
69 | uint64_t intrcv; |
71 | uint64_t data0; |
70 | uint64_t data0; |
72 | 71 | ||
73 | intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); |
72 | intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); |
74 | data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0); |
73 | data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0); |
75 | 74 | ||
76 | switch (data0) { |
75 | switch (data0) { |
77 | #ifdef CONFIG_Z8530 |
76 | #ifdef CONFIG_Z8530 |
78 | case Z8530_INTRCV_DATA0: |
77 | case Z8530_INTRCV_DATA0: |
79 | /* |
78 | /* |
80 | * So far, we know we got this interrupt through the FHC. |
79 | * So far, we know we got this interrupt through the FHC. |
81 | * Since we don't have enough information about the FHC and |
80 | * Since we don't have enough information about the FHC and |
82 | * because the interrupt looks like level sensitive, |
81 | * because the interrupt looks like level sensitive, |
83 | * we cannot handle it by scheduling one of the level |
82 | * we cannot handle it by scheduling one of the level |
84 | * interrupt traps. Call the interrupt handler directly. |
83 | * interrupt traps. Call the interrupt handler directly. |
85 | */ |
84 | */ |
86 | fhc_uart_reset(); |
85 | fhc_uart_reset(); |
87 | z8530_interrupt(); |
86 | z8530_interrupt(); |
88 | break; |
87 | break; |
89 | #endif |
88 | #endif |
90 | } |
89 | } |
91 | 90 | ||
92 | membar(); |
91 | membar(); |
93 | asi_u64_write(ASI_INTR_RECEIVE, 0, 0); |
92 | asi_u64_write(ASI_INTR_RECEIVE, 0, 0); |
94 | } |
93 | } |
95 | 94 | ||
96 | /** @} |
95 | /** @} |
97 | */ |
96 | */ |
98 | 97 |