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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
30 | #include <mm/tlb.h> |
30 | #include <mm/tlb.h> |
31 | #include <arch/mm/frame.h> |
31 | #include <arch/mm/frame.h> |
32 | #include <arch/mm/page.h> |
32 | #include <arch/mm/page.h> |
33 | #include <arch/mm/mmu.h> |
33 | #include <arch/mm/mmu.h> |
34 | #include <mm/asid.h> |
34 | #include <mm/asid.h> |
35 | #include <print.h> |
35 | #include <print.h> |
36 | #include <arch/types.h> |
36 | #include <arch/types.h> |
37 | #include <typedefs.h> |
37 | #include <typedefs.h> |
38 | #include <config.h> |
38 | #include <config.h> |
39 | #include <arch/trap/trap.h> |
39 | #include <arch/trap/trap.h> |
40 | #include <panic.h> |
40 | #include <panic.h> |
41 | #include <arch/asm.h> |
41 | #include <arch/asm.h> |
42 | #include <symtab.h> |
42 | #include <symtab.h> |
- | 43 | ||
43 | #include <arch/drivers/fb.h> |
44 | #include <arch/drivers/fb.h> |
- | 45 | #include <arch/drivers/keyboard.h> |
|
44 | 46 | ||
45 | char *context_encoding[] = { |
47 | char *context_encoding[] = { |
46 | "Primary", |
48 | "Primary", |
47 | "Secondary", |
49 | "Secondary", |
48 | "Nucleus", |
50 | "Nucleus", |
49 | "Reserved" |
51 | "Reserved" |
50 | }; |
52 | }; |
51 | 53 | ||
52 | /** Initialize ITLB and DTLB. |
54 | /** Initialize ITLB and DTLB. |
53 | * |
55 | * |
54 | * The goal of this function is to disable MMU |
56 | * The goal of this function is to disable MMU |
55 | * so that both TLBs can be purged and new |
57 | * so that both TLBs can be purged and new |
56 | * kernel 4M locked entry can be installed. |
58 | * kernel 4M locked entry can be installed. |
57 | * After TLB is initialized, MMU is enabled |
59 | * After TLB is initialized, MMU is enabled |
58 | * again. |
60 | * again. |
59 | * |
61 | * |
60 | * Switching MMU off imposes the requirement for |
62 | * Switching MMU off imposes the requirement for |
61 | * the kernel to run in identity mapped environment. |
63 | * the kernel to run in identity mapped environment. |
62 | */ |
64 | */ |
63 | void tlb_arch_init(void) |
65 | void tlb_arch_init(void) |
64 | { |
66 | { |
65 | tlb_tag_access_reg_t tag; |
67 | tlb_tag_access_reg_t tag; |
66 | tlb_data_t data; |
68 | tlb_data_t data; |
67 | frame_address_t fr; |
69 | frame_address_t fr; |
68 | page_address_t pg; |
70 | page_address_t pg; |
69 | 71 | ||
70 | fr.address = config.base; |
72 | fr.address = config.base; |
71 | pg.address = config.base; |
73 | pg.address = config.base; |
72 | 74 | ||
73 | immu_disable(); |
75 | immu_disable(); |
74 | dmmu_disable(); |
76 | dmmu_disable(); |
75 | 77 | ||
76 | /* |
78 | /* |
77 | * We do identity mapping of 4M-page at 4M. |
79 | * We do identity mapping of 4M-page at 4M. |
78 | */ |
80 | */ |
79 | tag.value = ASID_KERNEL; |
81 | tag.value = ASID_KERNEL; |
80 | tag.vpn = pg.vpn; |
82 | tag.vpn = pg.vpn; |
81 | 83 | ||
82 | itlb_tag_access_write(tag.value); |
84 | itlb_tag_access_write(tag.value); |
83 | dtlb_tag_access_write(tag.value); |
85 | dtlb_tag_access_write(tag.value); |
84 | 86 | ||
85 | data.value = 0; |
87 | data.value = 0; |
86 | data.v = true; |
88 | data.v = true; |
87 | data.size = PAGESIZE_4M; |
89 | data.size = PAGESIZE_4M; |
88 | data.pfn = fr.pfn; |
90 | data.pfn = fr.pfn; |
89 | data.l = true; |
91 | data.l = true; |
90 | data.cp = 1; |
92 | data.cp = 1; |
91 | data.cv = 1; |
93 | data.cv = 1; |
92 | data.p = true; |
94 | data.p = true; |
93 | data.w = true; |
95 | data.w = true; |
94 | data.g = true; |
96 | data.g = true; |
95 | 97 | ||
96 | itlb_data_in_write(data.value); |
98 | itlb_data_in_write(data.value); |
97 | dtlb_data_in_write(data.value); |
99 | dtlb_data_in_write(data.value); |
98 | 100 | ||
99 | /* |
101 | /* |
100 | * Register window traps can occur before MMU is enabled again. |
102 | * Register window traps can occur before MMU is enabled again. |
101 | * This ensures that any such traps will be handled from |
103 | * This ensures that any such traps will be handled from |
102 | * kernel identity mapped trap handler. |
104 | * kernel identity mapped trap handler. |
103 | */ |
105 | */ |
104 | trap_switch_trap_table(); |
106 | trap_switch_trap_table(); |
105 | 107 | ||
106 | tlb_invalidate_all(); |
108 | tlb_invalidate_all(); |
107 | 109 | ||
108 | dmmu_enable(); |
110 | dmmu_enable(); |
109 | immu_enable(); |
111 | immu_enable(); |
110 | 112 | ||
111 | /* |
113 | /* |
112 | * Quick hack: map frame buffer |
114 | * Quick hack: map frame buffer |
113 | */ |
115 | */ |
114 | fr.address = FB_PHYS_ADDRESS; |
116 | fr.address = FB_PHYS_ADDRESS; |
115 | pg.address = FB_VIRT_ADDRESS; |
117 | pg.address = FB_VIRT_ADDRESS; |
116 | 118 | ||
117 | tag.value = ASID_KERNEL; |
119 | tag.value = ASID_KERNEL; |
118 | tag.vpn = pg.vpn; |
120 | tag.vpn = pg.vpn; |
119 | 121 | ||
120 | dtlb_tag_access_write(tag.value); |
122 | dtlb_tag_access_write(tag.value); |
121 | 123 | ||
122 | data.value = 0; |
124 | data.value = 0; |
123 | data.v = true; |
125 | data.v = true; |
124 | data.size = PAGESIZE_4M; |
126 | data.size = PAGESIZE_4M; |
125 | data.pfn = fr.pfn; |
127 | data.pfn = fr.pfn; |
- | 128 | data.l = true; |
|
- | 129 | data.cp = 0; |
|
- | 130 | data.cv = 0; |
|
- | 131 | data.p = true; |
|
- | 132 | data.w = true; |
|
- | 133 | data.g = true; |
|
- | 134 | ||
- | 135 | dtlb_data_in_write(data.value); |
|
- | 136 | ||
- | 137 | /* |
|
- | 138 | * Quick hack: map keyboard |
|
- | 139 | */ |
|
- | 140 | fr.address = KBD_PHYS_ADDRESS; |
|
- | 141 | pg.address = KBD_VIRT_ADDRESS; |
|
- | 142 | ||
- | 143 | tag.value = ASID_KERNEL; |
|
- | 144 | tag.vpn = pg.vpn; |
|
- | 145 | ||
- | 146 | dtlb_tag_access_write(tag.value); |
|
- | 147 | ||
- | 148 | data.value = 0; |
|
- | 149 | data.v = true; |
|
- | 150 | data.size = PAGESIZE_8K; |
|
- | 151 | data.pfn = fr.pfn; |
|
126 | data.l = true; |
152 | data.l = true; |
127 | data.cp = 0; |
153 | data.cp = 0; |
128 | data.cv = 0; |
154 | data.cv = 0; |
129 | data.p = true; |
155 | data.p = true; |
130 | data.w = true; |
156 | data.w = true; |
131 | data.g = true; |
157 | data.g = true; |
132 | 158 | ||
133 | dtlb_data_in_write(data.value); |
159 | dtlb_data_in_write(data.value); |
134 | } |
160 | } |
135 | 161 | ||
136 | /** ITLB miss handler. */ |
162 | /** ITLB miss handler. */ |
137 | void fast_instruction_access_mmu_miss(void) |
163 | void fast_instruction_access_mmu_miss(void) |
138 | { |
164 | { |
139 | panic("%s\n", __FUNCTION__); |
165 | panic("%s\n", __FUNCTION__); |
140 | } |
166 | } |
141 | 167 | ||
142 | /** DTLB miss handler. */ |
168 | /** DTLB miss handler. */ |
143 | void fast_data_access_mmu_miss(void) |
169 | void fast_data_access_mmu_miss(void) |
144 | { |
170 | { |
145 | tlb_tag_access_reg_t tag; |
171 | tlb_tag_access_reg_t tag; |
146 | tlb_data_t data; |
172 | tlb_data_t data; |
147 | __address tpc; |
173 | __address tpc; |
148 | char *tpc_str; |
174 | char *tpc_str; |
149 | 175 | ||
150 | tag.value = dtlb_tag_access_read(); |
176 | tag.value = dtlb_tag_access_read(); |
151 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
177 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
152 | tpc = tpc_read(); |
178 | tpc = tpc_read(); |
153 | tpc_str = get_symtab_entry(tpc); |
179 | tpc_str = get_symtab_entry(tpc); |
154 | 180 | ||
155 | printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context); |
181 | printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context); |
156 | printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?"); |
182 | printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?"); |
157 | panic("%s\n", __FUNCTION__); |
183 | panic("%s\n", __FUNCTION__); |
158 | } |
184 | } |
159 | 185 | ||
160 | /* |
186 | /* |
161 | * Identity map piece of faulting kernel address space. |
187 | * Identity map piece of faulting kernel address space. |
162 | */ |
188 | */ |
163 | data.value = 0; |
189 | data.value = 0; |
164 | data.v = true; |
190 | data.v = true; |
165 | data.size = PAGESIZE_8K; |
191 | data.size = PAGESIZE_8K; |
166 | data.pfn = tag.vpn; |
192 | data.pfn = tag.vpn; |
167 | data.l = false; |
193 | data.l = false; |
168 | data.cp = 1; |
194 | data.cp = 1; |
169 | data.cv = 1; |
195 | data.cv = 1; |
170 | data.p = true; |
196 | data.p = true; |
171 | data.w = true; |
197 | data.w = true; |
172 | data.g = true; |
198 | data.g = true; |
173 | 199 | ||
174 | dtlb_data_in_write(data.value); |
200 | dtlb_data_in_write(data.value); |
175 | } |
201 | } |
176 | 202 | ||
177 | /** DTLB protection fault handler. */ |
203 | /** DTLB protection fault handler. */ |
178 | void fast_data_access_protection(void) |
204 | void fast_data_access_protection(void) |
179 | { |
205 | { |
180 | panic("%s\n", __FUNCTION__); |
206 | panic("%s\n", __FUNCTION__); |
181 | } |
207 | } |
182 | 208 | ||
183 | /** Print contents of both TLBs. */ |
209 | /** Print contents of both TLBs. */ |
184 | void tlb_print(void) |
210 | void tlb_print(void) |
185 | { |
211 | { |
186 | int i; |
212 | int i; |
187 | tlb_data_t d; |
213 | tlb_data_t d; |
188 | tlb_tag_read_reg_t t; |
214 | tlb_tag_read_reg_t t; |
189 | 215 | ||
190 | printf("I-TLB contents:\n"); |
216 | printf("I-TLB contents:\n"); |
191 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
217 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
192 | d.value = itlb_data_access_read(i); |
218 | d.value = itlb_data_access_read(i); |
193 | t.value = itlb_tag_read_read(i); |
219 | t.value = itlb_tag_read_read(i); |
194 | 220 | ||
195 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
221 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
196 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
222 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
197 | } |
223 | } |
198 | 224 | ||
199 | printf("D-TLB contents:\n"); |
225 | printf("D-TLB contents:\n"); |
200 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
226 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
201 | d.value = dtlb_data_access_read(i); |
227 | d.value = dtlb_data_access_read(i); |
202 | t.value = dtlb_tag_read_read(i); |
228 | t.value = dtlb_tag_read_read(i); |
203 | 229 | ||
204 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
230 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
205 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
231 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
206 | } |
232 | } |
207 | 233 | ||
208 | } |
234 | } |
209 | 235 | ||
210 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
236 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
211 | void tlb_invalidate_all(void) |
237 | void tlb_invalidate_all(void) |
212 | { |
238 | { |
213 | int i; |
239 | int i; |
214 | tlb_data_t d; |
240 | tlb_data_t d; |
215 | tlb_tag_read_reg_t t; |
241 | tlb_tag_read_reg_t t; |
216 | 242 | ||
217 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
243 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
218 | d.value = itlb_data_access_read(i); |
244 | d.value = itlb_data_access_read(i); |
219 | if (!d.l) { |
245 | if (!d.l) { |
220 | t.value = itlb_tag_read_read(i); |
246 | t.value = itlb_tag_read_read(i); |
221 | d.v = false; |
247 | d.v = false; |
222 | itlb_tag_access_write(t.value); |
248 | itlb_tag_access_write(t.value); |
223 | itlb_data_access_write(i, d.value); |
249 | itlb_data_access_write(i, d.value); |
224 | } |
250 | } |
225 | } |
251 | } |
226 | 252 | ||
227 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
253 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
228 | d.value = dtlb_data_access_read(i); |
254 | d.value = dtlb_data_access_read(i); |
229 | if (!d.l) { |
255 | if (!d.l) { |
230 | t.value = dtlb_tag_read_read(i); |
256 | t.value = dtlb_tag_read_read(i); |
231 | d.v = false; |
257 | d.v = false; |
232 | dtlb_tag_access_write(t.value); |
258 | dtlb_tag_access_write(t.value); |
233 | dtlb_data_access_write(i, d.value); |
259 | dtlb_data_access_write(i, d.value); |
234 | } |
260 | } |
235 | } |
261 | } |
236 | 262 | ||
237 | } |
263 | } |
238 | 264 | ||
239 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
265 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
240 | * |
266 | * |
241 | * @param asid Address Space ID. |
267 | * @param asid Address Space ID. |
242 | */ |
268 | */ |
243 | void tlb_invalidate_asid(asid_t asid) |
269 | void tlb_invalidate_asid(asid_t asid) |
244 | { |
270 | { |
245 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
271 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
246 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
272 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
247 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
273 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
248 | } |
274 | } |
249 | 275 | ||
250 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
276 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
251 | * |
277 | * |
252 | * @param asid Address Space ID. |
278 | * @param asid Address Space ID. |
253 | * @param page First page which to sweep out from ITLB and DTLB. |
279 | * @param page First page which to sweep out from ITLB and DTLB. |
254 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
280 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
255 | */ |
281 | */ |
256 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
282 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
257 | { |
283 | { |
258 | int i; |
284 | int i; |
259 | 285 | ||
260 | for (i = 0; i < cnt; i++) { |
286 | for (i = 0; i < cnt; i++) { |
261 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
287 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
262 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
288 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
263 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
289 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
264 | } |
290 | } |
265 | } |
291 | } |
266 | 292 |