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| 1 | /* |
1 | /* |
| 2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (C) 2006 Jakub Jermar |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| 34 | 34 | ||
| 35 | #ifndef KERN_sparc64_TSB_H_ |
35 | #ifndef KERN_sparc64_TSB_H_ |
| 36 | #define KERN_sparc64_TSB_H_ |
36 | #define KERN_sparc64_TSB_H_ |
| 37 | 37 | ||
| 38 | #include <arch/mm/tte.h> |
38 | #include <arch/mm/tte.h> |
| - | 39 | #include <arch/mm/mmu.h> |
|
| 39 | #include <arch/types.h> |
40 | #include <arch/types.h> |
| 40 | #include <typedefs.h> |
41 | #include <typedefs.h> |
| 41 | 42 | ||
| 42 | /* |
43 | /* |
| 43 | * ITSB abd DTSB will claim 64K of memory, which |
44 | * ITSB abd DTSB will claim 64K of memory, which |
| 44 | * is a nice number considered that it is one of |
45 | * is a nice number considered that it is one of |
| 45 | * the page sizes supported by hardware, which, |
46 | * the page sizes supported by hardware, which, |
| 46 | * again, is nice because TSBs need to be locked |
47 | * again, is nice because TSBs need to be locked |
| 47 | * in TLBs - only one TLB entry will do. |
48 | * in TLBs - only one TLB entry will do. |
| 48 | */ |
49 | */ |
| - | 50 | #define TSB_SIZE 2 /* when changing this, change as.c as well */ |
|
| 49 | #define ITSB_ENTRY_COUNT 2048 |
51 | #define ITSB_ENTRY_COUNT (512*(1<<TSB_SIZE)) |
| 50 | #define DTSB_ENTRY_COUNT 2048 |
52 | #define DTSB_ENTRY_COUNT (512*(1<<TSB_SIZE)) |
| 51 | 53 | ||
| 52 | struct tsb_entry { |
54 | struct tsb_entry { |
| 53 | tte_tag_t tag; |
55 | tte_tag_t tag; |
| 54 | tte_data_t data; |
56 | tte_data_t data; |
| 55 | } __attribute__ ((packed)); |
57 | } __attribute__ ((packed)); |
| 56 | - | ||
| 57 | typedef struct tsb_entry tsb_entry_t; |
58 | typedef struct tsb_entry tsb_entry_t; |
| 58 | 59 | ||
| - | 60 | /** TSB Base register. */ |
|
| - | 61 | union tsb_base_reg { |
|
| - | 62 | uint64_t value; |
|
| - | 63 | struct { |
|
| - | 64 | uint64_t base : 51; /**< TSB base address, bits 63:13. */ |
|
| - | 65 | unsigned split : 1; /**< Split vs. common TSB for 8K and 64K pages. |
|
| - | 66 | * HelenOS uses only 8K pages for user mappings, |
|
| - | 67 | * so we always set this to 0. |
|
| - | 68 | */ |
|
| - | 69 | unsigned : 9; |
|
| - | 70 | unsigned size : 3; /**< TSB size. Number of entries is 512*2^size. */ |
|
| - | 71 | } __attribute__ ((packed)); |
|
| - | 72 | }; |
|
| - | 73 | typedef union tsb_base_reg tsb_base_reg_t; |
|
| - | 74 | ||
| - | 75 | /** Read ITSB Base register. |
|
| - | 76 | * |
|
| - | 77 | * @return Content of the ITSB Base register. |
|
| - | 78 | */ |
|
| - | 79 | static inline uint64_t itsb_base_read(void) |
|
| - | 80 | { |
|
| - | 81 | return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); |
|
| - | 82 | } |
|
| - | 83 | ||
| - | 84 | /** Read DTSB Base register. |
|
| - | 85 | * |
|
| - | 86 | * @return Content of the DTSB Base register. |
|
| - | 87 | */ |
|
| - | 88 | static inline uint64_t dtsb_base_read(void) |
|
| - | 89 | { |
|
| - | 90 | return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); |
|
| - | 91 | } |
|
| - | 92 | ||
| - | 93 | /** Write ITSB Base register. |
|
| - | 94 | * |
|
| - | 95 | * @param v New content of the ITSB Base register. |
|
| - | 96 | */ |
|
| - | 97 | static inline void itsb_base_write(uint64_t v) |
|
| - | 98 | { |
|
| - | 99 | asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); |
|
| - | 100 | } |
|
| - | 101 | ||
| - | 102 | /** Write DTSB Base register. |
|
| - | 103 | * |
|
| - | 104 | * @param v New content of the DTSB Base register. |
|
| - | 105 | */ |
|
| - | 106 | static inline void dtsb_base_write(uint64_t v) |
|
| - | 107 | { |
|
| - | 108 | asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
|
| - | 109 | } |
|
| - | 110 | ||
| 59 | extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages); |
111 | extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages); |
| 60 | 112 | ||
| 61 | #endif |
113 | #endif |
| 62 | 114 | ||
| 63 | /** @} |
115 | /** @} |
| 64 | */ |
116 | */ |
| 65 | 117 | ||