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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
- | 38 | #include <interrupt.h> |
|
38 | #include <mm/as.h> |
39 | #include <mm/as.h> |
39 | #include <arch.h> |
40 | #include <arch.h> |
40 | #include <print.h> |
41 | #include <print.h> |
41 | #include <symtab.h> |
42 | #include <symtab.h> |
42 | 43 | ||
43 | 44 | ||
44 | /** Try to find PTE for faulting address |
45 | /** Try to find PTE for faulting address |
45 | * |
46 | * |
46 | * Try to find PTE for faulting address. |
47 | * Try to find PTE for faulting address. |
47 | * The as->lock must be held on entry to this function |
48 | * The as->lock must be held on entry to this function |
48 | * if lock is true. |
49 | * if lock is true. |
49 | * |
50 | * |
50 | * @param as Address space. |
51 | * @param as Address space. |
51 | * @param lock Lock/unlock the address space. |
52 | * @param lock Lock/unlock the address space. |
52 | * @param badvaddr Faulting virtual address. |
53 | * @param badvaddr Faulting virtual address. |
53 | * @param access Access mode that caused the fault. |
54 | * @param access Access mode that caused the fault. |
54 | * @param istate Pointer to interrupted state. |
55 | * @param istate Pointer to interrupted state. |
55 | * @param pfrc Pointer to variable where as_page_fault() return code |
56 | * @param pfrc Pointer to variable where as_page_fault() return code |
56 | * will be stored. |
57 | * will be stored. |
57 | * @return PTE on success, NULL otherwise. |
58 | * @return PTE on success, NULL otherwise. |
58 | * |
59 | * |
59 | */ |
60 | */ |
60 | static pte_t * |
61 | static pte_t * |
61 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
62 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
62 | istate_t *istate, int *pfrc) |
63 | istate_t *istate, int *pfrc) |
63 | { |
64 | { |
64 | /* |
65 | /* |
65 | * Check if the mapping exists in page tables. |
66 | * Check if the mapping exists in page tables. |
66 | */ |
67 | */ |
67 | pte_t *pte = page_mapping_find(as, badvaddr); |
68 | pte_t *pte = page_mapping_find(as, badvaddr); |
68 | if ((pte) && (pte->p)) { |
69 | if ((pte) && (pte->p)) { |
69 | /* |
70 | /* |
70 | * Mapping found in page tables. |
71 | * Mapping found in page tables. |
71 | * Immediately succeed. |
72 | * Immediately succeed. |
72 | */ |
73 | */ |
73 | return pte; |
74 | return pte; |
74 | } else { |
75 | } else { |
75 | int rc; |
76 | int rc; |
76 | 77 | ||
77 | /* |
78 | /* |
78 | * Mapping not found in page tables. |
79 | * Mapping not found in page tables. |
79 | * Resort to higher-level page fault handler. |
80 | * Resort to higher-level page fault handler. |
80 | */ |
81 | */ |
81 | page_table_unlock(as, lock); |
82 | page_table_unlock(as, lock); |
82 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
83 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
83 | case AS_PF_OK: |
84 | case AS_PF_OK: |
84 | /* |
85 | /* |
85 | * The higher-level page fault handler succeeded, |
86 | * The higher-level page fault handler succeeded, |
86 | * The mapping ought to be in place. |
87 | * The mapping ought to be in place. |
87 | */ |
88 | */ |
88 | page_table_lock(as, lock); |
89 | page_table_lock(as, lock); |
89 | pte = page_mapping_find(as, badvaddr); |
90 | pte = page_mapping_find(as, badvaddr); |
90 | ASSERT((pte) && (pte->p)); |
91 | ASSERT((pte) && (pte->p)); |
91 | *pfrc = 0; |
92 | *pfrc = 0; |
92 | return pte; |
93 | return pte; |
93 | case AS_PF_DEFER: |
94 | case AS_PF_DEFER: |
94 | page_table_lock(as, lock); |
95 | page_table_lock(as, lock); |
95 | *pfrc = rc; |
96 | *pfrc = rc; |
96 | return NULL; |
97 | return NULL; |
97 | case AS_PF_FAULT: |
98 | case AS_PF_FAULT: |
98 | page_table_lock(as, lock); |
99 | page_table_lock(as, lock); |
99 | *pfrc = rc; |
100 | *pfrc = rc; |
100 | return NULL; |
101 | return NULL; |
101 | default: |
102 | default: |
102 | panic("unexpected rc (%d)\n", rc); |
103 | panic("unexpected rc (%d)\n", rc); |
103 | } |
104 | } |
104 | } |
105 | } |
105 | } |
106 | } |
106 | 107 | ||
107 | 108 | ||
108 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
109 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
109 | { |
110 | { |
110 | char *symbol = ""; |
111 | char *symbol = ""; |
111 | char *sym2 = ""; |
112 | char *sym2 = ""; |
112 | 113 | ||
113 | char *s = get_symtab_entry(istate->pc); |
114 | char *s = get_symtab_entry(istate->pc); |
114 | if (s) |
115 | if (s) |
115 | symbol = s; |
116 | symbol = s; |
116 | s = get_symtab_entry(istate->lr); |
117 | s = get_symtab_entry(istate->lr); |
117 | if (s) |
118 | if (s) |
118 | sym2 = s; |
119 | sym2 = s; |
- | 120 | ||
- | 121 | fault_if_from_uspace(istate, |
|
- | 122 | "%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, |
|
- | 123 | istate->pc, symbol, sym2); |
|
119 | panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, |
124 | panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, |
120 | istate->pc, symbol, sym2); |
125 | istate->pc, symbol, sym2); |
121 | } |
126 | } |
122 | 127 | ||
123 | 128 | ||
124 | static void pht_insert(const uintptr_t vaddr, const pfn_t pfn) |
129 | static void pht_insert(const uintptr_t vaddr, const pfn_t pfn) |
125 | { |
130 | { |
126 | uint32_t page = (vaddr >> 12) & 0xffff; |
131 | uint32_t page = (vaddr >> 12) & 0xffff; |
127 | uint32_t api = (vaddr >> 22) & 0x3f; |
132 | uint32_t api = (vaddr >> 22) & 0x3f; |
128 | 133 | ||
129 | uint32_t vsid; |
134 | uint32_t vsid; |
130 | asm volatile ( |
135 | asm volatile ( |
131 | "mfsrin %0, %1\n" |
136 | "mfsrin %0, %1\n" |
132 | : "=r" (vsid) |
137 | : "=r" (vsid) |
133 | : "r" (vaddr) |
138 | : "r" (vaddr) |
134 | ); |
139 | ); |
135 | 140 | ||
136 | uint32_t sdr1; |
141 | uint32_t sdr1; |
137 | asm volatile ( |
142 | asm volatile ( |
138 | "mfsdr1 %0\n" |
143 | "mfsdr1 %0\n" |
139 | : "=r" (sdr1) |
144 | : "=r" (sdr1) |
140 | ); |
145 | ); |
141 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
146 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
142 | 147 | ||
143 | /* Primary hash (xor) */ |
148 | /* Primary hash (xor) */ |
144 | uint32_t h = 0; |
149 | uint32_t h = 0; |
145 | uint32_t hash = vsid ^ page; |
150 | uint32_t hash = vsid ^ page; |
146 | uint32_t base = (hash & 0x3ff) << 3; |
151 | uint32_t base = (hash & 0x3ff) << 3; |
147 | uint32_t i; |
152 | uint32_t i; |
148 | bool found = false; |
153 | bool found = false; |
149 | 154 | ||
150 | /* Find unused or colliding |
155 | /* Find unused or colliding |
151 | PTE in PTEG */ |
156 | PTE in PTEG */ |
152 | for (i = 0; i < 8; i++) { |
157 | for (i = 0; i < 8; i++) { |
153 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && |
158 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && |
154 | (phte[base + i].api == api))) { |
159 | (phte[base + i].api == api))) { |
155 | found = true; |
160 | found = true; |
156 | break; |
161 | break; |
157 | } |
162 | } |
158 | } |
163 | } |
159 | 164 | ||
160 | if (!found) { |
165 | if (!found) { |
161 | /* Secondary hash (not) */ |
166 | /* Secondary hash (not) */ |
162 | uint32_t base2 = (~hash & 0x3ff) << 3; |
167 | uint32_t base2 = (~hash & 0x3ff) << 3; |
163 | 168 | ||
164 | /* Find unused or colliding |
169 | /* Find unused or colliding |
165 | PTE in PTEG */ |
170 | PTE in PTEG */ |
166 | for (i = 0; i < 8; i++) { |
171 | for (i = 0; i < 8; i++) { |
167 | if ((!phte[base2 + i].v) || |
172 | if ((!phte[base2 + i].v) || |
168 | ((phte[base2 + i].vsid == vsid) && |
173 | ((phte[base2 + i].vsid == vsid) && |
169 | (phte[base2 + i].api == api))) { |
174 | (phte[base2 + i].api == api))) { |
170 | found = true; |
175 | found = true; |
171 | base = base2; |
176 | base = base2; |
172 | h = 1; |
177 | h = 1; |
173 | break; |
178 | break; |
174 | } |
179 | } |
175 | } |
180 | } |
176 | 181 | ||
177 | if (!found) { |
182 | if (!found) { |
178 | // TODO: A/C precedence groups |
183 | // TODO: A/C precedence groups |
179 | i = page % 8; |
184 | i = page % 8; |
180 | } |
185 | } |
181 | } |
186 | } |
182 | 187 | ||
183 | phte[base + i].v = 1; |
188 | phte[base + i].v = 1; |
184 | phte[base + i].vsid = vsid; |
189 | phte[base + i].vsid = vsid; |
185 | phte[base + i].h = h; |
190 | phte[base + i].h = h; |
186 | phte[base + i].api = api; |
191 | phte[base + i].api = api; |
187 | phte[base + i].rpn = pfn; |
192 | phte[base + i].rpn = pfn; |
188 | phte[base + i].r = 0; |
193 | phte[base + i].r = 0; |
189 | phte[base + i].c = 0; |
194 | phte[base + i].c = 0; |
190 | phte[base + i].pp = 2; // FIXME |
195 | phte[base + i].pp = 2; // FIXME |
191 | } |
196 | } |
192 | 197 | ||
193 | 198 | ||
194 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
199 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
195 | { |
200 | { |
196 | uint32_t page = (vaddr >> 12) & 0xffff; |
201 | uint32_t page = (vaddr >> 12) & 0xffff; |
197 | uint32_t api = (vaddr >> 22) & 0x3f; |
202 | uint32_t api = (vaddr >> 22) & 0x3f; |
198 | 203 | ||
199 | uint32_t vsid; |
204 | uint32_t vsid; |
200 | asm volatile ( |
205 | asm volatile ( |
201 | "mfsrin %0, %1\n" |
206 | "mfsrin %0, %1\n" |
202 | : "=r" (vsid) |
207 | : "=r" (vsid) |
203 | : "r" (vaddr) |
208 | : "r" (vaddr) |
204 | ); |
209 | ); |
205 | 210 | ||
206 | uint32_t sdr1; |
211 | uint32_t sdr1; |
207 | asm volatile ( |
212 | asm volatile ( |
208 | "mfsdr1 %0\n" |
213 | "mfsdr1 %0\n" |
209 | : "=r" (sdr1) |
214 | : "=r" (sdr1) |
210 | ); |
215 | ); |
211 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
216 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
212 | 217 | ||
213 | /* Primary hash (xor) */ |
218 | /* Primary hash (xor) */ |
214 | uint32_t h = 0; |
219 | uint32_t h = 0; |
215 | uint32_t hash = vsid ^ page; |
220 | uint32_t hash = vsid ^ page; |
216 | uint32_t base = (hash & 0x3ff) << 3; |
221 | uint32_t base = (hash & 0x3ff) << 3; |
217 | uint32_t i; |
222 | uint32_t i; |
218 | bool found = false; |
223 | bool found = false; |
219 | 224 | ||
220 | /* Find unused or colliding |
225 | /* Find unused or colliding |
221 | PTE in PTEG */ |
226 | PTE in PTEG */ |
222 | for (i = 0; i < 8; i++) { |
227 | for (i = 0; i < 8; i++) { |
223 | if ((!phte_physical[base + i].v) || |
228 | if ((!phte_physical[base + i].v) || |
224 | ((phte_physical[base + i].vsid == vsid) && |
229 | ((phte_physical[base + i].vsid == vsid) && |
225 | (phte_physical[base + i].api == api))) { |
230 | (phte_physical[base + i].api == api))) { |
226 | found = true; |
231 | found = true; |
227 | break; |
232 | break; |
228 | } |
233 | } |
229 | } |
234 | } |
230 | 235 | ||
231 | if (!found) { |
236 | if (!found) { |
232 | /* Secondary hash (not) */ |
237 | /* Secondary hash (not) */ |
233 | uint32_t base2 = (~hash & 0x3ff) << 3; |
238 | uint32_t base2 = (~hash & 0x3ff) << 3; |
234 | 239 | ||
235 | /* Find unused or colliding |
240 | /* Find unused or colliding |
236 | PTE in PTEG */ |
241 | PTE in PTEG */ |
237 | for (i = 0; i < 8; i++) { |
242 | for (i = 0; i < 8; i++) { |
238 | if ((!phte_physical[base2 + i].v) || |
243 | if ((!phte_physical[base2 + i].v) || |
239 | ((phte_physical[base2 + i].vsid == vsid) && |
244 | ((phte_physical[base2 + i].vsid == vsid) && |
240 | (phte_physical[base2 + i].api == api))) { |
245 | (phte_physical[base2 + i].api == api))) { |
241 | found = true; |
246 | found = true; |
242 | base = base2; |
247 | base = base2; |
243 | h = 1; |
248 | h = 1; |
244 | break; |
249 | break; |
245 | } |
250 | } |
246 | } |
251 | } |
247 | 252 | ||
248 | if (!found) { |
253 | if (!found) { |
249 | // TODO: A/C precedence groups |
254 | // TODO: A/C precedence groups |
250 | i = page % 8; |
255 | i = page % 8; |
251 | } |
256 | } |
252 | } |
257 | } |
253 | 258 | ||
254 | phte_physical[base + i].v = 1; |
259 | phte_physical[base + i].v = 1; |
255 | phte_physical[base + i].vsid = vsid; |
260 | phte_physical[base + i].vsid = vsid; |
256 | phte_physical[base + i].h = h; |
261 | phte_physical[base + i].h = h; |
257 | phte_physical[base + i].api = api; |
262 | phte_physical[base + i].api = api; |
258 | phte_physical[base + i].rpn = pfn; |
263 | phte_physical[base + i].rpn = pfn; |
259 | phte_physical[base + i].r = 0; |
264 | phte_physical[base + i].r = 0; |
260 | phte_physical[base + i].c = 0; |
265 | phte_physical[base + i].c = 0; |
261 | phte_physical[base + i].pp = 2; // FIXME |
266 | phte_physical[base + i].pp = 2; // FIXME |
262 | } |
267 | } |
263 | 268 | ||
264 | 269 | ||
265 | /** Process Instruction/Data Storage Interrupt |
270 | /** Process Instruction/Data Storage Interrupt |
266 | * |
271 | * |
267 | * @param n Interrupt vector number. |
272 | * @param n Interrupt vector number. |
268 | * @param istate Interrupted register context. |
273 | * @param istate Interrupted register context. |
269 | * |
274 | * |
270 | */ |
275 | */ |
271 | void pht_refill(int n, istate_t *istate) |
276 | void pht_refill(int n, istate_t *istate) |
272 | { |
277 | { |
273 | uintptr_t badvaddr; |
278 | uintptr_t badvaddr; |
274 | pte_t *pte; |
279 | pte_t *pte; |
275 | int pfrc; |
280 | int pfrc; |
276 | as_t *as; |
281 | as_t *as; |
277 | bool lock; |
282 | bool lock; |
278 | 283 | ||
279 | if (AS == NULL) { |
284 | if (AS == NULL) { |
280 | as = AS_KERNEL; |
285 | as = AS_KERNEL; |
281 | lock = false; |
286 | lock = false; |
282 | } else { |
287 | } else { |
283 | as = AS; |
288 | as = AS; |
284 | lock = true; |
289 | lock = true; |
285 | } |
290 | } |
286 | 291 | ||
287 | if (n == VECTOR_DATA_STORAGE) { |
292 | if (n == VECTOR_DATA_STORAGE) { |
288 | asm volatile ( |
293 | asm volatile ( |
289 | "mfdar %0\n" |
294 | "mfdar %0\n" |
290 | : "=r" (badvaddr) |
295 | : "=r" (badvaddr) |
291 | ); |
296 | ); |
292 | } else |
297 | } else |
293 | badvaddr = istate->pc; |
298 | badvaddr = istate->pc; |
294 | 299 | ||
295 | page_table_lock(as, lock); |
300 | page_table_lock(as, lock); |
296 | 301 | ||
297 | pte = find_mapping_and_check(as, lock, badvaddr, |
302 | pte = find_mapping_and_check(as, lock, badvaddr, |
298 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
303 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
299 | if (!pte) { |
304 | if (!pte) { |
300 | switch (pfrc) { |
305 | switch (pfrc) { |
301 | case AS_PF_FAULT: |
306 | case AS_PF_FAULT: |
302 | goto fail; |
307 | goto fail; |
303 | break; |
308 | break; |
304 | case AS_PF_DEFER: |
309 | case AS_PF_DEFER: |
305 | /* |
310 | /* |
306 | * The page fault came during copy_from_uspace() |
311 | * The page fault came during copy_from_uspace() |
307 | * or copy_to_uspace(). |
312 | * or copy_to_uspace(). |
308 | */ |
313 | */ |
309 | page_table_unlock(as, lock); |
314 | page_table_unlock(as, lock); |
310 | return; |
315 | return; |
311 | default: |
316 | default: |
312 | panic("Unexpected pfrc (%d)\n", pfrc); |
317 | panic("Unexpected pfrc (%d)\n", pfrc); |
313 | } |
318 | } |
314 | } |
319 | } |
315 | 320 | ||
316 | pte->a = 1; /* Record access to PTE */ |
321 | pte->a = 1; /* Record access to PTE */ |
317 | pht_insert(badvaddr, pte->pfn); |
322 | pht_insert(badvaddr, pte->pfn); |
318 | 323 | ||
319 | page_table_unlock(as, lock); |
324 | page_table_unlock(as, lock); |
320 | return; |
325 | return; |
321 | 326 | ||
322 | fail: |
327 | fail: |
323 | page_table_unlock(as, lock); |
328 | page_table_unlock(as, lock); |
324 | pht_refill_fail(badvaddr, istate); |
329 | pht_refill_fail(badvaddr, istate); |
325 | } |
330 | } |
326 | 331 | ||
327 | 332 | ||
328 | /** Process Instruction/Data Storage Interrupt in Real Mode |
333 | /** Process Instruction/Data Storage Interrupt in Real Mode |
329 | * |
334 | * |
330 | * @param n Interrupt vector number. |
335 | * @param n Interrupt vector number. |
331 | * @param istate Interrupted register context. |
336 | * @param istate Interrupted register context. |
332 | * |
337 | * |
333 | */ |
338 | */ |
334 | bool pht_real_refill(int n, istate_t *istate) |
339 | bool pht_real_refill(int n, istate_t *istate) |
335 | { |
340 | { |
336 | uintptr_t badvaddr; |
341 | uintptr_t badvaddr; |
337 | 342 | ||
338 | if (n == VECTOR_DATA_STORAGE) { |
343 | if (n == VECTOR_DATA_STORAGE) { |
339 | asm volatile ( |
344 | asm volatile ( |
340 | "mfdar %0\n" |
345 | "mfdar %0\n" |
341 | : "=r" (badvaddr) |
346 | : "=r" (badvaddr) |
342 | ); |
347 | ); |
343 | } else |
348 | } else |
344 | badvaddr = istate->pc; |
349 | badvaddr = istate->pc; |
345 | 350 | ||
346 | uint32_t physmem; |
351 | uint32_t physmem; |
347 | asm volatile ( |
352 | asm volatile ( |
348 | "mfsprg3 %0\n" |
353 | "mfsprg3 %0\n" |
349 | : "=r" (physmem) |
354 | : "=r" (physmem) |
350 | ); |
355 | ); |
351 | 356 | ||
352 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
357 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
353 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
358 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
354 | return true; |
359 | return true; |
355 | } |
360 | } |
356 | 361 | ||
357 | return false; |
362 | return false; |
358 | } |
363 | } |
359 | 364 | ||
360 | 365 | ||
361 | void tlb_arch_init(void) |
366 | void tlb_arch_init(void) |
362 | { |
367 | { |
363 | tlb_invalidate_all(); |
368 | tlb_invalidate_all(); |
364 | } |
369 | } |
365 | 370 | ||
366 | 371 | ||
367 | void tlb_invalidate_all(void) |
372 | void tlb_invalidate_all(void) |
368 | { |
373 | { |
369 | asm volatile ( |
374 | asm volatile ( |
370 | "tlbia\n" |
375 | "tlbia\n" |
371 | "tlbsync\n" |
376 | "tlbsync\n" |
372 | ); |
377 | ); |
373 | } |
378 | } |
374 | 379 | ||
375 | 380 | ||
376 | void tlb_invalidate_asid(asid_t asid) |
381 | void tlb_invalidate_asid(asid_t asid) |
377 | { |
382 | { |
378 | uint32_t sdr1; |
383 | uint32_t sdr1; |
379 | asm volatile ( |
384 | asm volatile ( |
380 | "mfsdr1 %0\n" |
385 | "mfsdr1 %0\n" |
381 | : "=r" (sdr1) |
386 | : "=r" (sdr1) |
382 | ); |
387 | ); |
383 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
388 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
384 | 389 | ||
385 | uint32_t i; |
390 | uint32_t i; |
386 | for (i = 0; i < 8192; i++) { |
391 | for (i = 0; i < 8192; i++) { |
387 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
392 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
388 | (phte[i].vsid < ((asid << 4) + 16))) |
393 | (phte[i].vsid < ((asid << 4) + 16))) |
389 | phte[i].v = 0; |
394 | phte[i].v = 0; |
390 | } |
395 | } |
391 | tlb_invalidate_all(); |
396 | tlb_invalidate_all(); |
392 | } |
397 | } |
393 | 398 | ||
394 | 399 | ||
395 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
400 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
396 | { |
401 | { |
397 | // TODO |
402 | // TODO |
398 | tlb_invalidate_all(); |
403 | tlb_invalidate_all(); |
399 | } |
404 | } |
400 | 405 | ||
401 | 406 | ||
402 | #define PRINT_BAT(name, ureg, lreg) \ |
407 | #define PRINT_BAT(name, ureg, lreg) \ |
403 | asm volatile ( \ |
408 | asm volatile ( \ |
404 | "mfspr %0," #ureg "\n" \ |
409 | "mfspr %0," #ureg "\n" \ |
405 | "mfspr %1," #lreg "\n" \ |
410 | "mfspr %1," #lreg "\n" \ |
406 | : "=r" (upper), "=r" (lower) \ |
411 | : "=r" (upper), "=r" (lower) \ |
407 | ); \ |
412 | ); \ |
408 | mask = (upper & 0x1ffc) >> 2; \ |
413 | mask = (upper & 0x1ffc) >> 2; \ |
409 | if (upper & 3) { \ |
414 | if (upper & 3) { \ |
410 | uint32_t tmp = mask; \ |
415 | uint32_t tmp = mask; \ |
411 | length = 128; \ |
416 | length = 128; \ |
412 | while (tmp) { \ |
417 | while (tmp) { \ |
413 | if ((tmp & 1) == 0) { \ |
418 | if ((tmp & 1) == 0) { \ |
414 | printf("ibat[0]: error in mask\n"); \ |
419 | printf("ibat[0]: error in mask\n"); \ |
415 | break; \ |
420 | break; \ |
416 | } \ |
421 | } \ |
417 | length <<= 1; \ |
422 | length <<= 1; \ |
418 | tmp >>= 1; \ |
423 | tmp >>= 1; \ |
419 | } \ |
424 | } \ |
420 | } else \ |
425 | } else \ |
421 | length = 0; \ |
426 | length = 0; \ |
422 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
427 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
423 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
428 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
424 | lower & 0xffff0000, length, mask, \ |
429 | lower & 0xffff0000, length, mask, \ |
425 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
430 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
426 | (upper & 1) ? " user" : ""); |
431 | (upper & 1) ? " user" : ""); |
427 | 432 | ||
428 | 433 | ||
429 | void tlb_print(void) |
434 | void tlb_print(void) |
430 | { |
435 | { |
431 | uint32_t sr; |
436 | uint32_t sr; |
432 | 437 | ||
433 | for (sr = 0; sr < 16; sr++) { |
438 | for (sr = 0; sr < 16; sr++) { |
434 | uint32_t vsid; |
439 | uint32_t vsid; |
435 | asm volatile ( |
440 | asm volatile ( |
436 | "mfsrin %0, %1\n" |
441 | "mfsrin %0, %1\n" |
437 | : "=r" (vsid) |
442 | : "=r" (vsid) |
438 | : "r" (sr << 28) |
443 | : "r" (sr << 28) |
439 | ); |
444 | ); |
440 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, |
445 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, |
441 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
446 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
442 | ((vsid >> 30) & 1) ? " supervisor" : "", |
447 | ((vsid >> 30) & 1) ? " supervisor" : "", |
443 | ((vsid >> 29) & 1) ? " user" : ""); |
448 | ((vsid >> 29) & 1) ? " user" : ""); |
444 | } |
449 | } |
445 | 450 | ||
446 | uint32_t upper; |
451 | uint32_t upper; |
447 | uint32_t lower; |
452 | uint32_t lower; |
448 | uint32_t mask; |
453 | uint32_t mask; |
449 | uint32_t length; |
454 | uint32_t length; |
450 | 455 | ||
451 | PRINT_BAT("ibat[0]", 528, 529); |
456 | PRINT_BAT("ibat[0]", 528, 529); |
452 | PRINT_BAT("ibat[1]", 530, 531); |
457 | PRINT_BAT("ibat[1]", 530, 531); |
453 | PRINT_BAT("ibat[2]", 532, 533); |
458 | PRINT_BAT("ibat[2]", 532, 533); |
454 | PRINT_BAT("ibat[3]", 534, 535); |
459 | PRINT_BAT("ibat[3]", 534, 535); |
455 | 460 | ||
456 | PRINT_BAT("dbat[0]", 536, 537); |
461 | PRINT_BAT("dbat[0]", 536, 537); |
457 | PRINT_BAT("dbat[1]", 538, 539); |
462 | PRINT_BAT("dbat[1]", 538, 539); |
458 | PRINT_BAT("dbat[2]", 540, 541); |
463 | PRINT_BAT("dbat[2]", 540, 541); |
459 | PRINT_BAT("dbat[3]", 542, 543); |
464 | PRINT_BAT("dbat[3]", 542, 543); |
460 | } |
465 | } |
461 | 466 | ||
462 | /** @} |
467 | /** @} |
463 | */ |
468 | */ |
464 | 469 |