WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ppc32/src/asm.S


#
# Copyright (c) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
 
.text
 
.global userspace_asm
.global iret
.global iret_syscall
.global memsetb
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
 
userspace_asm:
 
	# r3 = uspace_uarg
	# r4 = stack
	# r5 = entry
	
	# disable interrupts
 
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	# set entry point
	
	mtsrr0 r5
	
	# set problem state, enable interrupts
	
	ori r31, r31, msr_pr
	ori r31, r31, msr_ee
	mtsrr1 r31
	
	# set stack
	
	mr sp, r4
 
	# %r3 is defined to hold pcb_ptr - set it to 0
 
	xor r3, r3, r3
	
	# jump to userspace
	
	rfi
 
iret:
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	lwz r0, 8(sp)
	lwz r2, 12(sp)
	lwz r3, 16(sp)
	lwz r4, 20(sp)
	lwz r5, 24(sp)
	lwz r6, 28(sp)
	lwz r7, 32(sp)
	lwz r8, 36(sp)
	lwz r9, 40(sp)
	lwz r10, 44(sp)
	lwz r11, 48(sp)
	lwz r13, 52(sp)
	lwz r14, 56(sp)
	lwz r15, 60(sp)
	lwz r16, 64(sp)
	lwz r17, 68(sp)
	lwz r18, 72(sp)
	lwz r19, 76(sp)
	lwz r20, 80(sp)
	lwz r21, 84(sp)
	lwz r22, 88(sp)
	lwz r23, 92(sp)
	lwz r24, 96(sp)
	lwz r25, 100(sp)
	lwz r26, 104(sp)
	lwz r27, 108(sp)
	lwz r28, 112(sp)
	lwz r29, 116(sp)
	lwz r30, 120(sp)
	lwz r31, 124(sp)
	
	lwz r12, 128(sp)
	mtcr r12
	
	lwz r12, 132(sp)
	mtsrr0 r12
	
	lwz r12, 136(sp)
	mtsrr1 r12
	
	lwz r12, 140(sp)
	mtlr r12
	
	lwz r12, 144(sp)
	mtctr r12
	
	lwz r12, 148(sp)
	mtxer r12
	
	lwz r12, 152(sp)
	lwz sp, 156(sp)
	
	rfi
 
iret_syscall:
	
	# reset decrementer
 
	li r31, 1000
	mtdec r31
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	lwz r0, 8(sp)
	lwz r2, 12(sp)
	lwz r4, 20(sp)
	lwz r5, 24(sp)
	lwz r6, 28(sp)
	lwz r7, 32(sp)
	lwz r8, 36(sp)
	lwz r9, 40(sp)
	lwz r10, 44(sp)
	lwz r11, 48(sp)
	lwz r13, 52(sp)
	lwz r14, 56(sp)
	lwz r15, 60(sp)
	lwz r16, 64(sp)
	lwz r17, 68(sp)
	lwz r18, 72(sp)
	lwz r19, 76(sp)
	lwz r20, 80(sp)
	lwz r21, 84(sp)
	lwz r22, 88(sp)
	lwz r23, 92(sp)
	lwz r24, 96(sp)
	lwz r25, 100(sp)
	lwz r26, 104(sp)
	lwz r27, 108(sp)
	lwz r28, 112(sp)
	lwz r29, 116(sp)
	lwz r30, 120(sp)
	lwz r31, 124(sp)
	
	lwz r12, 128(sp)
	mtcr r12
	
	lwz r12, 132(sp)
	mtsrr0 r12
	
	lwz r12, 136(sp)
	mtsrr1 r12
	
	lwz r12, 140(sp)
	mtlr r12
	
	lwz r12, 144(sp)
	mtctr r12
	
	lwz r12, 148(sp)
	mtxer r12
	
	lwz r12, 152(sp)
	lwz sp, 156(sp)
 
	rfi
	
memsetb:
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
	b _memsetb
 
 
 
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
 
	srwi. r7, r5, 3
	addi r6, r3, -4
	addi r4, r4, -4
	beq	2f
	
	andi. r0, r6, 3
	mtctr r7
	bne 5f
	
	1:
	
	lwz r7, 4(r4)
	lwzu r8, 8(r4)
	stw r7, 4(r6)
	stwu r8, 8(r6)
	bdnz 1b
	
	andi. r5, r5, 7
	
	2:
	
	cmplwi 0, r5, 4
	blt 3f
	
	lwzu r0, 4(r4)
	addi r5, r5, -4
	stwu r0, 4(r6)
	
	3:
	
	cmpwi 0, r5, 0
	beqlr
	mtctr r5
	addi r4, r4, 3
	addi r6, r6, 3
	
	4:
	
	lbzu r0, 1(r4)
	stbu r0, 1(r6)
	bdnz 4b
	blr
	
	5:
	
	subfic r0, r0, 4
	mtctr r0
	
	6:
	
	lbz r7, 4(r4)
	addi r4, r4, 1
	stb r7, 4(r6)
	addi r6, r6, 1
	bdnz 6b
	subf r5, r0, r5
	rlwinm. r7, r5, 32-3, 3, 31
	beq 2b
	mtctr r7
	b 1b
 
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	# return zero, failure
	xor r3, r3, r3
	blr
 

Rev 3191	Rev 3211
1	#	1	#
2	# Copyright (c) 2005 Martin Decky	2	# Copyright (c) 2005 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30		30
31	.text	31	.text
32		32
33	.global userspace_asm	33	.global userspace_asm
34	.global iret	34	.global iret
35	.global iret_syscall	35	.global iret_syscall
36	.global memsetb	36	.global memsetb
37	.global memcpy	37	.global memcpy
38	.global memcpy_from_uspace	38	.global memcpy_from_uspace
39	.global memcpy_to_uspace	39	.global memcpy_to_uspace
40	.global memcpy_from_uspace_failover_address	40	.global memcpy_from_uspace_failover_address
41	.global memcpy_to_uspace_failover_address	41	.global memcpy_to_uspace_failover_address
42		42
43	userspace_asm:	43	userspace_asm:
44		44
45	# r3 = uspace_uarg	45	# r3 = uspace_uarg
46	# r4 = stack	46	# r4 = stack
47	# r5 = entry	47	# r5 = entry
48		48
49	# disable interrupts	49	# disable interrupts
50		50
51	mfmsr r31	51	mfmsr r31
52	rlwinm r31, r31, 0, 17, 15	52	rlwinm r31, r31, 0, 17, 15
53	mtmsr r31	53	mtmsr r31
54		54
55	# set entry point	55	# set entry point
56		56
57	mtsrr0 r5	57	mtsrr0 r5
58		58
59	# set problem state, enable interrupts	59	# set problem state, enable interrupts
60		60
61	ori r31, r31, msr_pr	61	ori r31, r31, msr_pr
62	ori r31, r31, msr_ee	62	ori r31, r31, msr_ee
63	mtsrr1 r31	63	mtsrr1 r31
64		64
65	# set stack	65	# set stack
66		66
67	mr sp, r4	67	mr sp, r4
68		68
69	# %r3 is defined to hold pcb_ptr - set it to 0	69	# %r3 is defined to hold pcb_ptr - set it to 0
70		70
71	xor r3, r3, r3	71	xor r3, r3, r3
72		72
73	# jump to userspace	73	# jump to userspace
74		74
75	rfi	75	rfi
76		76
77	iret:	77	iret:
78		78
79	# disable interrupts	79	# disable interrupts
80		80
81	mfmsr r31	81	mfmsr r31
82	rlwinm r31, r31, 0, 17, 15	82	rlwinm r31, r31, 0, 17, 15
83	mtmsr r31	83	mtmsr r31
84		84
85	lwz r0, 8(sp)	85	lwz r0, 8(sp)
86	lwz r2, 12(sp)	86	lwz r2, 12(sp)
87	lwz r3, 16(sp)	87	lwz r3, 16(sp)
88	lwz r4, 20(sp)	88	lwz r4, 20(sp)
89	lwz r5, 24(sp)	89	lwz r5, 24(sp)
90	lwz r6, 28(sp)	90	lwz r6, 28(sp)
91	lwz r7, 32(sp)	91	lwz r7, 32(sp)
92	lwz r8, 36(sp)	92	lwz r8, 36(sp)
93	lwz r9, 40(sp)	93	lwz r9, 40(sp)
94	lwz r10, 44(sp)	94	lwz r10, 44(sp)
95	lwz r11, 48(sp)	95	lwz r11, 48(sp)
96	lwz r13, 52(sp)	96	lwz r13, 52(sp)
97	lwz r14, 56(sp)	97	lwz r14, 56(sp)
98	lwz r15, 60(sp)	98	lwz r15, 60(sp)
99	lwz r16, 64(sp)	99	lwz r16, 64(sp)
100	lwz r17, 68(sp)	100	lwz r17, 68(sp)
101	lwz r18, 72(sp)	101	lwz r18, 72(sp)
102	lwz r19, 76(sp)	102	lwz r19, 76(sp)
103	lwz r20, 80(sp)	103	lwz r20, 80(sp)
104	lwz r21, 84(sp)	104	lwz r21, 84(sp)
105	lwz r22, 88(sp)	105	lwz r22, 88(sp)
106	lwz r23, 92(sp)	106	lwz r23, 92(sp)
107	lwz r24, 96(sp)	107	lwz r24, 96(sp)
108	lwz r25, 100(sp)	108	lwz r25, 100(sp)
109	lwz r26, 104(sp)	109	lwz r26, 104(sp)
110	lwz r27, 108(sp)	110	lwz r27, 108(sp)
111	lwz r28, 112(sp)	111	lwz r28, 112(sp)
112	lwz r29, 116(sp)	112	lwz r29, 116(sp)
113	lwz r30, 120(sp)	113	lwz r30, 120(sp)
114	lwz r31, 124(sp)	114	lwz r31, 124(sp)
115		115
116	lwz r12, 128(sp)	116	lwz r12, 128(sp)
117	mtcr r12	117	mtcr r12
118		118
119	lwz r12, 132(sp)	119	lwz r12, 132(sp)
120	mtsrr0 r12	120	mtsrr0 r12
121		121
122	lwz r12, 136(sp)	122	lwz r12, 136(sp)
123	mtsrr1 r12	123	mtsrr1 r12
124		124
125	lwz r12, 140(sp)	125	lwz r12, 140(sp)
126	mtlr r12	126	mtlr r12
127		127
128	lwz r12, 144(sp)	128	lwz r12, 144(sp)
129	mtctr r12	129	mtctr r12
130		130
131	lwz r12, 148(sp)	131	lwz r12, 148(sp)
132	mtxer r12	132	mtxer r12
133		133
134	lwz r12, 152(sp)	134	lwz r12, 152(sp)
135	lwz sp, 156(sp)	135	lwz sp, 156(sp)
136		136
137	rfi	137	rfi
138		138
139	iret_syscall:	139	iret_syscall:
140		140
141	# reset decrementer	141	# reset decrementer
142		142
143	li r31, 1000	143	li r31, 1000
144	mtdec r31	144	mtdec r31
145		145
146	# disable interrupts	146	# disable interrupts
147		147
148	mfmsr r31	148	mfmsr r31
149	rlwinm r31, r31, 0, 17, 15	149	rlwinm r31, r31, 0, 17, 15
150	mtmsr r31	150	mtmsr r31
151		151
152	lwz r0, 8(sp)	152	lwz r0, 8(sp)
153	lwz r2, 12(sp)	153	lwz r2, 12(sp)
154	lwz r4, 20(sp)	154	lwz r4, 20(sp)
155	lwz r5, 24(sp)	155	lwz r5, 24(sp)
156	lwz r6, 28(sp)	156	lwz r6, 28(sp)
157	lwz r7, 32(sp)	157	lwz r7, 32(sp)
158	lwz r8, 36(sp)	158	lwz r8, 36(sp)
159	lwz r9, 40(sp)	159	lwz r9, 40(sp)
160	lwz r10, 44(sp)	160	lwz r10, 44(sp)
161	lwz r11, 48(sp)	161	lwz r11, 48(sp)
162	lwz r13, 52(sp)	162	lwz r13, 52(sp)
163	lwz r14, 56(sp)	163	lwz r14, 56(sp)
164	lwz r15, 60(sp)	164	lwz r15, 60(sp)
165	lwz r16, 64(sp)	165	lwz r16, 64(sp)
166	lwz r17, 68(sp)	166	lwz r17, 68(sp)
167	lwz r18, 72(sp)	167	lwz r18, 72(sp)
168	lwz r19, 76(sp)	168	lwz r19, 76(sp)
169	lwz r20, 80(sp)	169	lwz r20, 80(sp)
170	lwz r21, 84(sp)	170	lwz r21, 84(sp)
171	lwz r22, 88(sp)	171	lwz r22, 88(sp)
172	lwz r23, 92(sp)	172	lwz r23, 92(sp)
173	lwz r24, 96(sp)	173	lwz r24, 96(sp)
174	lwz r25, 100(sp)	174	lwz r25, 100(sp)
175	lwz r26, 104(sp)	175	lwz r26, 104(sp)
176	lwz r27, 108(sp)	176	lwz r27, 108(sp)
177	lwz r28, 112(sp)	177	lwz r28, 112(sp)
178	lwz r29, 116(sp)	178	lwz r29, 116(sp)
179	lwz r30, 120(sp)	179	lwz r30, 120(sp)
180	lwz r31, 124(sp)	180	lwz r31, 124(sp)
181		181
182	lwz r12, 128(sp)	182	lwz r12, 128(sp)
183	mtcr r12	183	mtcr r12
184		184
185	lwz r12, 132(sp)	185	lwz r12, 132(sp)
186	mtsrr0 r12	186	mtsrr0 r12
187		187
188	lwz r12, 136(sp)	188	lwz r12, 136(sp)
189	mtsrr1 r12	189	mtsrr1 r12
190		190
191	lwz r12, 140(sp)	191	lwz r12, 140(sp)
192	mtlr r12	192	mtlr r12
193		193
194	lwz r12, 144(sp)	194	lwz r12, 144(sp)
195	mtctr r12	195	mtctr r12
196		196
197	lwz r12, 148(sp)	197	lwz r12, 148(sp)
198	mtxer r12	198	mtxer r12
199		199
200	lwz r12, 152(sp)	200	lwz r12, 152(sp)
201	lwz sp, 156(sp)	201	lwz sp, 156(sp)
202		202
203	rfi	203	rfi
204		204
205	memsetb:	205	memsetb:
206	rlwimi r5, r5, 8, 16, 23	-
207	rlwimi r5, r5, 16, 0, 15	-
208		-
209	addi r14, r3, -4	-
210		-
211	cmplwi 0, r4, 4	-
212	blt 7f	-
213		-
214	stwu r5, 4(r14)	-
215	beqlr	-
216		-
217	andi. r15, r14, 3	-
218	add r4, r15, r4	-
219	subf r14, r15, r14	-
220	srwi r15, r4, 2	-
221	mtctr r15	-
222		-
223	bdz 6f	-
224		-
225	1:	-
226	stwu r5, 4(r14)	-
227	bdnz 1b	-
228		-
229	6:	-
230		-
231	andi. r4, r4, 3	-
232		-
233	7:	-
234		-
235	cmpwi 0, r4, 0	-
236	beqlr	-
237		-
238	mtctr r4	-
239	addi r6, r6, 3	-
240		-
241	8:	-
242		-
243	stbu r5, 1(r14)	-
244	bdnz 8b	206	b _memsetb
245		-
246	blr	-
247		207
248	memcpy:	208	memcpy:
249	memcpy_from_uspace:	209	memcpy_from_uspace:
250	memcpy_to_uspace:	210	memcpy_to_uspace:
251		211
252	srwi. r7, r5, 3	212	srwi. r7, r5, 3
253	addi r6, r3, -4	213	addi r6, r3, -4
254	addi r4, r4, -4	214	addi r4, r4, -4
255	beq 2f	215	beq 2f
256		216
257	andi. r0, r6, 3	217	andi. r0, r6, 3
258	mtctr r7	218	mtctr r7
259	bne 5f	219	bne 5f
260		220
261	1:	221	1:
262		222
263	lwz r7, 4(r4)	223	lwz r7, 4(r4)
264	lwzu r8, 8(r4)	224	lwzu r8, 8(r4)
265	stw r7, 4(r6)	225	stw r7, 4(r6)
266	stwu r8, 8(r6)	226	stwu r8, 8(r6)
267	bdnz 1b	227	bdnz 1b
268		228
269	andi. r5, r5, 7	229	andi. r5, r5, 7
270		230
271	2:	231	2:
272		232
273	cmplwi 0, r5, 4	233	cmplwi 0, r5, 4
274	blt 3f	234	blt 3f
275		235
276	lwzu r0, 4(r4)	236	lwzu r0, 4(r4)
277	addi r5, r5, -4	237	addi r5, r5, -4
278	stwu r0, 4(r6)	238	stwu r0, 4(r6)
279		239
280	3:	240	3:
281		241
282	cmpwi 0, r5, 0	242	cmpwi 0, r5, 0
283	beqlr	243	beqlr
284	mtctr r5	244	mtctr r5
285	addi r4, r4, 3	245	addi r4, r4, 3
286	addi r6, r6, 3	246	addi r6, r6, 3
287		247
288	4:	248	4:
289		249
290	lbzu r0, 1(r4)	250	lbzu r0, 1(r4)
291	stbu r0, 1(r6)	251	stbu r0, 1(r6)
292	bdnz 4b	252	bdnz 4b
293	blr	253	blr
294		254
295	5:	255	5:
296		256
297	subfic r0, r0, 4	257	subfic r0, r0, 4
298	mtctr r0	258	mtctr r0
299		259
300	6:	260	6:
301		261
302	lbz r7, 4(r4)	262	lbz r7, 4(r4)
303	addi r4, r4, 1	263	addi r4, r4, 1
304	stb r7, 4(r6)	264	stb r7, 4(r6)
305	addi r6, r6, 1	265	addi r6, r6, 1
306	bdnz 6b	266	bdnz 6b
307	subf r5, r0, r5	267	subf r5, r0, r5
308	rlwinm. r7, r5, 32-3, 3, 31	268	rlwinm. r7, r5, 32-3, 3, 31
309	beq 2b	269	beq 2b
310	mtctr r7	270	mtctr r7
311	b 1b	271	b 1b
312		272
313	memcpy_from_uspace_failover_address:	273	memcpy_from_uspace_failover_address:
314	memcpy_to_uspace_failover_address:	274	memcpy_to_uspace_failover_address:
315	# return zero, failure	275	# return zero, failure
316	xor r3, r3, r3	276	xor r3, r3, r3
317	blr	277	blr
318		278

Subversion Repositories HelenOS

(root)/branches/dynload/kernel/arch/ppc32/src/asm.S – Rev 3191 → 3211