WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/mips32/src/mips32.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32
 * @{
 */
/** @file
 */
 
#include <arch.h>
#include <arch/cp0.h>
#include <arch/exception.h>
#include <mm/as.h>
 
#include <userspace.h>
 
#include <memstr.h>
#include <proc/thread.h>
#include <proc/uarg.h>
#include <print.h>
#include <console/console.h>
#include <syscall/syscall.h>
#include <sysinfo/sysinfo.h>
 
#include <arch/interrupt.h>
#include <console/chardev.h>
#include <arch/barrier.h>
#include <arch/debugger.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <genarch/drivers/dsrln/dsrlnin.h>
#include <genarch/drivers/dsrln/dsrlnout.h>
#include <genarch/srln/srln.h>
#include <macros.h>
#include <config.h>
#include <string.h>
#include <arch/drivers/msim.h>
 
#include <arch/asm/regname.h>
 
/* Size of the code jumping to the exception handler code
 * - J+NOP
 */
#define EXCEPTION_JUMP_SIZE  8
 
#define TLB_EXC    ((char *) 0x80000000)
#define NORM_EXC   ((char *) 0x80000180)
#define CACHE_EXC  ((char *) 0x80000100)
 
 
/* Why the linker moves the variable 64K away in assembler
 * when not in .text section?
 */
 
/* Stack pointer saved when entering user mode */
uintptr_t supervisor_sp __attribute__ ((section (".text")));
 
count_t cpu_count = 0;
 
/** Performs mips32-specific initialization before main_bsp() is called. */
void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
{
    /* Setup usermode */
    init.cnt = bootinfo->cnt;
   
    count_t i;
    for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
        init.tasks[i].addr = bootinfo->tasks[i].addr;
        init.tasks[i].size = bootinfo->tasks[i].size;
        str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
            bootinfo->tasks[i].name);
    }
   
    for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
        if ((bootinfo->cpumap & (1 << i)) != 0)
            cpu_count++;
    }
}
 
void arch_pre_mm_init(void)
{
    /* It is not assumed by default */
    interrupts_disable();
   
    /* Initialize dispatch table */
    exception_init();
 
    /* Copy the exception vectors to the right places */
    memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
    smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
    memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
    smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
    memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
    smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
   
    /*
     * Switch to BEV normal level so that exception vectors point to the
     * kernel. Clear the error level.
     */
    cp0_status_write(cp0_status_read() &
        ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
   
    /*
     * Mask all interrupts
     */
    cp0_mask_all_int();
   
    debugger_init();
}
 
void arch_post_mm_init(void)
{
    interrupt_init();
   
#ifdef CONFIG_FB
    /* GXemul framebuffer */
    fb_properties_t gxemul_prop = {
        .addr = 0x12000000,
        .offset = 0,
        .x = 640,
        .y = 480,
        .scan = 1920,
        .visual = VISUAL_BGR_8_8_8,
    };
    fb_init(&gxemul_prop);
#else
#ifdef CONFIG_MIPS_PRN
    dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
#endif /* CONFIG_MIPS_PRN */
#endif /* CONFIG_FB */
}
 
void arch_post_cpu_init(void)
{
}
 
void arch_pre_smp_init(void)
{
}
 
void arch_post_smp_init(void)
{
#ifdef CONFIG_MIPS_KBD
    /*
     * Initialize the msim/GXemul keyboard port. Then initialize the serial line
     * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
     */
    dsrlnin_instance_t *dsrlnin_instance
        = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
    if (dsrlnin_instance) {
        srln_instance_t *srln_instance = srln_init();
        if (srln_instance) {
            indev_t *sink = stdin_wire();
            indev_t *srln = srln_wire(srln_instance, sink);
            dsrlnin_wire(dsrlnin_instance, srln);
            cp0_unmask_int(MSIM_KBD_IRQ);
        }
    }
   
    /*
     * This is the necessary evil until the userspace driver is entirely
     * self-sufficient.
     */
    sysinfo_set_item_val("kbd", NULL, true);
    sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ);
    sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS);
#endif
}
 
void calibrate_delay_loop(void)
{
}
 
void userspace(uspace_arg_t *kernel_uarg)
{
    /* EXL = 1, UM = 1, IE = 1 */
    cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
        cp0_status_um_bit | cp0_status_ie_enabled_bit));
    cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
    userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
        (uintptr_t) kernel_uarg->uspace_uarg,
        (uintptr_t) kernel_uarg->uspace_entry);
   
    while (1);
}
 
/** Perform mips32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
 
/** Perform mips32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
    supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
        SP_DELTA];
}
 
void after_thread_ran_arch(void)
{
}
 
/** Set thread-local-storage pointer
 *
 * We have it currently in K1, it is
 * possible to have it separately in the future.
 */
unative_t sys_tls_set(unative_t addr)
{
    return 0;
}
 
void arch_reboot(void)
{
    ___halt();
    while (1);
}
 
/** Construct function pointer
 *
 * @param fptr   function pointer structure
 * @param addr   function address
 * @param caller calling function address
 *
 * @return address of the function pointer
 *
 */
void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
{
    return addr;
}
 
void arch_grab_console(void)
{
#ifdef CONFIG_FB
    fb_redraw();
#endif
}
 
/** Return console to userspace
 *
 */
void arch_release_console(void)
{
}
 
/** @}
 */
 

Rev 4347	Rev 4348
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32	29	/** @addtogroup mips32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch.h>	35	#include <arch.h>
36	#include <arch/cp0.h>	36	#include <arch/cp0.h>
37	#include <arch/exception.h>	37	#include <arch/exception.h>
38	#include <mm/as.h>	38	#include <mm/as.h>
39		-
40	#include <userspace.h>	39	#include <userspace.h>
41	#include <arch/console.h>	-
42	#include <memstr.h>	40	#include <memstr.h>
43	#include <proc/thread.h>	41	#include <proc/thread.h>
44	#include <proc/uarg.h>	42	#include <proc/uarg.h>
45	#include <print.h>	43	#include <print.h>
-		44	#include <console/console.h>
46	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
47	#include <sysinfo/sysinfo.h>	46	#include <sysinfo/sysinfo.h>
48		-
49	#include <arch/interrupt.h>	47	#include <arch/interrupt.h>
50	#include <console/chardev.h>	48	#include <console/chardev.h>
51	#include <arch/barrier.h>	49	#include <arch/barrier.h>
52	#include <arch/debugger.h>	50	#include <arch/debugger.h>
53	#include <genarch/fb/fb.h>	51	#include <genarch/fb/fb.h>
54	#include <genarch/fb/visuals.h>	52	#include <genarch/fb/visuals.h>
55	#include <genarch/drivers/dsrln/dsrlnin.h>	53	#include <genarch/drivers/dsrln/dsrlnin.h>
56	#include <genarch/drivers/dsrln/dsrlnout.h>	54	#include <genarch/drivers/dsrln/dsrlnout.h>
57	#include <genarch/srln/srln.h>	55	#include <genarch/srln/srln.h>
58	#include <macros.h>	56	#include <macros.h>
59	#include <config.h>	57	#include <config.h>
60	#include <string.h>	58	#include <string.h>
61	#include <arch/drivers/msim.h>	59	#include <arch/drivers/msim.h>
62		-
63	#include <arch/asm/regname.h>	60	#include <arch/asm/regname.h>
64		61
65	/* Size of the code jumping to the exception handler code	62	/* Size of the code jumping to the exception handler code
66	* - J+NOP	63	* - J+NOP
67	*/	64	*/
68	#define EXCEPTION_JUMP_SIZE 8	65	#define EXCEPTION_JUMP_SIZE 8
69		66
70	#define TLB_EXC ((char *) 0x80000000)	67	#define TLB_EXC ((char *) 0x80000000)
71	#define NORM_EXC ((char *) 0x80000180)	68	#define NORM_EXC ((char *) 0x80000180)
72	#define CACHE_EXC ((char *) 0x80000100)	69	#define CACHE_EXC ((char *) 0x80000100)
73		70
74		71
75	/* Why the linker moves the variable 64K away in assembler	72	/* Why the linker moves the variable 64K away in assembler
76	* when not in .text section?	73	* when not in .text section?
77	*/	74	*/
78		75
79	/* Stack pointer saved when entering user mode */	76	/* Stack pointer saved when entering user mode */
80	uintptr_t supervisor_sp __attribute__ ((section (".text")));	77	uintptr_t supervisor_sp __attribute__ ((section (".text")));
81		78
82	count_t cpu_count = 0;	79	count_t cpu_count = 0;
83		80
84	/** Performs mips32-specific initialization before main_bsp() is called. */	81	/** Performs mips32-specific initialization before main_bsp() is called. */
85	void arch_pre_main(void entry __attribute__((unused)), bootinfo_t bootinfo)	82	void arch_pre_main(void entry __attribute__((unused)), bootinfo_t bootinfo)
86	{	83	{
87	/* Setup usermode */	84	/* Setup usermode */
88	init.cnt = bootinfo->cnt;	85	init.cnt = bootinfo->cnt;
89		86
90	count_t i;	87	count_t i;
91	for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {	88	for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
92	init.tasks[i].addr = bootinfo->tasks[i].addr;	89	init.tasks[i].addr = bootinfo->tasks[i].addr;
93	init.tasks[i].size = bootinfo->tasks[i].size;	90	init.tasks[i].size = bootinfo->tasks[i].size;
94	strncpy(init.tasks[i].name, bootinfo->tasks[i].name,	91	str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
95	CONFIG_TASK_NAME_BUFLEN);	92	bootinfo->tasks[i].name);
96	}	93	}
97		94
98	for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {	95	for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
99	if ((bootinfo->cpumap & (1 << i)) != 0)	96	if ((bootinfo->cpumap & (1 << i)) != 0)
100	cpu_count++;	97	cpu_count++;
101	}	98	}
102	}	99	}
103		100
104	void arch_pre_mm_init(void)	101	void arch_pre_mm_init(void)
105	{	102	{
106	/* It is not assumed by default */	103	/* It is not assumed by default */
107	interrupts_disable();	104	interrupts_disable();
108		105
109	/* Initialize dispatch table */	106	/* Initialize dispatch table */
110	exception_init();	107	exception_init();
111		108
112	/* Copy the exception vectors to the right places */	109	/* Copy the exception vectors to the right places */
113	memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);	110	memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
114	smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);	111	smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
115	memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);	112	memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
116	smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);	113	smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
117	memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);	114	memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
118	smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);	115	smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
119		116
120	/*	117	/*
121	* Switch to BEV normal level so that exception vectors point to the	118	* Switch to BEV normal level so that exception vectors point to the
122	* kernel. Clear the error level.	119	* kernel. Clear the error level.
123	*/	120	*/
124	cp0_status_write(cp0_status_read() &	121	cp0_status_write(cp0_status_read() &
125	~(cp0_status_bev_bootstrap_bit \| cp0_status_erl_error_bit));	122	~(cp0_status_bev_bootstrap_bit \| cp0_status_erl_error_bit));
126		123
127	/*	124	/*
128	* Mask all interrupts	125	* Mask all interrupts
129	*/	126	*/
130	cp0_mask_all_int();	127	cp0_mask_all_int();
131		128
132	debugger_init();	129	debugger_init();
133	}	130	}
134		131
135	void arch_post_mm_init(void)	132	void arch_post_mm_init(void)
136	{	133	{
137	interrupt_init();	134	interrupt_init();
138		135
139	#ifdef CONFIG_FB	136	#ifdef CONFIG_FB
140	/* GXemul framebuffer */	137	/* GXemul framebuffer */
141	fb_properties_t gxemul_prop = {	138	fb_properties_t gxemul_prop = {
142	.addr = 0x12000000,	139	.addr = 0x12000000,
143	.offset = 0,	140	.offset = 0,
144	.x = 640,	141	.x = 640,
145	.y = 480,	142	.y = 480,
146	.scan = 1920,	143	.scan = 1920,
147	.visual = VISUAL_BGR_8_8_8,	144	.visual = VISUAL_BGR_8_8_8,
148	};	145	};
149	fb_init(&gxemul_prop);	146	fb_init(&gxemul_prop);
150	#else	147	#else
151	#ifdef CONFIG_MIPS_PRN	148	#ifdef CONFIG_MIPS_PRN
152	dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);	149	dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
153	#endif /* CONFIG_MIPS_PRN */	150	#endif /* CONFIG_MIPS_PRN */
154	#endif /* CONFIG_FB */	151	#endif /* CONFIG_FB */
155	}	152	}
156		153
157	void arch_post_cpu_init(void)	154	void arch_post_cpu_init(void)
158	{	155	{
159	}	156	}
160		157
161	void arch_pre_smp_init(void)	158	void arch_pre_smp_init(void)
162	{	159	{
163	}	160	}
164		161
165	void arch_post_smp_init(void)	162	void arch_post_smp_init(void)
166	{	163	{
167	#ifdef CONFIG_MIPS_KBD	164	#ifdef CONFIG_MIPS_KBD
168	/*	165	/*
169	* Initialize the msim/GXemul keyboard port. Then initialize the serial line	166	* Initialize the msim/GXemul keyboard port. Then initialize the serial line
170	* module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.	167	* module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
171	*/	168	*/
-		169	dsrlnin_instance_t *dsrlnin_instance
172	indev_t kbrdin = dsrlnin_init((dsrlnin_t ) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);	170	= dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
173	if (kbrdin) {	171	if (dsrlnin_instance) {
-		172	srln_instance_t *srln_instance = srln_init();
174	srln_init(kbrdin);	173	if (srln_instance) {
-		174	indev_t *sink = stdin_wire();
-		175	indev_t *srln = srln_wire(srln_instance, sink);
-		176	dsrlnin_wire(dsrlnin_instance, srln);
175	cp0_unmask_int(MSIM_KBD_IRQ);	177	cp0_unmask_int(MSIM_KBD_IRQ);
-		178	}
176	}	179	}
177		180
178	/*	181	/*
179	* This is the necessary evil until the userspace driver is entirely	182	* This is the necessary evil until the userspace driver is entirely
180	* self-sufficient.	183	* self-sufficient.
181	*/	184	*/
182	sysinfo_set_item_val("kbd", NULL, true);	185	sysinfo_set_item_val("kbd", NULL, true);
183	sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ);	186	sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ);
184	sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS);	187	sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS);
185	#endif	188	#endif
186	}	189	}
187		190
188	void calibrate_delay_loop(void)	191	void calibrate_delay_loop(void)
189	{	192	{
190	}	193	}
191		194
192	void userspace(uspace_arg_t *kernel_uarg)	195	void userspace(uspace_arg_t *kernel_uarg)
193	{	196	{
194	/* EXL = 1, UM = 1, IE = 1 */	197	/* EXL = 1, UM = 1, IE = 1 */
195	cp0_status_write(cp0_status_read() \| (cp0_status_exl_exception_bit \|	198	cp0_status_write(cp0_status_read() \| (cp0_status_exl_exception_bit \|
196	cp0_status_um_bit \| cp0_status_ie_enabled_bit));	199	cp0_status_um_bit \| cp0_status_ie_enabled_bit));
197	cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);	200	cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
198	userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),	201	userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
199	(uintptr_t) kernel_uarg->uspace_uarg,	202	(uintptr_t) kernel_uarg->uspace_uarg,
200	(uintptr_t) kernel_uarg->uspace_entry);	203	(uintptr_t) kernel_uarg->uspace_entry);
201		204
202	while (1);	205	while (1);
203	}	206	}
204		207
205	/** Perform mips32 specific tasks needed before the new task is run. */	208	/** Perform mips32 specific tasks needed before the new task is run. */
206	void before_task_runs_arch(void)	209	void before_task_runs_arch(void)
207	{	210	{
208	}	211	}
209		212
210	/** Perform mips32 specific tasks needed before the new thread is scheduled. */	213	/** Perform mips32 specific tasks needed before the new thread is scheduled. */
211	void before_thread_runs_arch(void)	214	void before_thread_runs_arch(void)
212	{	215	{
213	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -	216	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
214	SP_DELTA];	217	SP_DELTA];
215	}	218	}
216		219
217	void after_thread_ran_arch(void)	220	void after_thread_ran_arch(void)
218	{	221	{
219	}	222	}
220		223
221	/** Set thread-local-storage pointer	224	/** Set thread-local-storage pointer
222	*	225	*
223	* We have it currently in K1, it is	226	* We have it currently in K1, it is
224	* possible to have it separately in the future.	227	* possible to have it separately in the future.
225	*/	228	*/
226	unative_t sys_tls_set(unative_t addr)	229	unative_t sys_tls_set(unative_t addr)
227	{	230	{
228	return 0;	231	return 0;
229	}	232	}
230		233
231	void arch_reboot(void)	234	void arch_reboot(void)
232	{	235	{
233	___halt();	236	___halt();
234	while (1);	237	while (1);
235	}	238	}
236		239
237	/** Construct function pointer	240	/** Construct function pointer
238	*	241	*
239	* @param fptr function pointer structure	242	* @param fptr function pointer structure
240	* @param addr function address	243	* @param addr function address
241	* @param caller calling function address	244	* @param caller calling function address
242	*	245	*
243	* @return address of the function pointer	246	* @return address of the function pointer
244	*	247	*
245	*/	248	*/
246	void arch_construct_function(fncptr_t fptr, void addr, void caller)	249	void arch_construct_function(fncptr_t fptr, void addr, void caller)
247	{	250	{
248	return addr;	251	return addr;
249	}	252	}
-		253
-		254	void arch_grab_console(void)
-		255	{
-		256	#ifdef CONFIG_FB
-		257	fb_redraw();
-		258	#endif
-		259	}
-		260
-		261	/** Return console to userspace
-		262	*
-		263	*/
-		264	void arch_release_console(void)
-		265	{
-		266	}
250		267
251	/** @}	268	/** @}
252	*/	269	*/
253		270

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(root)/branches/dynload/kernel/arch/mips32/src/mips32.c @ 4691 – Rev 4347 → 4348