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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32interrupt |
29 | /** @addtogroup mips32interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <arch/interrupt.h> |
36 | #include <arch/interrupt.h> |
37 | #include <arch/types.h> |
37 | #include <arch/types.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | #include <arch/cp0.h> |
39 | #include <arch/cp0.h> |
40 | #include <time/clock.h> |
40 | #include <time/clock.h> |
41 | #include <arch/drivers/arc.h> |
- | |
42 | #include <ipc/sysipc.h> |
41 | #include <ipc/sysipc.h> |
43 | #include <ddi/device.h> |
42 | #include <ddi/device.h> |
44 | 43 | ||
45 | #define IRQ_COUNT 8 |
44 | #define IRQ_COUNT 8 |
46 | #define TIMER_IRQ 7 |
45 | #define TIMER_IRQ 7 |
47 | 46 | ||
48 | function virtual_timer_fnc = NULL; |
47 | function virtual_timer_fnc = NULL; |
49 | static irq_t timer_irq; |
48 | static irq_t timer_irq; |
50 | 49 | ||
51 | /** Disable interrupts. |
50 | /** Disable interrupts. |
52 | * |
51 | * |
53 | * @return Old interrupt priority level. |
52 | * @return Old interrupt priority level. |
54 | */ |
53 | */ |
55 | ipl_t interrupts_disable(void) |
54 | ipl_t interrupts_disable(void) |
56 | { |
55 | { |
57 | ipl_t ipl = (ipl_t) cp0_status_read(); |
56 | ipl_t ipl = (ipl_t) cp0_status_read(); |
58 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
57 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
59 | return ipl; |
58 | return ipl; |
60 | } |
59 | } |
61 | 60 | ||
62 | /** Enable interrupts. |
61 | /** Enable interrupts. |
63 | * |
62 | * |
64 | * @return Old interrupt priority level. |
63 | * @return Old interrupt priority level. |
65 | */ |
64 | */ |
66 | ipl_t interrupts_enable(void) |
65 | ipl_t interrupts_enable(void) |
67 | { |
66 | { |
68 | ipl_t ipl = (ipl_t) cp0_status_read(); |
67 | ipl_t ipl = (ipl_t) cp0_status_read(); |
69 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
68 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
70 | return ipl; |
69 | return ipl; |
71 | } |
70 | } |
72 | 71 | ||
73 | /** Restore interrupt priority level. |
72 | /** Restore interrupt priority level. |
74 | * |
73 | * |
75 | * @param ipl Saved interrupt priority level. |
74 | * @param ipl Saved interrupt priority level. |
76 | */ |
75 | */ |
77 | void interrupts_restore(ipl_t ipl) |
76 | void interrupts_restore(ipl_t ipl) |
78 | { |
77 | { |
79 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
78 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
80 | } |
79 | } |
81 | 80 | ||
82 | /** Read interrupt priority level. |
81 | /** Read interrupt priority level. |
83 | * |
82 | * |
84 | * @return Current interrupt priority level. |
83 | * @return Current interrupt priority level. |
85 | */ |
84 | */ |
86 | ipl_t interrupts_read(void) |
85 | ipl_t interrupts_read(void) |
87 | { |
86 | { |
88 | return cp0_status_read(); |
87 | return cp0_status_read(); |
89 | } |
88 | } |
90 | 89 | ||
91 | /* TODO: This is SMP unsafe!!! */ |
90 | /* TODO: This is SMP unsafe!!! */ |
92 | uint32_t count_hi = 0; |
91 | uint32_t count_hi = 0; |
93 | static unsigned long nextcount; |
92 | static unsigned long nextcount; |
94 | static unsigned long lastcount; |
93 | static unsigned long lastcount; |
95 | 94 | ||
96 | /** Start hardware clock */ |
95 | /** Start hardware clock */ |
97 | static void timer_start(void) |
96 | static void timer_start(void) |
98 | { |
97 | { |
99 | lastcount = cp0_count_read(); |
98 | lastcount = cp0_count_read(); |
100 | nextcount = cp0_compare_value + cp0_count_read(); |
99 | nextcount = cp0_compare_value + cp0_count_read(); |
101 | cp0_compare_write(nextcount); |
100 | cp0_compare_write(nextcount); |
102 | } |
101 | } |
103 | 102 | ||
104 | static irq_ownership_t timer_claim(void) |
103 | static irq_ownership_t timer_claim(void) |
105 | { |
104 | { |
106 | return IRQ_ACCEPT; |
105 | return IRQ_ACCEPT; |
107 | } |
106 | } |
108 | 107 | ||
109 | static void timer_irq_handler(irq_t *irq, void *arg, ...) |
108 | static void timer_irq_handler(irq_t *irq, void *arg, ...) |
110 | { |
109 | { |
111 | unsigned long drift; |
110 | unsigned long drift; |
112 | 111 | ||
113 | if (cp0_count_read() < lastcount) |
112 | if (cp0_count_read() < lastcount) |
114 | /* Count overflow detected */ |
113 | /* Count overflow detected */ |
115 | count_hi++; |
114 | count_hi++; |
116 | lastcount = cp0_count_read(); |
115 | lastcount = cp0_count_read(); |
117 | 116 | ||
118 | drift = cp0_count_read() - nextcount; |
117 | drift = cp0_count_read() - nextcount; |
119 | while (drift > cp0_compare_value) { |
118 | while (drift > cp0_compare_value) { |
120 | drift -= cp0_compare_value; |
119 | drift -= cp0_compare_value; |
121 | CPU->missed_clock_ticks++; |
120 | CPU->missed_clock_ticks++; |
122 | } |
121 | } |
123 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
122 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
124 | cp0_compare_write(nextcount); |
123 | cp0_compare_write(nextcount); |
125 | 124 | ||
126 | /* |
125 | /* |
127 | * We are holding a lock which prevents preemption. |
126 | * We are holding a lock which prevents preemption. |
128 | * Release the lock, call clock() and reacquire the lock again. |
127 | * Release the lock, call clock() and reacquire the lock again. |
129 | */ |
128 | */ |
130 | spinlock_unlock(&irq->lock); |
129 | spinlock_unlock(&irq->lock); |
131 | clock(); |
130 | clock(); |
132 | spinlock_lock(&irq->lock); |
131 | spinlock_lock(&irq->lock); |
133 | 132 | ||
134 | if (virtual_timer_fnc != NULL) |
133 | if (virtual_timer_fnc != NULL) |
135 | virtual_timer_fnc(); |
134 | virtual_timer_fnc(); |
136 | } |
135 | } |
137 | 136 | ||
138 | /* Initialize basic tables for exception dispatching */ |
137 | /* Initialize basic tables for exception dispatching */ |
139 | void interrupt_init(void) |
138 | void interrupt_init(void) |
140 | { |
139 | { |
141 | irq_init(IRQ_COUNT, IRQ_COUNT); |
140 | irq_init(IRQ_COUNT, IRQ_COUNT); |
142 | 141 | ||
143 | irq_initialize(&timer_irq); |
142 | irq_initialize(&timer_irq); |
144 | timer_irq.devno = device_assign_devno(); |
143 | timer_irq.devno = device_assign_devno(); |
145 | timer_irq.inr = TIMER_IRQ; |
144 | timer_irq.inr = TIMER_IRQ; |
146 | timer_irq.claim = timer_claim; |
145 | timer_irq.claim = timer_claim; |
147 | timer_irq.handler = timer_irq_handler; |
146 | timer_irq.handler = timer_irq_handler; |
148 | irq_register(&timer_irq); |
147 | irq_register(&timer_irq); |
149 | 148 | ||
150 | timer_start(); |
149 | timer_start(); |
151 | cp0_unmask_int(TIMER_IRQ); |
150 | cp0_unmask_int(TIMER_IRQ); |
152 | } |
151 | } |
153 | 152 | ||
154 | /** @} |
153 | /** @} |
155 | */ |
154 | */ |
156 | 155 |