WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/mips32/include/mm/tlb.h


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm   
 * @{
 */
/** @file
 */
 
#ifndef KERN_mips32_TLB_H_
#define KERN_mips32_TLB_H_
 
#include <arch/types.h>
#include <typedefs.h>
#include <arch/mm/asid.h>
#include <arch/exception.h>
 
#ifdef TLBCNT
#   define TLB_ENTRY_COUNT      TLBCNT
#else
#   define TLB_ENTRY_COUNT      48
#endif
 
#define TLB_WIRED       1
#define TLB_KSTACK_WIRED_INDEX  0
 
#define TLB_PAGE_MASK_4K    (0x000 << 13)
#define TLB_PAGE_MASK_16K   (0x003 << 13)
#define TLB_PAGE_MASK_64K   (0x00f << 13)
#define TLB_PAGE_MASK_256K  (0x03f << 13)
#define TLB_PAGE_MASK_1M    (0x0ff << 13)
#define TLB_PAGE_MASK_4M    (0x3ff << 13)
#define TLB_PAGE_MASK_16M   (0xfff << 13)
 
#define PAGE_UNCACHED           2
#define PAGE_CACHEABLE_EXC_WRITE    5
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned : 2;       /* zero */
        unsigned pfn : 24;  /* frame number */
        unsigned c : 3;     /* cache coherency attribute */
        unsigned d : 1;     /* dirty/write-protect bit */
        unsigned v : 1;     /* valid bit */
        unsigned g : 1;     /* global bit */
#else
        unsigned g : 1;     /* global bit */
        unsigned v : 1;     /* valid bit */
        unsigned d : 1;     /* dirty/write-protect bit */
        unsigned c : 3;     /* cache coherency attribute */
        unsigned pfn : 24;  /* frame number */
        unsigned : 2;       /* zero */
#endif
    } __attribute__ ((packed));
    uint32_t value;
} entry_lo_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned vpn2 : 19;
        unsigned : 5;
        unsigned asid : 8;
#else
        unsigned asid : 8;
        unsigned : 5;
        unsigned vpn2 : 19;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} entry_hi_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned : 7;
        unsigned mask : 12;
        unsigned : 13;
#else
        unsigned : 13;
        unsigned mask : 12;
        unsigned : 7;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} page_mask_t;
 
typedef union {
    struct {
#ifdef BIG_ENDIAN
        unsigned p : 1;
        unsigned : 27;
        unsigned index : 4;
#else
        unsigned index : 4;
        unsigned : 27;
        unsigned p : 1;
#endif
    } __attribute__ ((packed));
    uint32_t value;
} tlb_index_t;
 
/** Probe TLB for Matching Entry
 *
 * Probe TLB for Matching Entry.
 */
static inline void tlbp(void)
{
    asm volatile ("tlbp\n\t");
}
 
 
/** Read Indexed TLB Entry
 *
 * Read Indexed TLB Entry.
 */
static inline void tlbr(void)
{
    asm volatile ("tlbr\n\t");
}
 
/** Write Indexed TLB Entry
 *
 * Write Indexed TLB Entry.
 */
static inline void tlbwi(void)
{
    asm volatile ("tlbwi\n\t");
}
 
/** Write Random TLB Entry
 *
 * Write Random TLB Entry.
 */
static inline void tlbwr(void)
{
    asm volatile ("tlbwr\n\t");
}
 
#define tlb_invalidate(asid)    tlb_invalidate_asid(asid)
 
extern void tlb_invalid(istate_t *istate);
extern void tlb_refill(istate_t *istate);
extern void tlb_modified(istate_t *istate);
extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
 
#endif
 
/** @}
 */
 

Rev 2927	Rev 3403
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_mips32_TLB_H_	35	#ifndef KERN_mips32_TLB_H_
36	#define KERN_mips32_TLB_H_	36	#define KERN_mips32_TLB_H_
37		37
-		38	#include <arch/types.h>
-		39	#include <typedefs.h>
-		40	#include <arch/mm/asid.h>
38	#include <arch/exception.h>	41	#include <arch/exception.h>
39		42
40	#ifdef TLBCNT	43	#ifdef TLBCNT
41	# define TLB_ENTRY_COUNT TLBCNT	44	# define TLB_ENTRY_COUNT TLBCNT
42	#else	45	#else
43	# define TLB_ENTRY_COUNT 48	46	# define TLB_ENTRY_COUNT 48
44	#endif	47	#endif
45		48
46	#define TLB_WIRED 1	49	#define TLB_WIRED 1
47	#define TLB_KSTACK_WIRED_INDEX 0	50	#define TLB_KSTACK_WIRED_INDEX 0
48		51
-		52	#define TLB_PAGE_MASK_4K (0x000 << 13)
49	#define TLB_PAGE_MASK_16K (0x3<<13)	53	#define TLB_PAGE_MASK_16K (0x003 << 13)
-		54	#define TLB_PAGE_MASK_64K (0x00f << 13)
-		55	#define TLB_PAGE_MASK_256K (0x03f << 13)
-		56	#define TLB_PAGE_MASK_1M (0x0ff << 13)
-		57	#define TLB_PAGE_MASK_4M (0x3ff << 13)
-		58	#define TLB_PAGE_MASK_16M (0xfff << 13)
50		59
51	#define PAGE_UNCACHED 2	60	#define PAGE_UNCACHED 2
52	#define PAGE_CACHEABLE_EXC_WRITE 5	61	#define PAGE_CACHEABLE_EXC_WRITE 5
53		62
54	typedef union {	63	typedef union {
55	struct {	64	struct {
56	#ifdef BIG_ENDIAN	65	#ifdef BIG_ENDIAN
57	unsigned : 2; /* zero */	66	unsigned : 2; /* zero */
58	unsigned pfn : 24; /* frame number */	67	unsigned pfn : 24; /* frame number */
59	unsigned c : 3; /* cache coherency attribute */	68	unsigned c : 3; /* cache coherency attribute */
60	unsigned d : 1; /* dirty/write-protect bit */	69	unsigned d : 1; /* dirty/write-protect bit */
61	unsigned v : 1; /* valid bit */	70	unsigned v : 1; /* valid bit */
62	unsigned g : 1; /* global bit */	71	unsigned g : 1; /* global bit */
63	#else	72	#else
64	unsigned g : 1; /* global bit */	73	unsigned g : 1; /* global bit */
65	unsigned v : 1; /* valid bit */	74	unsigned v : 1; /* valid bit */
66	unsigned d : 1; /* dirty/write-protect bit */	75	unsigned d : 1; /* dirty/write-protect bit */
67	unsigned c : 3; /* cache coherency attribute */	76	unsigned c : 3; /* cache coherency attribute */
68	unsigned pfn : 24; /* frame number */	77	unsigned pfn : 24; /* frame number */
69	unsigned : 2; /* zero */	78	unsigned : 2; /* zero */
70	#endif	79	#endif
71	} __attribute__ ((packed));	80	} __attribute__ ((packed));
72	uint32_t value;	81	uint32_t value;
73	} entry_lo_t;	82	} entry_lo_t;
74		83
75	typedef union {	84	typedef union {
76	struct {	85	struct {
77	#ifdef BIG_ENDIAN	86	#ifdef BIG_ENDIAN
78	unsigned vpn2 : 19;	87	unsigned vpn2 : 19;
79	unsigned : 5;	88	unsigned : 5;
80	unsigned asid : 8;	89	unsigned asid : 8;
81	#else	90	#else
82	unsigned asid : 8;	91	unsigned asid : 8;
83	unsigned : 5;	92	unsigned : 5;
84	unsigned vpn2 : 19;	93	unsigned vpn2 : 19;
85	#endif	94	#endif
86	} __attribute__ ((packed));	95	} __attribute__ ((packed));
87	uint32_t value;	96	uint32_t value;
88	} entry_hi_t;	97	} entry_hi_t;
89		98
90	typedef union {	99	typedef union {
91	struct {	100	struct {
92	#ifdef BIG_ENDIAN	101	#ifdef BIG_ENDIAN
93	unsigned : 7;	102	unsigned : 7;
94	unsigned mask : 12;	103	unsigned mask : 12;
95	unsigned : 13;	104	unsigned : 13;
96	#else	105	#else
97	unsigned : 13;	106	unsigned : 13;
98	unsigned mask : 12;	107	unsigned mask : 12;
99	unsigned : 7;	108	unsigned : 7;
100	#endif	109	#endif
101	} __attribute__ ((packed));	110	} __attribute__ ((packed));
102	uint32_t value;	111	uint32_t value;
103	} page_mask_t;	112	} page_mask_t;
104		113
105	typedef union {	114	typedef union {
106	struct {	115	struct {
107	#ifdef BIG_ENDIAN	116	#ifdef BIG_ENDIAN
108	unsigned p : 1;	117	unsigned p : 1;
109	unsigned : 27;	118	unsigned : 27;
110	unsigned index : 4;	119	unsigned index : 4;
111	#else	120	#else
112	unsigned index : 4;	121	unsigned index : 4;
113	unsigned : 27;	122	unsigned : 27;
114	unsigned p : 1;	123	unsigned p : 1;
115	#endif	124	#endif
116	} __attribute__ ((packed));	125	} __attribute__ ((packed));
117	uint32_t value;	126	uint32_t value;
118	} tlb_index_t;	127	} tlb_index_t;
119		128
120	/** Probe TLB for Matching Entry	129	/** Probe TLB for Matching Entry
121	*	130	*
122	* Probe TLB for Matching Entry.	131	* Probe TLB for Matching Entry.
123	*/	132	*/
124	static inline void tlbp(void)	133	static inline void tlbp(void)
125	{	134	{
126	asm volatile ("tlbp\n\t");	135	asm volatile ("tlbp\n\t");
127	}	136	}
128		137
129		138
130	/** Read Indexed TLB Entry	139	/** Read Indexed TLB Entry
131	*	140	*
132	* Read Indexed TLB Entry.	141	* Read Indexed TLB Entry.
133	*/	142	*/
134	static inline void tlbr(void)	143	static inline void tlbr(void)
135	{	144	{
136	asm volatile ("tlbr\n\t");	145	asm volatile ("tlbr\n\t");
137	}	146	}
138		147
139	/** Write Indexed TLB Entry	148	/** Write Indexed TLB Entry
140	*	149	*
141	* Write Indexed TLB Entry.	150	* Write Indexed TLB Entry.
142	*/	151	*/
143	static inline void tlbwi(void)	152	static inline void tlbwi(void)
144	{	153	{
145	asm volatile ("tlbwi\n\t");	154	asm volatile ("tlbwi\n\t");
146	}	155	}
147		156
148	/** Write Random TLB Entry	157	/** Write Random TLB Entry
149	*	158	*
150	* Write Random TLB Entry.	159	* Write Random TLB Entry.
151	*/	160	*/
152	static inline void tlbwr(void)	161	static inline void tlbwr(void)
153	{	162	{
154	asm volatile ("tlbwr\n\t");	163	asm volatile ("tlbwr\n\t");
155	}	164	}
156		165
157	#define tlb_invalidate(asid) tlb_invalidate_asid(asid)	166	#define tlb_invalidate(asid) tlb_invalidate_asid(asid)
158		167
159	extern void tlb_invalid(istate_t *istate);	168	extern void tlb_invalid(istate_t *istate);
160	extern void tlb_refill(istate_t *istate);	169	extern void tlb_refill(istate_t *istate);
161	extern void tlb_modified(istate_t *istate);	170	extern void tlb_modified(istate_t *istate);
-		171	extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
-		172	extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
162		173
163	#endif	174	#endif
164		175
165	/** @}	176	/** @}
166	*/	177	*/
167		178

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(root)/branches/dynload/kernel/arch/mips32/include/mm/tlb.h @ 4346 – Rev 2927 → 3403