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1
/*
1
/*
2
 * Copyright (c) 2005 Jakub Jermar
2
 * Copyright (c) 2005 Jakub Jermar
3
 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
/** @addtogroup ia64
29
/** @addtogroup ia64
30
 * @{
30
 * @{
31
 */
31
 */
32
/** @file
32
/** @file
33
 */
33
 */
34
 
34
 
35
#include <arch.h>
35
#include <arch.h>
36
#include <arch/ski/ski.h>
36
#include <arch/ski/ski.h>
37
#include <arch/drivers/it.h>
37
#include <arch/drivers/it.h>
38
#include <arch/interrupt.h>
38
#include <arch/interrupt.h>
39
#include <arch/barrier.h>
39
#include <arch/barrier.h>
40
#include <arch/asm.h>
40
#include <arch/asm.h>
41
#include <arch/register.h>
41
#include <arch/register.h>
42
#include <arch/types.h>
42
#include <arch/types.h>
43
#include <arch/context.h>
43
#include <arch/context.h>
44
#include <arch/stack.h>
44
#include <arch/stack.h>
45
#include <arch/mm/page.h>
45
#include <arch/mm/page.h>
46
#include <mm/as.h>
46
#include <mm/as.h>
47
#include <config.h>
47
#include <config.h>
48
#include <userspace.h>
48
#include <userspace.h>
49
#include <console/console.h>
49
#include <console/console.h>
50
#include <proc/uarg.h>
50
#include <proc/uarg.h>
51
#include <syscall/syscall.h>
51
#include <syscall/syscall.h>
52
#include <ddi/irq.h>
52
#include <ddi/irq.h>
53
#include <ddi/device.h>
53
#include <ddi/device.h>
54
#include <arch/bootinfo.h>
54
#include <arch/bootinfo.h>
55
#include <arch/drivers/ega.h>
55
#include <genarch/drivers/legacy/ia32/io.h>
56
#include <genarch/drivers/ega/ega.h>
56
#include <genarch/drivers/ega/ega.h>
57
#include <genarch/kbd/i8042.h>
57
#include <genarch/kbd/i8042.h>
58
#include <genarch/kbd/ns16550.h>
58
#include <genarch/kbd/ns16550.h>
59
#include <smp/smp.h>
59
#include <smp/smp.h>
60
#include <smp/ipi.h>
60
#include <smp/ipi.h>
61
#include <arch/atomic.h>
61
#include <arch/atomic.h>
62
#include <panic.h>
62
#include <panic.h>
63
#include <print.h>
63
#include <print.h>
64
#include <sysinfo/sysinfo.h>
64
#include <sysinfo/sysinfo.h>
65
 
65
 
66
/* NS16550 as a COM 1 */
66
/* NS16550 as a COM 1 */
67
#define NS16550_IRQ (4 + LEGACY_INTERRUPT_BASE)
67
#define NS16550_IRQ (4 + LEGACY_INTERRUPT_BASE)
68
#define NS16550_PORT    0x3f8
-
 
69
 
68
 
70
bootinfo_t *bootinfo;
69
bootinfo_t *bootinfo;
71
 
70
 
72
static uint64_t iosapic_base = 0xfec00000;
71
static uint64_t iosapic_base = 0xfec00000;
73
 
72
 
74
void arch_pre_main(void)
73
void arch_pre_main(void)
75
{
74
{
76
    /* Setup usermode init tasks. */
75
    /* Setup usermode init tasks. */
77
 
76
 
78
    unsigned int i;
77
    unsigned int i;
79
   
78
   
80
    init.cnt = bootinfo->taskmap.count;
79
    init.cnt = bootinfo->taskmap.count;
81
   
80
   
82
    for (i = 0; i < init.cnt; i++) {
81
    for (i = 0; i < init.cnt; i++) {
83
        init.tasks[i].addr =
82
        init.tasks[i].addr =
84
            ((unsigned long) bootinfo->taskmap.tasks[i].addr) |
83
            ((unsigned long) bootinfo->taskmap.tasks[i].addr) |
85
            VRN_MASK;
84
            VRN_MASK;
86
        init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
85
        init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
87
    }
86
    }
88
}
87
}
89
 
88
 
90
void arch_pre_mm_init(void)
89
void arch_pre_mm_init(void)
91
{
90
{
92
    /*
91
    /*
93
     * Set Interruption Vector Address (i.e. location of interruption vector
92
     * Set Interruption Vector Address (i.e. location of interruption vector
94
     * table).
93
     * table).
95
     */
94
     */
96
    iva_write((uintptr_t) &ivt);
95
    iva_write((uintptr_t) &ivt);
97
    srlz_d();
96
    srlz_d();
98
   
97
   
99
}
98
}
100
 
99
 
101
static void iosapic_init(void)
100
static void iosapic_init(void)
102
{
101
{
103
    uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base)) | FW_OFFSET;
102
    uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base)) | FW_OFFSET;
104
    int i;
103
    int i;
105
   
104
   
106
    int myid, myeid;
105
    int myid, myeid;
107
   
106
   
108
    myid = ia64_get_cpu_id();
107
    myid = ia64_get_cpu_id();
109
    myeid = ia64_get_cpu_eid();
108
    myeid = ia64_get_cpu_eid();
110
 
109
 
111
    for (i = 0; i < 16; i++) {
110
    for (i = 0; i < 16; i++) {
112
        if (i == 2)
111
        if (i == 2)
113
            continue;    /* Disable Cascade interrupt */
112
            continue;    /* Disable Cascade interrupt */
114
        ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i;
113
        ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i;
115
        srlz_d();
114
        srlz_d();
116
        ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i;
115
        ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i;
117
        srlz_d();
116
        srlz_d();
118
        ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1;
117
        ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1;
119
        srlz_d();
118
        srlz_d();
120
        ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) |
119
        ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) |
121
            myeid << (48 - 32);
120
            myeid << (48 - 32);
122
        srlz_d();
121
        srlz_d();
123
    }
122
    }
124
 
123
 
125
}
124
}
126
 
125
 
127
 
126
 
128
void arch_post_mm_init(void)
127
void arch_post_mm_init(void)
129
{
128
{
130
    if (config.cpu_active == 1) {
129
    if (config.cpu_active == 1) {
131
        iosapic_init();
130
        iosapic_init();
132
        irq_init(INR_COUNT, INR_COUNT);
131
        irq_init(INR_COUNT, INR_COUNT);
133
#ifdef SKI
132
#ifdef SKI
134
        ski_init_console();
133
        ski_init_console();
135
#else
134
#else
136
        ega_init(EGA_BASE, EGA_VIDEORAM);
135
        ega_init(EGA_BASE, EGA_VIDEORAM);
137
#endif
136
#endif
138
    }
137
    }
139
    it_init();
138
    it_init();
140
       
139
       
141
}
140
}
142
 
141
 
143
void arch_post_cpu_init(void)
142
void arch_post_cpu_init(void)
144
{
143
{
145
}
144
}
146
 
145
 
147
void arch_pre_smp_init(void)
146
void arch_pre_smp_init(void)
148
{
147
{
149
}
148
}
150
 
149
 
151
void arch_post_smp_init(void)
150
void arch_post_smp_init(void)
152
{
151
{
153
    /*
152
    /*
154
     * Create thread that polls keyboard.
153
     * Create thread that polls keyboard.
155
     */
154
     */
156
#ifdef SKI
155
#ifdef SKI
157
    thread_t *t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
156
    thread_t *t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
158
    if (!t)
157
    if (!t)
159
        panic("Cannot create kkbdpoll.");
158
        panic("Cannot create kkbdpoll.");
160
    thread_ready(t);
159
    thread_ready(t);
161
#endif      
160
#endif      
162
 
161
 
163
#ifdef I460GX
162
#ifdef I460GX
164
    devno_t kbd = device_assign_devno();
163
    devno_t devno = device_assign_devno();
-
 
164
    inr_t inr;
165
 
165
 
166
#ifdef CONFIG_NS16550
166
#ifdef CONFIG_NS16550
-
 
167
    inr = NS16550_IRQ;
167
    ns16550_init(kbd, NS16550_PORT, NS16550_IRQ, NULL, NULL);
168
    (void) ns16550_init((ns16550_t *)NS16550_BASE, devno, inr, NULL, NULL);
-
 
169
    sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
-
 
170
    sysinfo_set_item_val("kbd.port", NULL, (uintptr_t)NS16550_BASE);
168
#else
171
#else
-
 
172
    inr = IRQ_KBD;
169
    devno_t mouse = device_assign_devno();
173
    (void) i8042_init((i8042_t *)I8042_BASE, devno, inr);
170
    i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE);
174
    sysinfo_set_item_val("kbd.type", NULL, KBD_LEGACY);
171
#endif
175
#endif
-
 
176
    sysinfo_set_item_val("kbd", NULL, true);
-
 
177
    sysinfo_set_item_val("kbd.devno", NULL, devno);
-
 
178
    sysinfo_set_item_val("kbd.inr", NULL, inr);
172
#endif
179
#endif
173
 
180
 
174
    sysinfo_set_item_val("ia64_iospace", NULL, true);
181
    sysinfo_set_item_val("ia64_iospace", NULL, true);
175
    sysinfo_set_item_val("ia64_iospace.address", NULL, true);
182
    sysinfo_set_item_val("ia64_iospace.address", NULL, true);
176
    sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET);
183
    sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET);
177
}
184
}
178
 
185
 
179
 
186
 
180
/** Enter userspace and never return. */
187
/** Enter userspace and never return. */
181
void userspace(uspace_arg_t *kernel_uarg)
188
void userspace(uspace_arg_t *kernel_uarg)
182
{
189
{
183
    psr_t psr;
190
    psr_t psr;
184
    rsc_t rsc;
191
    rsc_t rsc;
185
 
192
 
186
    psr.value = psr_read();
193
    psr.value = psr_read();
187
    psr.cpl = PL_USER;
194
    psr.cpl = PL_USER;
188
    psr.i = true;           /* start with interrupts enabled */
195
    psr.i = true;           /* start with interrupts enabled */
189
    psr.ic = true;
196
    psr.ic = true;
190
    psr.ri = 0;         /* start with instruction #0 */
197
    psr.ri = 0;         /* start with instruction #0 */
191
    psr.bn = 1;         /* start in bank 0 */
198
    psr.bn = 1;         /* start in bank 0 */
192
 
199
 
193
    asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
200
    asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
194
    rsc.loadrs = 0;
201
    rsc.loadrs = 0;
195
    rsc.be = false;
202
    rsc.be = false;
196
    rsc.pl = PL_USER;
203
    rsc.pl = PL_USER;
197
    rsc.mode = 3;           /* eager mode */
204
    rsc.mode = 3;           /* eager mode */
198
 
205
 
199
    switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
206
    switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
200
        ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE -
207
        ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE -
201
        ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
208
        ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
202
        ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE,
209
        ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE,
203
        (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
210
        (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
204
 
211
 
205
    while (1)
212
    while (1)
206
        ;
213
        ;
207
}
214
}
208
 
215
 
209
/** Set thread-local-storage pointer.
216
/** Set thread-local-storage pointer.
210
 *
217
 *
211
 * We use r13 (a.k.a. tp) for this purpose.
218
 * We use r13 (a.k.a. tp) for this purpose.
212
 */
219
 */
213
unative_t sys_tls_set(unative_t addr)
220
unative_t sys_tls_set(unative_t addr)
214
{
221
{
215
        return 0;
222
        return 0;
216
}
223
}
217
 
224
 
218
/** Acquire console back for kernel
225
/** Acquire console back for kernel
219
 *
226
 *
220
 */
227
 */
221
void arch_grab_console(void)
228
void arch_grab_console(void)
222
{
229
{
223
#ifdef SKI
230
#ifdef SKI
224
    ski_kbd_grab();
231
    ski_kbd_grab();
225
#else
-
 
226
#ifdef CONFIG_NS16550
-
 
227
    ns16550_grab();
-
 
228
#else
-
 
229
    i8042_grab();
-
 
230
#endif
-
 
231
#endif
232
#endif
232
}
233
}
233
 
234
 
234
/** Return console to userspace
235
/** Return console to userspace
235
 *
236
 *
236
 */
237
 */
237
void arch_release_console(void)
238
void arch_release_console(void)
238
{
239
{
239
#ifdef SKI
240
#ifdef SKI
240
    ski_kbd_release();
241
    ski_kbd_release();
241
#else
-
 
242
#ifdef CONFIG_NS16550
-
 
243
    ns16550_release();
-
 
244
#else
-
 
245
    i8042_release();
-
 
246
#endif
-
 
247
#endif
242
#endif
248
}
243
}
249
 
244
 
250
void arch_reboot(void)
245
void arch_reboot(void)
251
{
246
{
252
    pio_write_8(0x64, 0xfe);
247
    pio_write_8((ioport8_t *)0x64, 0xfe);
253
    while (1)
248
    while (1)
254
        ;
249
        ;
255
}
250
}
256
 
251
 
257
/** Construct function pointer
252
/** Construct function pointer
258
 *
253
 *
259
 * @param fptr   function pointer structure
254
 * @param fptr   function pointer structure
260
 * @param addr   function address
255
 * @param addr   function address
261
 * @param caller calling function address
256
 * @param caller calling function address
262
 *
257
 *
263
 * @return address of the function pointer
258
 * @return address of the function pointer
264
 *
259
 *
265
 */
260
 */
266
void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
261
void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
267
{
262
{
268
    fptr->fnc = (unative_t) addr;
263
    fptr->fnc = (unative_t) addr;
269
    fptr->gp = ((unative_t *) caller)[1];
264
    fptr->gp = ((unative_t *) caller)[1];
270
   
265
   
271
    return (void *) fptr;
266
    return (void *) fptr;
272
}
267
}
273
 
268
 
274
/** @}
269
/** @}
275
 */
270
 */
276
 
271