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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ia64 |
29 | /** @addtogroup ia64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | /** Interval Timer driver. */ |
35 | /** Interval Timer driver. */ |
36 | 36 | ||
37 | #include <arch/drivers/it.h> |
37 | #include <arch/drivers/it.h> |
38 | #include <arch/interrupt.h> |
38 | #include <arch/interrupt.h> |
39 | #include <arch/register.h> |
39 | #include <arch/register.h> |
40 | #include <arch/asm.h> |
40 | #include <arch/asm.h> |
41 | #include <arch/barrier.h> |
41 | #include <arch/barrier.h> |
42 | #include <time/clock.h> |
42 | #include <time/clock.h> |
43 | #include <ddi/irq.h> |
43 | #include <ddi/irq.h> |
44 | #include <ddi/device.h> |
44 | #include <ddi/device.h> |
45 | #include <arch.h> |
45 | #include <arch.h> |
46 | 46 | ||
47 | #define IT_SERVICE_CLOCKS 64 |
47 | #define IT_SERVICE_CLOCKS 64 |
48 | 48 | ||
- | 49 | #define FREQ_NUMERATOR_SHIFT 32 |
|
- | 50 | #define FREQ_NUMERATOR_MASK 0xffffffff00000000LL |
|
- | 51 | ||
- | 52 | #define FREQ_DENOMINATOR_SHIFT 0 |
|
- | 53 | #define FREQ_DENOMINATOR_MASK 0xffffffffLL |
|
- | 54 | ||
- | 55 | ||
- | 56 | uint64_t it_delta; |
|
- | 57 | ||
- | 58 | ||
49 | static irq_t it_irq; |
59 | static irq_t it_irq; |
50 | 60 | ||
51 | static irq_ownership_t it_claim(void); |
61 | static irq_ownership_t it_claim(void); |
52 | static void it_interrupt(irq_t *irq, void *arg, ...); |
62 | static void it_interrupt(irq_t *irq, void *arg, ...); |
53 | 63 | ||
54 | /** Initialize Interval Timer. */ |
64 | /** Initialize Interval Timer. */ |
55 | void it_init(void) |
65 | void it_init(void) |
56 | { |
66 | { |
57 | cr_itv_t itv; |
67 | cr_itv_t itv; |
58 | 68 | ||
- | 69 | if(config.cpu_active==1) |
|
- | 70 | { |
|
59 | irq_initialize(&it_irq); |
71 | irq_initialize(&it_irq); |
60 | it_irq.inr = INTERRUPT_TIMER; |
72 | it_irq.inr = INTERRUPT_TIMER; |
61 | it_irq.devno = device_assign_devno(); |
73 | it_irq.devno = device_assign_devno(); |
62 | it_irq.claim = it_claim; |
74 | it_irq.claim = it_claim; |
63 | it_irq.handler = it_interrupt; |
75 | it_irq.handler = it_interrupt; |
64 | irq_register(&it_irq); |
76 | irq_register(&it_irq); |
- | 77 | ||
- | 78 | uint64_t base_freq; |
|
- | 79 | base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >> FREQ_NUMERATOR_SHIFT; |
|
- | 80 | base_freq *= bootinfo->sys_freq; |
|
- | 81 | base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >> FREQ_DENOMINATOR_SHIFT; |
|
- | 82 | ||
- | 83 | it_delta = base_freq /HZ; |
|
- | 84 | ||
- | 85 | } |
|
65 | 86 | ||
66 | /* initialize Interval Timer external interrupt vector */ |
87 | /* initialize Interval Timer external interrupt vector */ |
67 | itv.value = itv_read(); |
88 | itv.value = itv_read(); |
68 | itv.vector = INTERRUPT_TIMER; |
89 | itv.vector = INTERRUPT_TIMER; |
69 | itv.m = 0; |
90 | itv.m = 0; |
70 | itv_write(itv.value); |
91 | itv_write(itv.value); |
71 | 92 | ||
72 | /* set Interval Timer Counter to zero */ |
93 | /* set Interval Timer Counter to zero */ |
73 | itc_write(0); |
94 | itc_write(0); |
74 | 95 | ||
75 | /* generate first Interval Timer interrupt in IT_DELTA ticks */ |
96 | /* generate first Interval Timer interrupt in IT_DELTA ticks */ |
76 | itm_write(IT_DELTA); |
97 | itm_write(IT_DELTA); |
77 | 98 | ||
78 | /* propagate changes */ |
99 | /* propagate changes */ |
79 | srlz_d(); |
100 | srlz_d(); |
80 | } |
101 | } |
81 | 102 | ||
82 | /** Always claim ownership for this IRQ. |
103 | /** Always claim ownership for this IRQ. |
83 | * |
104 | * |
84 | * Other devices are responsible to avoid using INR 0. |
105 | * Other devices are responsible to avoid using INR 0. |
85 | * |
106 | * |
86 | * @return Always IRQ_ACCEPT. |
107 | * @return Always IRQ_ACCEPT. |
87 | */ |
108 | */ |
88 | irq_ownership_t it_claim(void) |
109 | irq_ownership_t it_claim(void) |
89 | { |
110 | { |
90 | return IRQ_ACCEPT; |
111 | return IRQ_ACCEPT; |
91 | } |
112 | } |
92 | 113 | ||
93 | /** Process Interval Timer interrupt. */ |
114 | /** Process Interval Timer interrupt. */ |
94 | void it_interrupt(irq_t *irq, void *arg, ...) |
115 | void it_interrupt(irq_t *irq, void *arg, ...) |
95 | { |
116 | { |
96 | int64_t c; |
117 | int64_t c; |
97 | int64_t m; |
118 | int64_t m; |
98 | 119 | ||
99 | eoi_write(EOI); |
120 | eoi_write(EOI); |
100 | 121 | ||
101 | m = itm_read(); |
122 | m = itm_read(); |
102 | 123 | ||
103 | while (1) { |
124 | while (1) { |
104 | c = itc_read(); |
125 | c = itc_read(); |
105 | c += IT_SERVICE_CLOCKS; |
126 | c += IT_SERVICE_CLOCKS; |
106 | 127 | ||
107 | m += IT_DELTA; |
128 | m += IT_DELTA; |
108 | if (m - c < 0) |
129 | if (m - c < 0) |
109 | CPU->missed_clock_ticks++; |
130 | CPU->missed_clock_ticks++; |
110 | else |
131 | else |
111 | break; |
132 | break; |
112 | } |
133 | } |
113 | 134 | ||
114 | itm_write(m); |
135 | itm_write(m); |
115 | srlz_d(); /* propagate changes */ |
136 | srlz_d(); /* propagate changes */ |
116 | 137 | ||
117 | /* |
138 | /* |
118 | * We are holding a lock which prevents preemption. |
139 | * We are holding a lock which prevents preemption. |
119 | * Release the lock, call clock() and reacquire the lock again. |
140 | * Release the lock, call clock() and reacquire the lock again. |
120 | */ |
141 | */ |
121 | spinlock_unlock(&irq->lock); |
142 | spinlock_unlock(&irq->lock); |
122 | clock(); |
143 | clock(); |
123 | spinlock_lock(&irq->lock); |
144 | spinlock_lock(&irq->lock); |
124 | } |
145 | } |
125 | 146 | ||
126 | /** @} |
147 | /** @} |
127 | */ |
148 | */ |
128 | 149 |