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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 - 2006 Jakub Jermar |
2 | * Copyright (c) 2005 - 2006 Jakub Jermar |
3 | * Copyright (c) 2006 Jakub Vana |
3 | * Copyright (c) 2006 Jakub Vana |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | */ |
28 | */ |
29 | 29 | ||
30 | /** @addtogroup ia64mm |
30 | /** @addtogroup ia64mm |
31 | * @{ |
31 | * @{ |
32 | */ |
32 | */ |
33 | /** @file |
33 | /** @file |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #ifndef KERN_ia64_PAGE_H_ |
36 | #ifndef KERN_ia64_PAGE_H_ |
37 | #define KERN_ia64_PAGE_H_ |
37 | #define KERN_ia64_PAGE_H_ |
38 | 38 | ||
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | 40 | ||
41 | #define PAGE_SIZE FRAME_SIZE |
41 | #define PAGE_SIZE FRAME_SIZE |
42 | #define PAGE_WIDTH FRAME_WIDTH |
42 | #define PAGE_WIDTH FRAME_WIDTH |
43 | 43 | ||
44 | #ifdef KERNEL |
44 | #ifdef KERNEL |
45 | 45 | ||
46 | /** Bit width of the TLB-locked portion of kernel address space. */ |
46 | /** Bit width of the TLB-locked portion of kernel address space. */ |
47 | #define KERNEL_PAGE_WIDTH 28 /* 256M */ |
47 | #define KERNEL_PAGE_WIDTH 28 /* 256M */ |
48 | #define IO_PAGE_WIDTH 26 /* 64M */ |
48 | #define IO_PAGE_WIDTH 26 /* 64M */ |
49 | #define FW_PAGE_WIDTH 28 /* 256M */ |
49 | #define FW_PAGE_WIDTH 28 /* 256M */ |
50 | 50 | ||
- | 51 | #define USPACE_IO_PAGE_WIDTH 12 /* 4K */ |
|
- | 52 | ||
- | 53 | ||
- | 54 | ||
51 | /** Staticly mapped IO spaces */ |
55 | /** Staticly mapped IO spaces - offsets to 0xe...00 of virtual adresses |
- | 56 | becauce of "minimal virtual bits implemented is 51" |
|
- | 57 | it is possible to have here values up to 0x0007000000000000 |
|
- | 58 | */ |
|
52 | 59 | ||
53 | /* Firmware area (bellow 4GB in phys mem) */ |
60 | /* Firmware area (bellow 4GB in phys mem) */ |
54 | #define FW_OFFSET 0x00000000F0000000 |
61 | #define FW_OFFSET 0x00000000F0000000 |
55 | /* Legacy IO space */ |
62 | /* Legacy IO space */ |
56 | #define IO_OFFSET 0x0001000000000000 |
63 | #define IO_OFFSET 0x0001000000000000 |
57 | /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/ |
64 | /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/ |
58 | #define VIO_OFFSET 0x0002000000000000 |
65 | #define VIO_OFFSET 0x0002000000000000 |
59 | 66 | ||
60 | 67 | ||
61 | 68 | ||
62 | 69 | ||
63 | #define PPN_SHIFT 12 |
70 | #define PPN_SHIFT 12 |
64 | 71 | ||
65 | #define VRN_SHIFT 61 |
72 | #define VRN_SHIFT 61 |
66 | #define VRN_MASK (7LL << VRN_SHIFT) |
73 | #define VRN_MASK (7LL << VRN_SHIFT) |
67 | #define VA2VRN(va) ((va)>>VRN_SHIFT) |
74 | #define VA2VRN(va) ((va)>>VRN_SHIFT) |
68 | 75 | ||
69 | #ifdef __ASM__ |
76 | #ifdef __ASM__ |
70 | #define VRN_KERNEL 7 |
77 | #define VRN_KERNEL 7 |
71 | #else |
78 | #else |
72 | #define VRN_KERNEL 7LL |
79 | #define VRN_KERNEL 7LL |
73 | #endif |
80 | #endif |
74 | 81 | ||
75 | #define REGION_REGISTERS 8 |
82 | #define REGION_REGISTERS 8 |
76 | 83 | ||
77 | #define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT))) |
84 | #define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT))) |
78 | #define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT))) |
85 | #define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT))) |
79 | 86 | ||
80 | #define VHPT_WIDTH 20 /* 1M */ |
87 | #define VHPT_WIDTH 20 /* 1M */ |
81 | #define VHPT_SIZE (1 << VHPT_WIDTH) |
88 | #define VHPT_SIZE (1 << VHPT_WIDTH) |
82 | 89 | ||
83 | #define PTA_BASE_SHIFT 15 |
90 | #define PTA_BASE_SHIFT 15 |
84 | 91 | ||
85 | /** Memory Attributes. */ |
92 | /** Memory Attributes. */ |
86 | #define MA_WRITEBACK 0x0 |
93 | #define MA_WRITEBACK 0x0 |
87 | #define MA_UNCACHEABLE 0x4 |
94 | #define MA_UNCACHEABLE 0x4 |
88 | 95 | ||
89 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
96 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
90 | #define PL_KERNEL 0x0 |
97 | #define PL_KERNEL 0x0 |
91 | #define PL_USER 0x3 |
98 | #define PL_USER 0x3 |
92 | 99 | ||
93 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
100 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
94 | #define AR_READ 0x0 |
101 | #define AR_READ 0x0 |
95 | #define AR_EXECUTE 0x1 |
102 | #define AR_EXECUTE 0x1 |
96 | #define AR_WRITE 0x2 |
103 | #define AR_WRITE 0x2 |
97 | 104 | ||
98 | #ifndef __ASM__ |
105 | #ifndef __ASM__ |
99 | 106 | ||
100 | #include <arch/mm/as.h> |
107 | #include <arch/mm/as.h> |
101 | #include <arch/mm/frame.h> |
108 | #include <arch/mm/frame.h> |
102 | #include <arch/interrupt.h> |
109 | #include <arch/interrupt.h> |
103 | #include <arch/barrier.h> |
110 | #include <arch/barrier.h> |
104 | #include <arch/mm/asid.h> |
111 | #include <arch/mm/asid.h> |
105 | #include <arch/types.h> |
112 | #include <arch/types.h> |
106 | #include <debug.h> |
113 | #include <debug.h> |
107 | 114 | ||
108 | struct vhpt_tag_info { |
115 | struct vhpt_tag_info { |
109 | unsigned long long tag : 63; |
116 | unsigned long long tag : 63; |
110 | unsigned ti : 1; |
117 | unsigned ti : 1; |
111 | } __attribute__ ((packed)); |
118 | } __attribute__ ((packed)); |
112 | 119 | ||
113 | union vhpt_tag { |
120 | union vhpt_tag { |
114 | struct vhpt_tag_info tag_info; |
121 | struct vhpt_tag_info tag_info; |
115 | unsigned tag_word; |
122 | unsigned tag_word; |
116 | }; |
123 | }; |
117 | 124 | ||
118 | struct vhpt_entry_present { |
125 | struct vhpt_entry_present { |
119 | /* Word 0 */ |
126 | /* Word 0 */ |
120 | unsigned p : 1; |
127 | unsigned p : 1; |
121 | unsigned : 1; |
128 | unsigned : 1; |
122 | unsigned ma : 3; |
129 | unsigned ma : 3; |
123 | unsigned a : 1; |
130 | unsigned a : 1; |
124 | unsigned d : 1; |
131 | unsigned d : 1; |
125 | unsigned pl : 2; |
132 | unsigned pl : 2; |
126 | unsigned ar : 3; |
133 | unsigned ar : 3; |
127 | unsigned long long ppn : 38; |
134 | unsigned long long ppn : 38; |
128 | unsigned : 2; |
135 | unsigned : 2; |
129 | unsigned ed : 1; |
136 | unsigned ed : 1; |
130 | unsigned ig1 : 11; |
137 | unsigned ig1 : 11; |
131 | 138 | ||
132 | /* Word 1 */ |
139 | /* Word 1 */ |
133 | unsigned : 2; |
140 | unsigned : 2; |
134 | unsigned ps : 6; |
141 | unsigned ps : 6; |
135 | unsigned key : 24; |
142 | unsigned key : 24; |
136 | unsigned : 32; |
143 | unsigned : 32; |
137 | 144 | ||
138 | /* Word 2 */ |
145 | /* Word 2 */ |
139 | union vhpt_tag tag; |
146 | union vhpt_tag tag; |
140 | 147 | ||
141 | /* Word 3 */ |
148 | /* Word 3 */ |
142 | uint64_t ig3 : 64; |
149 | uint64_t ig3 : 64; |
143 | } __attribute__ ((packed)); |
150 | } __attribute__ ((packed)); |
144 | 151 | ||
145 | struct vhpt_entry_not_present { |
152 | struct vhpt_entry_not_present { |
146 | /* Word 0 */ |
153 | /* Word 0 */ |
147 | unsigned p : 1; |
154 | unsigned p : 1; |
148 | unsigned long long ig0 : 52; |
155 | unsigned long long ig0 : 52; |
149 | unsigned ig1 : 11; |
156 | unsigned ig1 : 11; |
150 | 157 | ||
151 | /* Word 1 */ |
158 | /* Word 1 */ |
152 | unsigned : 2; |
159 | unsigned : 2; |
153 | unsigned ps : 6; |
160 | unsigned ps : 6; |
154 | unsigned long long ig2 : 56; |
161 | unsigned long long ig2 : 56; |
155 | 162 | ||
156 | /* Word 2 */ |
163 | /* Word 2 */ |
157 | union vhpt_tag tag; |
164 | union vhpt_tag tag; |
158 | 165 | ||
159 | /* Word 3 */ |
166 | /* Word 3 */ |
160 | uint64_t ig3 : 64; |
167 | uint64_t ig3 : 64; |
161 | } __attribute__ ((packed)); |
168 | } __attribute__ ((packed)); |
162 | 169 | ||
163 | typedef union vhpt_entry { |
170 | typedef union vhpt_entry { |
164 | struct vhpt_entry_present present; |
171 | struct vhpt_entry_present present; |
165 | struct vhpt_entry_not_present not_present; |
172 | struct vhpt_entry_not_present not_present; |
166 | uint64_t word[4]; |
173 | uint64_t word[4]; |
167 | } vhpt_entry_t; |
174 | } vhpt_entry_t; |
168 | 175 | ||
169 | struct region_register_map { |
176 | struct region_register_map { |
170 | unsigned ve : 1; |
177 | unsigned ve : 1; |
171 | unsigned : 1; |
178 | unsigned : 1; |
172 | unsigned ps : 6; |
179 | unsigned ps : 6; |
173 | unsigned rid : 24; |
180 | unsigned rid : 24; |
174 | unsigned : 32; |
181 | unsigned : 32; |
175 | } __attribute__ ((packed)); |
182 | } __attribute__ ((packed)); |
176 | 183 | ||
177 | typedef union region_register { |
184 | typedef union region_register { |
178 | struct region_register_map map; |
185 | struct region_register_map map; |
179 | unsigned long long word; |
186 | unsigned long long word; |
180 | } region_register; |
187 | } region_register; |
181 | 188 | ||
182 | struct pta_register_map { |
189 | struct pta_register_map { |
183 | unsigned ve : 1; |
190 | unsigned ve : 1; |
184 | unsigned : 1; |
191 | unsigned : 1; |
185 | unsigned size : 6; |
192 | unsigned size : 6; |
186 | unsigned vf : 1; |
193 | unsigned vf : 1; |
187 | unsigned : 6; |
194 | unsigned : 6; |
188 | unsigned long long base : 49; |
195 | unsigned long long base : 49; |
189 | } __attribute__ ((packed)); |
196 | } __attribute__ ((packed)); |
190 | 197 | ||
191 | typedef union pta_register { |
198 | typedef union pta_register { |
192 | struct pta_register_map map; |
199 | struct pta_register_map map; |
193 | uint64_t word; |
200 | uint64_t word; |
194 | } pta_register; |
201 | } pta_register; |
195 | 202 | ||
196 | /** Return Translation Hashed Entry Address. |
203 | /** Return Translation Hashed Entry Address. |
197 | * |
204 | * |
198 | * VRN bits are used to read RID (ASID) from one |
205 | * VRN bits are used to read RID (ASID) from one |
199 | * of the eight region registers registers. |
206 | * of the eight region registers registers. |
200 | * |
207 | * |
201 | * @param va Virtual address including VRN bits. |
208 | * @param va Virtual address including VRN bits. |
202 | * |
209 | * |
203 | * @return Address of the head of VHPT collision chain. |
210 | * @return Address of the head of VHPT collision chain. |
204 | */ |
211 | */ |
205 | static inline uint64_t thash(uint64_t va) |
212 | static inline uint64_t thash(uint64_t va) |
206 | { |
213 | { |
207 | uint64_t ret; |
214 | uint64_t ret; |
208 | 215 | ||
209 | asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
216 | asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
210 | 217 | ||
211 | return ret; |
218 | return ret; |
212 | } |
219 | } |
213 | 220 | ||
214 | /** Return Translation Hashed Entry Tag. |
221 | /** Return Translation Hashed Entry Tag. |
215 | * |
222 | * |
216 | * VRN bits are used to read RID (ASID) from one |
223 | * VRN bits are used to read RID (ASID) from one |
217 | * of the eight region registers. |
224 | * of the eight region registers. |
218 | * |
225 | * |
219 | * @param va Virtual address including VRN bits. |
226 | * @param va Virtual address including VRN bits. |
220 | * |
227 | * |
221 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
228 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
222 | */ |
229 | */ |
223 | static inline uint64_t ttag(uint64_t va) |
230 | static inline uint64_t ttag(uint64_t va) |
224 | { |
231 | { |
225 | uint64_t ret; |
232 | uint64_t ret; |
226 | 233 | ||
227 | asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
234 | asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
228 | 235 | ||
229 | return ret; |
236 | return ret; |
230 | } |
237 | } |
231 | 238 | ||
232 | /** Read Region Register. |
239 | /** Read Region Register. |
233 | * |
240 | * |
234 | * @param i Region register index. |
241 | * @param i Region register index. |
235 | * |
242 | * |
236 | * @return Current contents of rr[i]. |
243 | * @return Current contents of rr[i]. |
237 | */ |
244 | */ |
238 | static inline uint64_t rr_read(index_t i) |
245 | static inline uint64_t rr_read(index_t i) |
239 | { |
246 | { |
240 | uint64_t ret; |
247 | uint64_t ret; |
241 | ASSERT(i < REGION_REGISTERS); |
248 | ASSERT(i < REGION_REGISTERS); |
242 | asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
249 | asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
243 | return ret; |
250 | return ret; |
244 | } |
251 | } |
245 | 252 | ||
246 | /** Write Region Register. |
253 | /** Write Region Register. |
247 | * |
254 | * |
248 | * @param i Region register index. |
255 | * @param i Region register index. |
249 | * @param v Value to be written to rr[i]. |
256 | * @param v Value to be written to rr[i]. |
250 | */ |
257 | */ |
251 | static inline void rr_write(index_t i, uint64_t v) |
258 | static inline void rr_write(index_t i, uint64_t v) |
252 | { |
259 | { |
253 | ASSERT(i < REGION_REGISTERS); |
260 | ASSERT(i < REGION_REGISTERS); |
254 | asm volatile ( |
261 | asm volatile ( |
255 | "mov rr[%0] = %1\n" |
262 | "mov rr[%0] = %1\n" |
256 | : |
263 | : |
257 | : "r" (i << VRN_SHIFT), "r" (v) |
264 | : "r" (i << VRN_SHIFT), "r" (v) |
258 | ); |
265 | ); |
259 | } |
266 | } |
260 | 267 | ||
261 | /** Read Page Table Register. |
268 | /** Read Page Table Register. |
262 | * |
269 | * |
263 | * @return Current value stored in PTA. |
270 | * @return Current value stored in PTA. |
264 | */ |
271 | */ |
265 | static inline uint64_t pta_read(void) |
272 | static inline uint64_t pta_read(void) |
266 | { |
273 | { |
267 | uint64_t ret; |
274 | uint64_t ret; |
268 | 275 | ||
269 | asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
276 | asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
270 | 277 | ||
271 | return ret; |
278 | return ret; |
272 | } |
279 | } |
273 | 280 | ||
274 | /** Write Page Table Register. |
281 | /** Write Page Table Register. |
275 | * |
282 | * |
276 | * @param v New value to be stored in PTA. |
283 | * @param v New value to be stored in PTA. |
277 | */ |
284 | */ |
278 | static inline void pta_write(uint64_t v) |
285 | static inline void pta_write(uint64_t v) |
279 | { |
286 | { |
280 | asm volatile ("mov cr.pta = %0\n" : : "r" (v)); |
287 | asm volatile ("mov cr.pta = %0\n" : : "r" (v)); |
281 | } |
288 | } |
282 | 289 | ||
283 | extern void page_arch_init(void); |
290 | extern void page_arch_init(void); |
284 | 291 | ||
285 | extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); |
292 | extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); |
286 | extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v); |
293 | extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v); |
287 | extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags); |
294 | extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags); |
288 | 295 | ||
289 | #endif /* __ASM__ */ |
296 | #endif /* __ASM__ */ |
290 | 297 | ||
291 | #endif /* KERNEL */ |
298 | #endif /* KERNEL */ |
292 | 299 | ||
293 | #endif |
300 | #endif |
294 | 301 | ||
295 | /** @} |
302 | /** @} |
296 | */ |
303 | */ |
297 | 304 |