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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ia64 |
29 | /** @addtogroup ia64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_ia64_ASM_H_ |
35 | #ifndef KERN_ia64_ASM_H_ |
36 | #define KERN_ia64_ASM_H_ |
36 | #define KERN_ia64_ASM_H_ |
37 | 37 | ||
38 | #include <config.h> |
38 | #include <config.h> |
39 | #include <arch/types.h> |
39 | #include <arch/types.h> |
40 | #include <arch/register.h> |
40 | #include <arch/register.h> |
41 | 41 | ||
- | 42 | typedef uint64_t ioport_t; |
|
42 | 43 | ||
43 | #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL |
44 | #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL |
44 | 45 | ||
45 | static inline void outb(uint64_t port,uint8_t v) |
46 | static inline void outb(ioport_t port,uint8_t v) |
46 | { |
47 | { |
47 | *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
48 | *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
48 | 49 | ||
49 | asm volatile ("mf\n" ::: "memory"); |
50 | asm volatile ("mf\n" ::: "memory"); |
50 | } |
51 | } |
51 | 52 | ||
52 | static inline void outw(uint64_t port,uint16_t v) |
53 | static inline void outw(ioport_t port,uint16_t v) |
53 | { |
54 | { |
54 | *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
55 | *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
55 | 56 | ||
56 | asm volatile ("mf\n" ::: "memory"); |
57 | asm volatile ("mf\n" ::: "memory"); |
57 | } |
58 | } |
58 | 59 | ||
59 | static inline void outl(uint64_t port,uint32_t v) |
60 | static inline void outl(ioport_t port,uint32_t v) |
60 | { |
61 | { |
61 | *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
62 | *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
62 | 63 | ||
63 | asm volatile ("mf\n" ::: "memory"); |
64 | asm volatile ("mf\n" ::: "memory"); |
64 | } |
65 | } |
65 | 66 | ||
66 | 67 | ||
67 | 68 | ||
68 | static inline uint8_t inb(uint64_t port) |
69 | static inline uint8_t inb(ioport_t port) |
69 | { |
70 | { |
70 | asm volatile ("mf\n" ::: "memory"); |
71 | asm volatile ("mf\n" ::: "memory"); |
71 | 72 | ||
72 | return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); |
73 | return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); |
73 | } |
74 | } |
74 | 75 | ||
75 | static inline uint16_t inw(uint64_t port) |
76 | static inline uint16_t inw(ioport_t port) |
76 | { |
77 | { |
77 | asm volatile ("mf\n" ::: "memory"); |
78 | asm volatile ("mf\n" ::: "memory"); |
78 | 79 | ||
79 | return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 )))); |
80 | return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 )))); |
80 | } |
81 | } |
81 | 82 | ||
82 | static inline uint32_t inl(uint64_t port) |
83 | static inline uint32_t inl(ioport_t port) |
83 | { |
84 | { |
84 | asm volatile ("mf\n" ::: "memory"); |
85 | asm volatile ("mf\n" ::: "memory"); |
85 | 86 | ||
86 | return *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); |
87 | return *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); |
87 | } |
88 | } |
88 | 89 | ||
89 | 90 | ||
90 | 91 | ||
91 | /** Return base address of current stack |
92 | /** Return base address of current stack |
92 | * |
93 | * |
93 | * Return the base address of the current stack. |
94 | * Return the base address of the current stack. |
94 | * The stack is assumed to be STACK_SIZE long. |
95 | * The stack is assumed to be STACK_SIZE long. |
95 | * The stack must start on page boundary. |
96 | * The stack must start on page boundary. |
96 | */ |
97 | */ |
97 | static inline uintptr_t get_stack_base(void) |
98 | static inline uintptr_t get_stack_base(void) |
98 | { |
99 | { |
99 | uint64_t v; |
100 | uint64_t v; |
100 | 101 | ||
- | 102 | //I'm not sure why but this code bad inlines in scheduler, |
|
- | 103 | //so THE shifts about 16B and causes kernel panic |
|
101 | asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
104 | //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
- | 105 | //return v; |
|
102 | 106 | ||
- | 107 | //this code have the same meaning but inlines well |
|
- | 108 | asm volatile ("mov %0 = r12" : "=r" (v) ); |
|
103 | return v; |
109 | return v & (~(STACK_SIZE-1)); |
104 | } |
110 | } |
105 | 111 | ||
106 | /** Return Processor State Register. |
112 | /** Return Processor State Register. |
107 | * |
113 | * |
108 | * @return PSR. |
114 | * @return PSR. |
109 | */ |
115 | */ |
110 | static inline uint64_t psr_read(void) |
116 | static inline uint64_t psr_read(void) |
111 | { |
117 | { |
112 | uint64_t v; |
118 | uint64_t v; |
113 | 119 | ||
114 | asm volatile ("mov %0 = psr\n" : "=r" (v)); |
120 | asm volatile ("mov %0 = psr\n" : "=r" (v)); |
115 | 121 | ||
116 | return v; |
122 | return v; |
117 | } |
123 | } |
118 | 124 | ||
119 | /** Read IVA (Interruption Vector Address). |
125 | /** Read IVA (Interruption Vector Address). |
120 | * |
126 | * |
121 | * @return Return location of interruption vector table. |
127 | * @return Return location of interruption vector table. |
122 | */ |
128 | */ |
123 | static inline uint64_t iva_read(void) |
129 | static inline uint64_t iva_read(void) |
124 | { |
130 | { |
125 | uint64_t v; |
131 | uint64_t v; |
126 | 132 | ||
127 | asm volatile ("mov %0 = cr.iva\n" : "=r" (v)); |
133 | asm volatile ("mov %0 = cr.iva\n" : "=r" (v)); |
128 | 134 | ||
129 | return v; |
135 | return v; |
130 | } |
136 | } |
131 | 137 | ||
132 | /** Write IVA (Interruption Vector Address) register. |
138 | /** Write IVA (Interruption Vector Address) register. |
133 | * |
139 | * |
134 | * @param v New location of interruption vector table. |
140 | * @param v New location of interruption vector table. |
135 | */ |
141 | */ |
136 | static inline void iva_write(uint64_t v) |
142 | static inline void iva_write(uint64_t v) |
137 | { |
143 | { |
138 | asm volatile ("mov cr.iva = %0\n" : : "r" (v)); |
144 | asm volatile ("mov cr.iva = %0\n" : : "r" (v)); |
139 | } |
145 | } |
140 | 146 | ||
141 | 147 | ||
142 | /** Read IVR (External Interrupt Vector Register). |
148 | /** Read IVR (External Interrupt Vector Register). |
143 | * |
149 | * |
144 | * @return Highest priority, pending, unmasked external interrupt vector. |
150 | * @return Highest priority, pending, unmasked external interrupt vector. |
145 | */ |
151 | */ |
146 | static inline uint64_t ivr_read(void) |
152 | static inline uint64_t ivr_read(void) |
147 | { |
153 | { |
148 | uint64_t v; |
154 | uint64_t v; |
149 | 155 | ||
150 | asm volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
156 | asm volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
151 | 157 | ||
152 | return v; |
158 | return v; |
153 | } |
159 | } |
154 | 160 | ||
- | 161 | static inline uint64_t cr64_read(void) |
|
- | 162 | { |
|
- | 163 | uint64_t v; |
|
- | 164 | ||
- | 165 | asm volatile ("mov %0 = cr64\n" : "=r" (v)); |
|
- | 166 | ||
- | 167 | return v; |
|
- | 168 | } |
|
- | 169 | ||
- | 170 | ||
155 | /** Write ITC (Interval Timer Counter) register. |
171 | /** Write ITC (Interval Timer Counter) register. |
156 | * |
172 | * |
157 | * @param v New counter value. |
173 | * @param v New counter value. |
158 | */ |
174 | */ |
159 | static inline void itc_write(uint64_t v) |
175 | static inline void itc_write(uint64_t v) |
160 | { |
176 | { |
161 | asm volatile ("mov ar.itc = %0\n" : : "r" (v)); |
177 | asm volatile ("mov ar.itc = %0\n" : : "r" (v)); |
162 | } |
178 | } |
163 | 179 | ||
164 | /** Read ITC (Interval Timer Counter) register. |
180 | /** Read ITC (Interval Timer Counter) register. |
165 | * |
181 | * |
166 | * @return Current counter value. |
182 | * @return Current counter value. |
167 | */ |
183 | */ |
168 | static inline uint64_t itc_read(void) |
184 | static inline uint64_t itc_read(void) |
169 | { |
185 | { |
170 | uint64_t v; |
186 | uint64_t v; |
171 | 187 | ||
172 | asm volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
188 | asm volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
173 | 189 | ||
174 | return v; |
190 | return v; |
175 | } |
191 | } |
176 | 192 | ||
177 | /** Write ITM (Interval Timer Match) register. |
193 | /** Write ITM (Interval Timer Match) register. |
178 | * |
194 | * |
179 | * @param v New match value. |
195 | * @param v New match value. |
180 | */ |
196 | */ |
181 | static inline void itm_write(uint64_t v) |
197 | static inline void itm_write(uint64_t v) |
182 | { |
198 | { |
183 | asm volatile ("mov cr.itm = %0\n" : : "r" (v)); |
199 | asm volatile ("mov cr.itm = %0\n" : : "r" (v)); |
184 | } |
200 | } |
185 | 201 | ||
186 | /** Read ITM (Interval Timer Match) register. |
202 | /** Read ITM (Interval Timer Match) register. |
187 | * |
203 | * |
188 | * @return Match value. |
204 | * @return Match value. |
189 | */ |
205 | */ |
190 | static inline uint64_t itm_read(void) |
206 | static inline uint64_t itm_read(void) |
191 | { |
207 | { |
192 | uint64_t v; |
208 | uint64_t v; |
193 | 209 | ||
194 | asm volatile ("mov %0 = cr.itm\n" : "=r" (v)); |
210 | asm volatile ("mov %0 = cr.itm\n" : "=r" (v)); |
195 | 211 | ||
196 | return v; |
212 | return v; |
197 | } |
213 | } |
198 | 214 | ||
199 | /** Read ITV (Interval Timer Vector) register. |
215 | /** Read ITV (Interval Timer Vector) register. |
200 | * |
216 | * |
201 | * @return Current vector and mask bit. |
217 | * @return Current vector and mask bit. |
202 | */ |
218 | */ |
203 | static inline uint64_t itv_read(void) |
219 | static inline uint64_t itv_read(void) |
204 | { |
220 | { |
205 | uint64_t v; |
221 | uint64_t v; |
206 | 222 | ||
207 | asm volatile ("mov %0 = cr.itv\n" : "=r" (v)); |
223 | asm volatile ("mov %0 = cr.itv\n" : "=r" (v)); |
208 | 224 | ||
209 | return v; |
225 | return v; |
210 | } |
226 | } |
211 | 227 | ||
212 | /** Write ITV (Interval Timer Vector) register. |
228 | /** Write ITV (Interval Timer Vector) register. |
213 | * |
229 | * |
214 | * @param v New vector and mask bit. |
230 | * @param v New vector and mask bit. |
215 | */ |
231 | */ |
216 | static inline void itv_write(uint64_t v) |
232 | static inline void itv_write(uint64_t v) |
217 | { |
233 | { |
218 | asm volatile ("mov cr.itv = %0\n" : : "r" (v)); |
234 | asm volatile ("mov cr.itv = %0\n" : : "r" (v)); |
219 | } |
235 | } |
220 | 236 | ||
221 | /** Write EOI (End Of Interrupt) register. |
237 | /** Write EOI (End Of Interrupt) register. |
222 | * |
238 | * |
223 | * @param v This value is ignored. |
239 | * @param v This value is ignored. |
224 | */ |
240 | */ |
225 | static inline void eoi_write(uint64_t v) |
241 | static inline void eoi_write(uint64_t v) |
226 | { |
242 | { |
227 | asm volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
243 | asm volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
228 | } |
244 | } |
229 | 245 | ||
230 | /** Read TPR (Task Priority Register). |
246 | /** Read TPR (Task Priority Register). |
231 | * |
247 | * |
232 | * @return Current value of TPR. |
248 | * @return Current value of TPR. |
233 | */ |
249 | */ |
234 | static inline uint64_t tpr_read(void) |
250 | static inline uint64_t tpr_read(void) |
235 | { |
251 | { |
236 | uint64_t v; |
252 | uint64_t v; |
237 | 253 | ||
238 | asm volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
254 | asm volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
239 | 255 | ||
240 | return v; |
256 | return v; |
241 | } |
257 | } |
242 | 258 | ||
243 | /** Write TPR (Task Priority Register). |
259 | /** Write TPR (Task Priority Register). |
244 | * |
260 | * |
245 | * @param v New value of TPR. |
261 | * @param v New value of TPR. |
246 | */ |
262 | */ |
247 | static inline void tpr_write(uint64_t v) |
263 | static inline void tpr_write(uint64_t v) |
248 | { |
264 | { |
249 | asm volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
265 | asm volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
250 | } |
266 | } |
251 | 267 | ||
252 | /** Disable interrupts. |
268 | /** Disable interrupts. |
253 | * |
269 | * |
254 | * Disable interrupts and return previous |
270 | * Disable interrupts and return previous |
255 | * value of PSR. |
271 | * value of PSR. |
256 | * |
272 | * |
257 | * @return Old interrupt priority level. |
273 | * @return Old interrupt priority level. |
258 | */ |
274 | */ |
259 | static ipl_t interrupts_disable(void) |
275 | static ipl_t interrupts_disable(void) |
260 | { |
276 | { |
261 | uint64_t v; |
277 | uint64_t v; |
262 | 278 | ||
263 | asm volatile ( |
279 | asm volatile ( |
264 | "mov %0 = psr\n" |
280 | "mov %0 = psr\n" |
265 | "rsm %1\n" |
281 | "rsm %1\n" |
266 | : "=r" (v) |
282 | : "=r" (v) |
267 | : "i" (PSR_I_MASK) |
283 | : "i" (PSR_I_MASK) |
268 | ); |
284 | ); |
269 | 285 | ||
270 | return (ipl_t) v; |
286 | return (ipl_t) v; |
271 | } |
287 | } |
272 | 288 | ||
273 | /** Enable interrupts. |
289 | /** Enable interrupts. |
274 | * |
290 | * |
275 | * Enable interrupts and return previous |
291 | * Enable interrupts and return previous |
276 | * value of PSR. |
292 | * value of PSR. |
277 | * |
293 | * |
278 | * @return Old interrupt priority level. |
294 | * @return Old interrupt priority level. |
279 | */ |
295 | */ |
280 | static ipl_t interrupts_enable(void) |
296 | static ipl_t interrupts_enable(void) |
281 | { |
297 | { |
282 | uint64_t v; |
298 | uint64_t v; |
283 | 299 | ||
284 | asm volatile ( |
300 | asm volatile ( |
285 | "mov %0 = psr\n" |
301 | "mov %0 = psr\n" |
286 | "ssm %1\n" |
302 | "ssm %1\n" |
287 | ";;\n" |
303 | ";;\n" |
288 | "srlz.d\n" |
304 | "srlz.d\n" |
289 | : "=r" (v) |
305 | : "=r" (v) |
290 | : "i" (PSR_I_MASK) |
306 | : "i" (PSR_I_MASK) |
291 | ); |
307 | ); |
292 | 308 | ||
293 | return (ipl_t) v; |
309 | return (ipl_t) v; |
294 | } |
310 | } |
295 | 311 | ||
296 | /** Restore interrupt priority level. |
312 | /** Restore interrupt priority level. |
297 | * |
313 | * |
298 | * Restore PSR. |
314 | * Restore PSR. |
299 | * |
315 | * |
300 | * @param ipl Saved interrupt priority level. |
316 | * @param ipl Saved interrupt priority level. |
301 | */ |
317 | */ |
302 | static inline void interrupts_restore(ipl_t ipl) |
318 | static inline void interrupts_restore(ipl_t ipl) |
303 | { |
319 | { |
304 | if (ipl & PSR_I_MASK) |
320 | if (ipl & PSR_I_MASK) |
305 | (void) interrupts_enable(); |
321 | (void) interrupts_enable(); |
306 | else |
322 | else |
307 | (void) interrupts_disable(); |
323 | (void) interrupts_disable(); |
308 | } |
324 | } |
309 | 325 | ||
310 | /** Return interrupt priority level. |
326 | /** Return interrupt priority level. |
311 | * |
327 | * |
312 | * @return PSR. |
328 | * @return PSR. |
313 | */ |
329 | */ |
314 | static inline ipl_t interrupts_read(void) |
330 | static inline ipl_t interrupts_read(void) |
315 | { |
331 | { |
316 | return (ipl_t) psr_read(); |
332 | return (ipl_t) psr_read(); |
317 | } |
333 | } |
318 | 334 | ||
319 | /** Disable protection key checking. */ |
335 | /** Disable protection key checking. */ |
320 | static inline void pk_disable(void) |
336 | static inline void pk_disable(void) |
321 | { |
337 | { |
322 | asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK)); |
338 | asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK)); |
323 | } |
339 | } |
324 | 340 | ||
325 | extern void cpu_halt(void); |
341 | extern void cpu_halt(void); |
326 | extern void cpu_sleep(void); |
342 | extern void cpu_sleep(void); |
327 | extern void asm_delay_loop(uint32_t t); |
343 | extern void asm_delay_loop(uint32_t t); |
328 | 344 | ||
329 | extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc); |
345 | extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc); |
330 | 346 | ||
331 | #endif |
347 | #endif |
332 | 348 | ||
333 | /** @} |
349 | /** @} |
334 | */ |
350 | */ |
335 | 351 |