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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/types.h> |
29 | #include <arch/types.h> |
30 | #include <arch/smp/apic.h> |
30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
31 | #include <arch/smp/ap.h> |
32 | #include <arch/smp/mps.h> |
32 | #include <arch/smp/mps.h> |
33 | #include <arch/boot/boot.h> |
33 | #include <arch/boot/boot.h> |
34 | #include <mm/page.h> |
34 | #include <mm/page.h> |
35 | #include <time/delay.h> |
35 | #include <time/delay.h> |
36 | #include <interrupt.h> |
36 | #include <interrupt.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <print.h> |
38 | #include <print.h> |
39 | #include <arch/asm.h> |
39 | #include <arch/asm.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | 41 | ||
42 | #ifdef CONFIG_SMP |
42 | #ifdef CONFIG_SMP |
43 | 43 | ||
44 | /* |
44 | /* |
45 | * Advanced Programmable Interrupt Controller for SMP systems. |
45 | * Advanced Programmable Interrupt Controller for SMP systems. |
46 | * Tested on: |
46 | * Tested on: |
47 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
47 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
48 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
48 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
49 | * VMware Workstation 5.5 with 2 CPUs |
49 | * VMware Workstation 5.5 with 2 CPUs |
50 | * QEMU 0.8.0 with 2-15 CPUs |
50 | * QEMU 0.8.0 with 2-15 CPUs |
51 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
51 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
52 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
52 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
53 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
53 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
54 | */ |
54 | */ |
55 | 55 | ||
56 | /* |
56 | /* |
57 | * These variables either stay configured as initilalized, or are changed by |
57 | * These variables either stay configured as initilalized, or are changed by |
58 | * the MP configuration code. |
58 | * the MP configuration code. |
59 | * |
59 | * |
60 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
60 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
61 | * optimize the code too much and accesses to l_apic and io_apic, that must |
61 | * optimize the code too much and accesses to l_apic and io_apic, that must |
62 | * always be 32-bit, would use byte oriented instructions. |
62 | * always be 32-bit, would use byte oriented instructions. |
63 | */ |
63 | */ |
64 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
64 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
65 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
65 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
66 | 66 | ||
67 | __u32 apic_id_mask = 0; |
67 | __u32 apic_id_mask = 0; |
68 | 68 | ||
69 | static int apic_poll_errors(void); |
69 | static int apic_poll_errors(void); |
70 | 70 | ||
71 | #ifdef LAPIC_VERBOSE |
71 | #ifdef LAPIC_VERBOSE |
72 | static char *delmod_str[] = { |
72 | static char *delmod_str[] = { |
73 | "Fixed", |
73 | "Fixed", |
74 | "Lowest Priority", |
74 | "Lowest Priority", |
75 | "SMI", |
75 | "SMI", |
76 | "Reserved", |
76 | "Reserved", |
77 | "NMI", |
77 | "NMI", |
78 | "INIT", |
78 | "INIT", |
79 | "STARTUP", |
79 | "STARTUP", |
80 | "ExtInt" |
80 | "ExtInt" |
81 | }; |
81 | }; |
82 | 82 | ||
83 | static char *destmod_str[] = { |
83 | static char *destmod_str[] = { |
84 | "Physical", |
84 | "Physical", |
85 | "Logical" |
85 | "Logical" |
86 | }; |
86 | }; |
87 | 87 | ||
88 | static char *trigmod_str[] = { |
88 | static char *trigmod_str[] = { |
89 | "Edge", |
89 | "Edge", |
90 | "Level" |
90 | "Level" |
91 | }; |
91 | }; |
92 | 92 | ||
93 | static char *mask_str[] = { |
93 | static char *mask_str[] = { |
94 | "Unmasked", |
94 | "Unmasked", |
95 | "Masked" |
95 | "Masked" |
96 | }; |
96 | }; |
97 | 97 | ||
98 | static char *delivs_str[] = { |
98 | static char *delivs_str[] = { |
99 | "Idle", |
99 | "Idle", |
100 | "Send Pending" |
100 | "Send Pending" |
101 | }; |
101 | }; |
102 | 102 | ||
103 | static char *tm_mode_str[] = { |
103 | static char *tm_mode_str[] = { |
104 | "One-shot", |
104 | "One-shot", |
105 | "Periodic" |
105 | "Periodic" |
106 | }; |
106 | }; |
107 | 107 | ||
108 | static char *intpol_str[] = { |
108 | static char *intpol_str[] = { |
109 | "Polarity High", |
109 | "Polarity High", |
110 | "Polarity Low" |
110 | "Polarity Low" |
111 | }; |
111 | }; |
112 | #endif /* LAPIC_VERBOSE */ |
112 | #endif /* LAPIC_VERBOSE */ |
113 | 113 | ||
114 | 114 | ||
115 | static void apic_spurious(int n, istate_t *istate); |
115 | static void apic_spurious(int n, istate_t *istate); |
116 | static void l_apic_timer_interrupt(int n, istate_t *istate); |
116 | static void l_apic_timer_interrupt(int n, istate_t *istate); |
117 | 117 | ||
118 | /** Initialize APIC on BSP. */ |
118 | /** Initialize APIC on BSP. */ |
119 | void apic_init(void) |
119 | void apic_init(void) |
120 | { |
120 | { |
121 | io_apic_id_t idreg; |
121 | io_apic_id_t idreg; |
122 | int i; |
122 | int i; |
123 | 123 | ||
124 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
124 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
125 | 125 | ||
126 | enable_irqs_function = io_apic_enable_irqs; |
126 | enable_irqs_function = io_apic_enable_irqs; |
127 | disable_irqs_function = io_apic_disable_irqs; |
127 | disable_irqs_function = io_apic_disable_irqs; |
128 | eoi_function = l_apic_eoi; |
128 | eoi_function = l_apic_eoi; |
129 | 129 | ||
130 | /* |
130 | /* |
131 | * Configure interrupt routing. |
131 | * Configure interrupt routing. |
132 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
132 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
133 | * Other interrupts will be forwarded to the lowest priority CPU. |
133 | * Other interrupts will be forwarded to the lowest priority CPU. |
134 | */ |
134 | */ |
135 | io_apic_disable_irqs(0xffff); |
135 | io_apic_disable_irqs(0xffff); |
136 | exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt); |
136 | exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt); |
137 | for (i = 0; i < IRQ_COUNT; i++) { |
137 | for (i = 0; i < IRQ_COUNT; i++) { |
138 | int pin; |
138 | int pin; |
139 | 139 | ||
140 | if ((pin = smp_irq_to_pin(i)) != -1) { |
140 | if ((pin = smp_irq_to_pin(i)) != -1) { |
141 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
141 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
142 | } |
142 | } |
143 | } |
143 | } |
144 | 144 | ||
145 | /* |
145 | /* |
146 | * Ensure that io_apic has unique ID. |
146 | * Ensure that io_apic has unique ID. |
147 | */ |
147 | */ |
148 | idreg.value = io_apic_read(IOAPICID); |
148 | idreg.value = io_apic_read(IOAPICID); |
149 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
149 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
150 | for (i = 0; i < APIC_ID_COUNT; i++) { |
150 | for (i = 0; i < APIC_ID_COUNT; i++) { |
151 | if (!((1<<i) & apic_id_mask)) { |
151 | if (!((1<<i) & apic_id_mask)) { |
152 | idreg.apic_id = i; |
152 | idreg.apic_id = i; |
153 | io_apic_write(IOAPICID, idreg.value); |
153 | io_apic_write(IOAPICID, idreg.value); |
154 | break; |
154 | break; |
155 | } |
155 | } |
156 | } |
156 | } |
157 | } |
157 | } |
158 | 158 | ||
159 | /* |
159 | /* |
160 | * Configure the BSP's lapic. |
160 | * Configure the BSP's lapic. |
161 | */ |
161 | */ |
162 | l_apic_init(); |
162 | l_apic_init(); |
163 | 163 | ||
164 | l_apic_debug(); |
164 | l_apic_debug(); |
165 | } |
165 | } |
166 | 166 | ||
167 | /** APIC spurious interrupt handler. |
167 | /** APIC spurious interrupt handler. |
168 | * |
168 | * |
169 | * @param n Interrupt vector. |
169 | * @param n Interrupt vector. |
170 | * @param stack Interrupted stack. |
170 | * @param stack Interrupted stack. |
171 | */ |
171 | */ |
172 | void apic_spurious(int n, istate_t *istate) |
172 | void apic_spurious(int n, istate_t *istate) |
173 | { |
173 | { |
- | 174 | #ifdef CONFIG_DEBUG |
|
174 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
175 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
- | 176 | #endif |
|
175 | } |
177 | } |
176 | 178 | ||
177 | /** Poll for APIC errors. |
179 | /** Poll for APIC errors. |
178 | * |
180 | * |
179 | * Examine Error Status Register and report all errors found. |
181 | * Examine Error Status Register and report all errors found. |
180 | * |
182 | * |
181 | * @return 0 on error, 1 on success. |
183 | * @return 0 on error, 1 on success. |
182 | */ |
184 | */ |
183 | int apic_poll_errors(void) |
185 | int apic_poll_errors(void) |
184 | { |
186 | { |
185 | esr_t esr; |
187 | esr_t esr; |
186 | 188 | ||
187 | esr.value = l_apic[ESR]; |
189 | esr.value = l_apic[ESR]; |
188 | 190 | ||
189 | if (esr.send_checksum_error) |
191 | if (esr.send_checksum_error) |
190 | printf("Send Checksum Error\n"); |
192 | printf("Send Checksum Error\n"); |
191 | if (esr.receive_checksum_error) |
193 | if (esr.receive_checksum_error) |
192 | printf("Receive Checksum Error\n"); |
194 | printf("Receive Checksum Error\n"); |
193 | if (esr.send_accept_error) |
195 | if (esr.send_accept_error) |
194 | printf("Send Accept Error\n"); |
196 | printf("Send Accept Error\n"); |
195 | if (esr.receive_accept_error) |
197 | if (esr.receive_accept_error) |
196 | printf("Receive Accept Error\n"); |
198 | printf("Receive Accept Error\n"); |
197 | if (esr.send_illegal_vector) |
199 | if (esr.send_illegal_vector) |
198 | printf("Send Illegal Vector\n"); |
200 | printf("Send Illegal Vector\n"); |
199 | if (esr.received_illegal_vector) |
201 | if (esr.received_illegal_vector) |
200 | printf("Received Illegal Vector\n"); |
202 | printf("Received Illegal Vector\n"); |
201 | if (esr.illegal_register_address) |
203 | if (esr.illegal_register_address) |
202 | printf("Illegal Register Address\n"); |
204 | printf("Illegal Register Address\n"); |
203 | 205 | ||
204 | return !esr.err_bitmap; |
206 | return !esr.err_bitmap; |
205 | } |
207 | } |
206 | 208 | ||
207 | /** Send all CPUs excluding CPU IPI vector. |
209 | /** Send all CPUs excluding CPU IPI vector. |
208 | * |
210 | * |
209 | * @param vector Interrupt vector to be sent. |
211 | * @param vector Interrupt vector to be sent. |
210 | * |
212 | * |
211 | * @return 0 on failure, 1 on success. |
213 | * @return 0 on failure, 1 on success. |
212 | */ |
214 | */ |
213 | int l_apic_broadcast_custom_ipi(__u8 vector) |
215 | int l_apic_broadcast_custom_ipi(__u8 vector) |
214 | { |
216 | { |
215 | icr_t icr; |
217 | icr_t icr; |
216 | 218 | ||
217 | icr.lo = l_apic[ICRlo]; |
219 | icr.lo = l_apic[ICRlo]; |
218 | icr.delmod = DELMOD_FIXED; |
220 | icr.delmod = DELMOD_FIXED; |
219 | icr.destmod = DESTMOD_LOGIC; |
221 | icr.destmod = DESTMOD_LOGIC; |
220 | icr.level = LEVEL_ASSERT; |
222 | icr.level = LEVEL_ASSERT; |
221 | icr.shorthand = SHORTHAND_ALL_EXCL; |
223 | icr.shorthand = SHORTHAND_ALL_EXCL; |
222 | icr.trigger_mode = TRIGMOD_LEVEL; |
224 | icr.trigger_mode = TRIGMOD_LEVEL; |
223 | icr.vector = vector; |
225 | icr.vector = vector; |
224 | 226 | ||
225 | l_apic[ICRlo] = icr.lo; |
227 | l_apic[ICRlo] = icr.lo; |
226 | 228 | ||
227 | icr.lo = l_apic[ICRlo]; |
229 | icr.lo = l_apic[ICRlo]; |
228 | if (icr.delivs == DELIVS_PENDING) |
230 | if (icr.delivs == DELIVS_PENDING) |
229 | printf("IPI is pending.\n"); |
231 | printf("IPI is pending.\n"); |
230 | 232 | ||
231 | return apic_poll_errors(); |
233 | return apic_poll_errors(); |
232 | } |
234 | } |
233 | 235 | ||
234 | /** Universal Start-up Algorithm for bringing up the AP processors. |
236 | /** Universal Start-up Algorithm for bringing up the AP processors. |
235 | * |
237 | * |
236 | * @param apicid APIC ID of the processor to be brought up. |
238 | * @param apicid APIC ID of the processor to be brought up. |
237 | * |
239 | * |
238 | * @return 0 on failure, 1 on success. |
240 | * @return 0 on failure, 1 on success. |
239 | */ |
241 | */ |
240 | int l_apic_send_init_ipi(__u8 apicid) |
242 | int l_apic_send_init_ipi(__u8 apicid) |
241 | { |
243 | { |
242 | icr_t icr; |
244 | icr_t icr; |
243 | int i; |
245 | int i; |
244 | 246 | ||
245 | /* |
247 | /* |
246 | * Read the ICR register in and zero all non-reserved fields. |
248 | * Read the ICR register in and zero all non-reserved fields. |
247 | */ |
249 | */ |
248 | icr.lo = l_apic[ICRlo]; |
250 | icr.lo = l_apic[ICRlo]; |
249 | icr.hi = l_apic[ICRhi]; |
251 | icr.hi = l_apic[ICRhi]; |
250 | 252 | ||
251 | icr.delmod = DELMOD_INIT; |
253 | icr.delmod = DELMOD_INIT; |
252 | icr.destmod = DESTMOD_PHYS; |
254 | icr.destmod = DESTMOD_PHYS; |
253 | icr.level = LEVEL_ASSERT; |
255 | icr.level = LEVEL_ASSERT; |
254 | icr.trigger_mode = TRIGMOD_LEVEL; |
256 | icr.trigger_mode = TRIGMOD_LEVEL; |
255 | icr.shorthand = SHORTHAND_NONE; |
257 | icr.shorthand = SHORTHAND_NONE; |
256 | icr.vector = 0; |
258 | icr.vector = 0; |
257 | icr.dest = apicid; |
259 | icr.dest = apicid; |
258 | 260 | ||
259 | l_apic[ICRhi] = icr.hi; |
261 | l_apic[ICRhi] = icr.hi; |
260 | l_apic[ICRlo] = icr.lo; |
262 | l_apic[ICRlo] = icr.lo; |
261 | 263 | ||
262 | /* |
264 | /* |
263 | * According to MP Specification, 20us should be enough to |
265 | * According to MP Specification, 20us should be enough to |
264 | * deliver the IPI. |
266 | * deliver the IPI. |
265 | */ |
267 | */ |
266 | delay(20); |
268 | delay(20); |
267 | 269 | ||
268 | if (!apic_poll_errors()) return 0; |
270 | if (!apic_poll_errors()) return 0; |
269 | 271 | ||
270 | icr.lo = l_apic[ICRlo]; |
272 | icr.lo = l_apic[ICRlo]; |
271 | if (icr.delivs == DELIVS_PENDING) |
273 | if (icr.delivs == DELIVS_PENDING) |
272 | printf("IPI is pending.\n"); |
274 | printf("IPI is pending.\n"); |
273 | 275 | ||
274 | icr.delmod = DELMOD_INIT; |
276 | icr.delmod = DELMOD_INIT; |
275 | icr.destmod = DESTMOD_PHYS; |
277 | icr.destmod = DESTMOD_PHYS; |
276 | icr.level = LEVEL_DEASSERT; |
278 | icr.level = LEVEL_DEASSERT; |
277 | icr.shorthand = SHORTHAND_NONE; |
279 | icr.shorthand = SHORTHAND_NONE; |
278 | icr.trigger_mode = TRIGMOD_LEVEL; |
280 | icr.trigger_mode = TRIGMOD_LEVEL; |
279 | icr.vector = 0; |
281 | icr.vector = 0; |
280 | l_apic[ICRlo] = icr.lo; |
282 | l_apic[ICRlo] = icr.lo; |
281 | 283 | ||
282 | /* |
284 | /* |
283 | * Wait 10ms as MP Specification specifies. |
285 | * Wait 10ms as MP Specification specifies. |
284 | */ |
286 | */ |
285 | delay(10000); |
287 | delay(10000); |
286 | 288 | ||
287 | if (!is_82489DX_apic(l_apic[LAVR])) { |
289 | if (!is_82489DX_apic(l_apic[LAVR])) { |
288 | /* |
290 | /* |
289 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
291 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
290 | */ |
292 | */ |
291 | for (i = 0; i<2; i++) { |
293 | for (i = 0; i<2; i++) { |
292 | icr.lo = l_apic[ICRlo]; |
294 | icr.lo = l_apic[ICRlo]; |
293 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
295 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
294 | icr.delmod = DELMOD_STARTUP; |
296 | icr.delmod = DELMOD_STARTUP; |
295 | icr.destmod = DESTMOD_PHYS; |
297 | icr.destmod = DESTMOD_PHYS; |
296 | icr.level = LEVEL_ASSERT; |
298 | icr.level = LEVEL_ASSERT; |
297 | icr.shorthand = SHORTHAND_NONE; |
299 | icr.shorthand = SHORTHAND_NONE; |
298 | icr.trigger_mode = TRIGMOD_LEVEL; |
300 | icr.trigger_mode = TRIGMOD_LEVEL; |
299 | l_apic[ICRlo] = icr.lo; |
301 | l_apic[ICRlo] = icr.lo; |
300 | delay(200); |
302 | delay(200); |
301 | } |
303 | } |
302 | } |
304 | } |
303 | 305 | ||
304 | return apic_poll_errors(); |
306 | return apic_poll_errors(); |
305 | } |
307 | } |
306 | 308 | ||
307 | /** Initialize Local APIC. */ |
309 | /** Initialize Local APIC. */ |
308 | void l_apic_init(void) |
310 | void l_apic_init(void) |
309 | { |
311 | { |
310 | lvt_error_t error; |
312 | lvt_error_t error; |
311 | lvt_lint_t lint; |
313 | lvt_lint_t lint; |
312 | tpr_t tpr; |
314 | tpr_t tpr; |
313 | svr_t svr; |
315 | svr_t svr; |
314 | icr_t icr; |
316 | icr_t icr; |
315 | tdcr_t tdcr; |
317 | tdcr_t tdcr; |
316 | lvt_tm_t tm; |
318 | lvt_tm_t tm; |
317 | ldr_t ldr; |
319 | ldr_t ldr; |
318 | dfr_t dfr; |
320 | dfr_t dfr; |
319 | __u32 t1, t2; |
321 | __u32 t1, t2; |
320 | 322 | ||
321 | /* Initialize LVT Error register. */ |
323 | /* Initialize LVT Error register. */ |
322 | error.value = l_apic[LVT_Err]; |
324 | error.value = l_apic[LVT_Err]; |
323 | error.masked = true; |
325 | error.masked = true; |
324 | l_apic[LVT_Err] = error.value; |
326 | l_apic[LVT_Err] = error.value; |
325 | 327 | ||
326 | /* Initialize LVT LINT0 register. */ |
328 | /* Initialize LVT LINT0 register. */ |
327 | lint.value = l_apic[LVT_LINT0]; |
329 | lint.value = l_apic[LVT_LINT0]; |
328 | lint.masked = true; |
330 | lint.masked = true; |
329 | l_apic[LVT_LINT0] = lint.value; |
331 | l_apic[LVT_LINT0] = lint.value; |
330 | 332 | ||
331 | /* Initialize LVT LINT1 register. */ |
333 | /* Initialize LVT LINT1 register. */ |
332 | lint.value = l_apic[LVT_LINT1]; |
334 | lint.value = l_apic[LVT_LINT1]; |
333 | lint.masked = true; |
335 | lint.masked = true; |
334 | l_apic[LVT_LINT1] = lint.value; |
336 | l_apic[LVT_LINT1] = lint.value; |
335 | 337 | ||
336 | /* Task Priority Register initialization. */ |
338 | /* Task Priority Register initialization. */ |
337 | tpr.value = l_apic[TPR]; |
339 | tpr.value = l_apic[TPR]; |
338 | tpr.pri_sc = 0; |
340 | tpr.pri_sc = 0; |
339 | tpr.pri = 0; |
341 | tpr.pri = 0; |
340 | l_apic[TPR] = tpr.value; |
342 | l_apic[TPR] = tpr.value; |
341 | 343 | ||
342 | /* Spurious-Interrupt Vector Register initialization. */ |
344 | /* Spurious-Interrupt Vector Register initialization. */ |
343 | svr.value = l_apic[SVR]; |
345 | svr.value = l_apic[SVR]; |
344 | svr.vector = VECTOR_APIC_SPUR; |
346 | svr.vector = VECTOR_APIC_SPUR; |
345 | svr.lapic_enabled = true; |
347 | svr.lapic_enabled = true; |
346 | svr.focus_checking = true; |
348 | svr.focus_checking = true; |
347 | l_apic[SVR] = svr.value; |
349 | l_apic[SVR] = svr.value; |
348 | 350 | ||
349 | if (CPU->arch.family >= 6) |
351 | if (CPU->arch.family >= 6) |
350 | enable_l_apic_in_msr(); |
352 | enable_l_apic_in_msr(); |
351 | 353 | ||
352 | /* Interrupt Command Register initialization. */ |
354 | /* Interrupt Command Register initialization. */ |
353 | icr.lo = l_apic[ICRlo]; |
355 | icr.lo = l_apic[ICRlo]; |
354 | icr.delmod = DELMOD_INIT; |
356 | icr.delmod = DELMOD_INIT; |
355 | icr.destmod = DESTMOD_PHYS; |
357 | icr.destmod = DESTMOD_PHYS; |
356 | icr.level = LEVEL_DEASSERT; |
358 | icr.level = LEVEL_DEASSERT; |
357 | icr.shorthand = SHORTHAND_ALL_INCL; |
359 | icr.shorthand = SHORTHAND_ALL_INCL; |
358 | icr.trigger_mode = TRIGMOD_LEVEL; |
360 | icr.trigger_mode = TRIGMOD_LEVEL; |
359 | l_apic[ICRlo] = icr.lo; |
361 | l_apic[ICRlo] = icr.lo; |
360 | 362 | ||
361 | /* Timer Divide Configuration Register initialization. */ |
363 | /* Timer Divide Configuration Register initialization. */ |
362 | tdcr.value = l_apic[TDCR]; |
364 | tdcr.value = l_apic[TDCR]; |
363 | tdcr.div_value = DIVIDE_1; |
365 | tdcr.div_value = DIVIDE_1; |
364 | l_apic[TDCR] = tdcr.value; |
366 | l_apic[TDCR] = tdcr.value; |
365 | 367 | ||
366 | /* Program local timer. */ |
368 | /* Program local timer. */ |
367 | tm.value = l_apic[LVT_Tm]; |
369 | tm.value = l_apic[LVT_Tm]; |
368 | tm.vector = VECTOR_CLK; |
370 | tm.vector = VECTOR_CLK; |
369 | tm.mode = TIMER_PERIODIC; |
371 | tm.mode = TIMER_PERIODIC; |
370 | tm.masked = false; |
372 | tm.masked = false; |
371 | l_apic[LVT_Tm] = tm.value; |
373 | l_apic[LVT_Tm] = tm.value; |
372 | 374 | ||
373 | /* |
375 | /* |
374 | * Measure and configure the timer to generate timer |
376 | * Measure and configure the timer to generate timer |
375 | * interrupt with period 1s/HZ seconds. |
377 | * interrupt with period 1s/HZ seconds. |
376 | */ |
378 | */ |
377 | t1 = l_apic[CCRT]; |
379 | t1 = l_apic[CCRT]; |
378 | l_apic[ICRT] = 0xffffffff; |
380 | l_apic[ICRT] = 0xffffffff; |
379 | 381 | ||
380 | while (l_apic[CCRT] == t1) |
382 | while (l_apic[CCRT] == t1) |
381 | ; |
383 | ; |
382 | 384 | ||
383 | t1 = l_apic[CCRT]; |
385 | t1 = l_apic[CCRT]; |
384 | delay(1000000/HZ); |
386 | delay(1000000/HZ); |
385 | t2 = l_apic[CCRT]; |
387 | t2 = l_apic[CCRT]; |
386 | 388 | ||
387 | l_apic[ICRT] = t1-t2; |
389 | l_apic[ICRT] = t1-t2; |
388 | 390 | ||
389 | /* Program Logical Destination Register. */ |
391 | /* Program Logical Destination Register. */ |
390 | ldr.value = l_apic[LDR]; |
392 | ldr.value = l_apic[LDR]; |
391 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
393 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
392 | ldr.id = (1<<CPU->id); |
394 | ldr.id = (1<<CPU->id); |
393 | l_apic[LDR] = ldr.value; |
395 | l_apic[LDR] = ldr.value; |
394 | 396 | ||
395 | /* Program Destination Format Register for Flat mode. */ |
397 | /* Program Destination Format Register for Flat mode. */ |
396 | dfr.value = l_apic[DFR]; |
398 | dfr.value = l_apic[DFR]; |
397 | dfr.model = MODEL_FLAT; |
399 | dfr.model = MODEL_FLAT; |
398 | l_apic[DFR] = dfr.value; |
400 | l_apic[DFR] = dfr.value; |
399 | } |
401 | } |
400 | 402 | ||
401 | /** Local APIC End of Interrupt. */ |
403 | /** Local APIC End of Interrupt. */ |
402 | void l_apic_eoi(void) |
404 | void l_apic_eoi(void) |
403 | { |
405 | { |
404 | l_apic[EOI] = 0; |
406 | l_apic[EOI] = 0; |
405 | } |
407 | } |
406 | 408 | ||
407 | /** Dump content of Local APIC registers. */ |
409 | /** Dump content of Local APIC registers. */ |
408 | void l_apic_debug(void) |
410 | void l_apic_debug(void) |
409 | { |
411 | { |
410 | #ifdef LAPIC_VERBOSE |
412 | #ifdef LAPIC_VERBOSE |
411 | lvt_tm_t tm; |
413 | lvt_tm_t tm; |
412 | lvt_lint_t lint; |
414 | lvt_lint_t lint; |
413 | lvt_error_t error; |
415 | lvt_error_t error; |
414 | 416 | ||
415 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
417 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
416 | 418 | ||
417 | tm.value = l_apic[LVT_Tm]; |
419 | tm.value = l_apic[LVT_Tm]; |
418 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
420 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
419 | lint.value = l_apic[LVT_LINT0]; |
421 | lint.value = l_apic[LVT_LINT0]; |
420 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
422 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
421 | lint.value = l_apic[LVT_LINT1]; |
423 | lint.value = l_apic[LVT_LINT1]; |
422 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
424 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
423 | error.value = l_apic[LVT_Err]; |
425 | error.value = l_apic[LVT_Err]; |
424 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
426 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
425 | #endif |
427 | #endif |
426 | } |
428 | } |
427 | 429 | ||
428 | /** Local APIC Timer Interrupt. |
430 | /** Local APIC Timer Interrupt. |
429 | * |
431 | * |
430 | * @param n Interrupt vector number. |
432 | * @param n Interrupt vector number. |
431 | * @param stack Interrupted stack. |
433 | * @param stack Interrupted stack. |
432 | */ |
434 | */ |
433 | void l_apic_timer_interrupt(int n, istate_t *istate) |
435 | void l_apic_timer_interrupt(int n, istate_t *istate) |
434 | { |
436 | { |
435 | l_apic_eoi(); |
437 | l_apic_eoi(); |
436 | clock(); |
438 | clock(); |
437 | } |
439 | } |
438 | 440 | ||
439 | /** Get Local APIC ID. |
441 | /** Get Local APIC ID. |
440 | * |
442 | * |
441 | * @return Local APIC ID. |
443 | * @return Local APIC ID. |
442 | */ |
444 | */ |
443 | __u8 l_apic_id(void) |
445 | __u8 l_apic_id(void) |
444 | { |
446 | { |
445 | l_apic_id_t idreg; |
447 | l_apic_id_t idreg; |
446 | 448 | ||
447 | idreg.value = l_apic[L_APIC_ID]; |
449 | idreg.value = l_apic[L_APIC_ID]; |
448 | return idreg.apic_id; |
450 | return idreg.apic_id; |
449 | } |
451 | } |
450 | 452 | ||
451 | /** Read from IO APIC register. |
453 | /** Read from IO APIC register. |
452 | * |
454 | * |
453 | * @param address IO APIC register address. |
455 | * @param address IO APIC register address. |
454 | * |
456 | * |
455 | * @return Content of the addressed IO APIC register. |
457 | * @return Content of the addressed IO APIC register. |
456 | */ |
458 | */ |
457 | __u32 io_apic_read(__u8 address) |
459 | __u32 io_apic_read(__u8 address) |
458 | { |
460 | { |
459 | io_regsel_t regsel; |
461 | io_regsel_t regsel; |
460 | 462 | ||
461 | regsel.value = io_apic[IOREGSEL]; |
463 | regsel.value = io_apic[IOREGSEL]; |
462 | regsel.reg_addr = address; |
464 | regsel.reg_addr = address; |
463 | io_apic[IOREGSEL] = regsel.value; |
465 | io_apic[IOREGSEL] = regsel.value; |
464 | return io_apic[IOWIN]; |
466 | return io_apic[IOWIN]; |
465 | } |
467 | } |
466 | 468 | ||
467 | /** Write to IO APIC register. |
469 | /** Write to IO APIC register. |
468 | * |
470 | * |
469 | * @param address IO APIC register address. |
471 | * @param address IO APIC register address. |
470 | * @param Content to be written to the addressed IO APIC register. |
472 | * @param Content to be written to the addressed IO APIC register. |
471 | */ |
473 | */ |
472 | void io_apic_write(__u8 address, __u32 x) |
474 | void io_apic_write(__u8 address, __u32 x) |
473 | { |
475 | { |
474 | io_regsel_t regsel; |
476 | io_regsel_t regsel; |
475 | 477 | ||
476 | regsel.value = io_apic[IOREGSEL]; |
478 | regsel.value = io_apic[IOREGSEL]; |
477 | regsel.reg_addr = address; |
479 | regsel.reg_addr = address; |
478 | io_apic[IOREGSEL] = regsel.value; |
480 | io_apic[IOREGSEL] = regsel.value; |
479 | io_apic[IOWIN] = x; |
481 | io_apic[IOWIN] = x; |
480 | } |
482 | } |
481 | 483 | ||
482 | /** Change some attributes of one item in I/O Redirection Table. |
484 | /** Change some attributes of one item in I/O Redirection Table. |
483 | * |
485 | * |
484 | * @param pin IO APIC pin number. |
486 | * @param pin IO APIC pin number. |
485 | * @param dest Interrupt destination address. |
487 | * @param dest Interrupt destination address. |
486 | * @param v Interrupt vector to trigger. |
488 | * @param v Interrupt vector to trigger. |
487 | * @param flags Flags. |
489 | * @param flags Flags. |
488 | */ |
490 | */ |
489 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
491 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
490 | { |
492 | { |
491 | io_redirection_reg_t reg; |
493 | io_redirection_reg_t reg; |
492 | int dlvr = DELMOD_FIXED; |
494 | int dlvr = DELMOD_FIXED; |
493 | 495 | ||
494 | if (flags & LOPRI) |
496 | if (flags & LOPRI) |
495 | dlvr = DELMOD_LOWPRI; |
497 | dlvr = DELMOD_LOWPRI; |
496 | 498 | ||
497 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
499 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
498 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
500 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
499 | 501 | ||
500 | reg.dest = dest; |
502 | reg.dest = dest; |
501 | reg.destmod = DESTMOD_LOGIC; |
503 | reg.destmod = DESTMOD_LOGIC; |
502 | reg.trigger_mode = TRIGMOD_EDGE; |
504 | reg.trigger_mode = TRIGMOD_EDGE; |
503 | reg.intpol = POLARITY_HIGH; |
505 | reg.intpol = POLARITY_HIGH; |
504 | reg.delmod = dlvr; |
506 | reg.delmod = dlvr; |
505 | reg.intvec = v; |
507 | reg.intvec = v; |
506 | 508 | ||
507 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
509 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
508 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
510 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
509 | } |
511 | } |
510 | 512 | ||
511 | /** Mask IRQs in IO APIC. |
513 | /** Mask IRQs in IO APIC. |
512 | * |
514 | * |
513 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
515 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
514 | */ |
516 | */ |
515 | void io_apic_disable_irqs(__u16 irqmask) |
517 | void io_apic_disable_irqs(__u16 irqmask) |
516 | { |
518 | { |
517 | io_redirection_reg_t reg; |
519 | io_redirection_reg_t reg; |
518 | int i, pin; |
520 | int i, pin; |
519 | 521 | ||
520 | for (i=0;i<16;i++) { |
522 | for (i=0;i<16;i++) { |
521 | if (irqmask & (1<<i)) { |
523 | if (irqmask & (1<<i)) { |
522 | /* |
524 | /* |
523 | * Mask the signal input in IO APIC if there is a |
525 | * Mask the signal input in IO APIC if there is a |
524 | * mapping for the respective IRQ number. |
526 | * mapping for the respective IRQ number. |
525 | */ |
527 | */ |
526 | pin = smp_irq_to_pin(i); |
528 | pin = smp_irq_to_pin(i); |
527 | if (pin != -1) { |
529 | if (pin != -1) { |
528 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
530 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
529 | reg.masked = true; |
531 | reg.masked = true; |
530 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
532 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
531 | } |
533 | } |
532 | 534 | ||
533 | } |
535 | } |
534 | } |
536 | } |
535 | } |
537 | } |
536 | 538 | ||
537 | /** Unmask IRQs in IO APIC. |
539 | /** Unmask IRQs in IO APIC. |
538 | * |
540 | * |
539 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
541 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
540 | */ |
542 | */ |
541 | void io_apic_enable_irqs(__u16 irqmask) |
543 | void io_apic_enable_irqs(__u16 irqmask) |
542 | { |
544 | { |
543 | int i, pin; |
545 | int i, pin; |
544 | io_redirection_reg_t reg; |
546 | io_redirection_reg_t reg; |
545 | 547 | ||
546 | for (i=0;i<16;i++) { |
548 | for (i=0;i<16;i++) { |
547 | if (irqmask & (1<<i)) { |
549 | if (irqmask & (1<<i)) { |
548 | /* |
550 | /* |
549 | * Unmask the signal input in IO APIC if there is a |
551 | * Unmask the signal input in IO APIC if there is a |
550 | * mapping for the respective IRQ number. |
552 | * mapping for the respective IRQ number. |
551 | */ |
553 | */ |
552 | pin = smp_irq_to_pin(i); |
554 | pin = smp_irq_to_pin(i); |
553 | if (pin != -1) { |
555 | if (pin != -1) { |
554 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
556 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
555 | reg.masked = false; |
557 | reg.masked = false; |
556 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
558 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
557 | } |
559 | } |
558 | 560 | ||
559 | } |
561 | } |
560 | } |
562 | } |
561 | } |
563 | } |
562 | 564 | ||
563 | #endif /* CONFIG_SMP */ |
565 | #endif /* CONFIG_SMP */ |
564 | 566 |