WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ia32/src/asm.S


#
# Copyright (c) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
## very low and hardware-level functions
 
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error
# word and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027d00
 
.text
 
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
.global memsetb
.global memsetw
.global memcpy
.global memcpy_from_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace
.global memcpy_to_uspace_failover_address
 
 
# Wrapper for generic memsetb
memsetb:
	jmp _memsetb
 
# Wrapper for generic memsetw
memsetw:
	jmp _memsetw
 
 
#define MEMCPY_DST	4
#define MEMCPY_SRC	8
#define MEMCPY_SIZE	12
 
/** Copy memory to/from userspace.
 *
 * This is almost conventional memcpy().
 * The difference is that there is a failover part
 * to where control is returned from a page fault
 * if the page fault occurs during copy_from_uspace()
 * or copy_to_uspace().
 *
 * @param MEMCPY_DST(%esp)	Destination address.
 * @param MEMCPY_SRC(%esp)	Source address.
 * @param MEMCPY_SIZE(%esp)	Size.
 *
 * @return MEMCPY_SRC(%esp) on success and 0 on failure.
 */
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
	movl %edi, %edx			/* save %edi */
	movl %esi, %eax			/* save %esi */
	
	movl MEMCPY_SIZE(%esp), %ecx
	shrl $2, %ecx			/* size / 4 */
	
	movl MEMCPY_DST(%esp), %edi
	movl MEMCPY_SRC(%esp), %esi
	
	rep movsl			/* copy whole words */
 
	movl MEMCPY_SIZE(%esp), %ecx
	andl $3, %ecx			/* size % 4 */
	jz 0f
	
	rep movsb			/* copy the rest byte by byte */
 
0:
	movl %edx, %edi
	movl %eax, %esi
	movl MEMCPY_SRC(%esp), %eax	/* MEMCPY_SRC(%esp), success */
	ret
	
/*
 * We got here from as_page_fault() after the memory operations
 * above had caused a page fault.
 */
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
	movl %edx, %edi
	movl %eax, %esi
	xorl %eax, %eax			/* return 0, failure */
	ret
 
## Turn paging on
#
# Enable paging and write-back caching in CR0.
#
paging_on:
	movl %cr0, %edx
	orl $(1 << 31), %edx		# paging on
	# clear Cache Disable and not Write Though
	andl $~((1 << 30) | (1 << 29)), %edx
	movl %edx,%cr0
	jmp 0f
0:
	ret
 
 
## Enable local APIC
#
# Enable local APIC in MSR.
#
enable_l_apic_in_msr:
	movl $0x1b, %ecx
	rdmsr
	orl $(1 << 11), %eax
	orl $(0xfee00000), %eax
	wrmsr
	ret
 
# Clear nested flag
# overwrites %ecx
.macro CLEAR_NT_FLAG
	pushfl
	pop %ecx
	and $0xffffbfff, %ecx
	push %ecx
	popfl
.endm	
 
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call exc_dispatch().
#
#define INTERRUPT_ALIGN 64
.macro handler i n
 
.ifeq \i - 0x30     # Syscall handler
	pushl %ds
	pushl %es
	pushl %fs
	pushl %gs
 
	#
	# Push syscall arguments onto the stack
	#
	# NOTE: The idea behind the order of arguments passed in registers is to
	#	use all scratch registers first and preserved registers next.
	#	An optimized libc syscall wrapper can make use of this setup.
	#
	pushl %eax
	pushl %ebp
	pushl %edi
	pushl %esi
	pushl %ebx
	pushl %ecx
	pushl %edx
	
	# we must fill the data segment registers
	movw $16, %ax
	movw %ax, %ds
	movw %ax, %es
	
	cld
	sti
	# syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax)
	call syscall_handler   
	cli
	addl $28, %esp         # clean-up of parameters
	
	popl %gs
	popl %fs
	popl %es
	popl %ds
	
	CLEAR_NT_FLAG
	iret
.else	
	/*
	 * This macro distinguishes between two versions of ia32 exceptions.
	 * One version has error word and the other does not have it.
	 * The latter version fakes the error word on the stack so that the
	 * handlers and istate_t can be the same for both types.
	 */
	.iflt \i - 32
		.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
			/* 
			 * With error word, do nothing
			 */
                .else
                        /*
                         * Version without error word,
                         */
			subl $4, %esp
                .endif
        .else
                /*
                 * Version without error word,
                 */
		subl $4, %esp
	.endif
	
	pushl %ds
	pushl %es
	pushl %fs
	pushl %gs
 
#ifdef CONFIG_DEBUG_ALLREGS
	pushl %ebx
	pushl %ebp
	pushl %edi
	pushl %esi
#else
	subl $16, %esp
#endif
	pushl %edx
	pushl %ecx
	pushl %eax
	
	# we must fill the data segment registers
	movw $16, %ax
	movw %ax, %ds
	movw %ax, %es
 
	cld
 
	pushl %esp          # *istate
	pushl $(\i)         # intnum
	call exc_dispatch   # excdispatch(intnum, *istate)
	addl $8, %esp       # Clear arguments from stack
 
	CLEAR_NT_FLAG # Modifies %ecx
	
	popl %eax
	popl %ecx
	popl %edx
#ifdef CONFIG_DEBUG_ALLREGS
	popl %esi
	popl %edi
	popl %ebp
	popl %ebx
#else
	addl $16, %esp
#endif	
	
	popl %gs
	popl %fs
	popl %es
	popl %ds
 
	addl $4, %esp	# Skip error word, no matter whether real or fake.
	iret
.endif
 
	.align INTERRUPT_ALIGN
	.if (\n- \i) - 1
	handler "(\i + 1)", \n
	.endif
.endm
 
# keep in sync with pm.h !!!
IDT_ITEMS = 64
.align INTERRUPT_ALIGN
interrupt_handlers:
h_start:
	handler 0 IDT_ITEMS
h_end:
 
.data
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS
 

Rev 2927	Rev 3107
1	#	1	#
2	# Copyright (c) 2001-2004 Jakub Jermar	2	# Copyright (c) 2001-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	## very low and hardware-level functions	29	## very low and hardware-level functions
30		30
31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error	31	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error
32	# word and 1 means interrupt with error word	32	# word and 1 means interrupt with error word
33	#define ERROR_WORD_INTERRUPT_LIST 0x00027d00	33	#define ERROR_WORD_INTERRUPT_LIST 0x00027d00
34		34
35	.text	35	.text
36		36
37	.global paging_on	37	.global paging_on
38	.global enable_l_apic_in_msr	38	.global enable_l_apic_in_msr
39	.global interrupt_handlers	39	.global interrupt_handlers
-		40	.global memsetb
-		41	.global memsetw
40	.global memcpy	42	.global memcpy
41	.global memcpy_from_uspace	43	.global memcpy_from_uspace
42	.global memcpy_from_uspace_failover_address	44	.global memcpy_from_uspace_failover_address
43	.global memcpy_to_uspace	45	.global memcpy_to_uspace
44	.global memcpy_to_uspace_failover_address	46	.global memcpy_to_uspace_failover_address
45		47
-		48
-		49	# Wrapper for generic memsetb
-		50	memsetb:
-		51	jmp _memsetb
-		52
-		53	# Wrapper for generic memsetw
-		54	memsetw:
-		55	jmp _memsetw
-		56
46		57
47	#define MEMCPY_DST 4	58	#define MEMCPY_DST 4
48	#define MEMCPY_SRC 8	59	#define MEMCPY_SRC 8
49	#define MEMCPY_SIZE 12	60	#define MEMCPY_SIZE 12
50		61
51	/** Copy memory to/from userspace.	62	/** Copy memory to/from userspace.
52	*	63	*
53	* This is almost conventional memcpy().	64	* This is almost conventional memcpy().
54	* The difference is that there is a failover part	65	* The difference is that there is a failover part
55	* to where control is returned from a page fault	66	* to where control is returned from a page fault
56	* if the page fault occurs during copy_from_uspace()	67	* if the page fault occurs during copy_from_uspace()
57	* or copy_to_uspace().	68	* or copy_to_uspace().
58	*	69	*
59	* @param MEMCPY_DST(%esp) Destination address.	70	* @param MEMCPY_DST(%esp) Destination address.
60	* @param MEMCPY_SRC(%esp) Source address.	71	* @param MEMCPY_SRC(%esp) Source address.
61	* @param MEMCPY_SIZE(%esp) Size.	72	* @param MEMCPY_SIZE(%esp) Size.
62	*	73	*
63	* @return MEMCPY_SRC(%esp) on success and 0 on failure.	74	* @return MEMCPY_SRC(%esp) on success and 0 on failure.
64	*/	75	*/
65	memcpy:	76	memcpy:
66	memcpy_from_uspace:	77	memcpy_from_uspace:
67	memcpy_to_uspace:	78	memcpy_to_uspace:
68	movl %edi, %edx /* save %edi */	79	movl %edi, %edx /* save %edi */
69	movl %esi, %eax /* save %esi */	80	movl %esi, %eax /* save %esi */
70		81
71	movl MEMCPY_SIZE(%esp), %ecx	82	movl MEMCPY_SIZE(%esp), %ecx
72	shrl $2, %ecx /* size / 4 */	83	shrl $2, %ecx /* size / 4 */
73		84
74	movl MEMCPY_DST(%esp), %edi	85	movl MEMCPY_DST(%esp), %edi
75	movl MEMCPY_SRC(%esp), %esi	86	movl MEMCPY_SRC(%esp), %esi
76		87
77	rep movsl /* copy whole words */	88	rep movsl /* copy whole words */
78		89
79	movl MEMCPY_SIZE(%esp), %ecx	90	movl MEMCPY_SIZE(%esp), %ecx
80	andl $3, %ecx /* size % 4 */	91	andl $3, %ecx /* size % 4 */
81	jz 0f	92	jz 0f
82		93
83	rep movsb /* copy the rest byte by byte */	94	rep movsb /* copy the rest byte by byte */
84		95
85	0:	96	0:
86	movl %edx, %edi	97	movl %edx, %edi
87	movl %eax, %esi	98	movl %eax, %esi
88	movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */	99	movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */
89	ret	100	ret
90		101
91	/*	102	/*
92	* We got here from as_page_fault() after the memory operations	103	* We got here from as_page_fault() after the memory operations
93	* above had caused a page fault.	104	* above had caused a page fault.
94	*/	105	*/
95	memcpy_from_uspace_failover_address:	106	memcpy_from_uspace_failover_address:
96	memcpy_to_uspace_failover_address:	107	memcpy_to_uspace_failover_address:
97	movl %edx, %edi	108	movl %edx, %edi
98	movl %eax, %esi	109	movl %eax, %esi
99	xorl %eax, %eax /* return 0, failure */	110	xorl %eax, %eax /* return 0, failure */
100	ret	111	ret
101		112
102	## Turn paging on	113	## Turn paging on
103	#	114	#
104	# Enable paging and write-back caching in CR0.	115	# Enable paging and write-back caching in CR0.
105	#	116	#
106	paging_on:	117	paging_on:
107	movl %cr0, %edx	118	movl %cr0, %edx
108	orl $(1 << 31), %edx # paging on	119	orl $(1 << 31), %edx # paging on
109	# clear Cache Disable and not Write Though	120	# clear Cache Disable and not Write Though
110	andl $~((1 << 30) \| (1 << 29)), %edx	121	andl $~((1 << 30) \| (1 << 29)), %edx
111	movl %edx,%cr0	122	movl %edx,%cr0
112	jmp 0f	123	jmp 0f
113	0:	124	0:
114	ret	125	ret
115		126
116		127
117	## Enable local APIC	128	## Enable local APIC
118	#	129	#
119	# Enable local APIC in MSR.	130	# Enable local APIC in MSR.
120	#	131	#
121	enable_l_apic_in_msr:	132	enable_l_apic_in_msr:
122	movl $0x1b, %ecx	133	movl $0x1b, %ecx
123	rdmsr	134	rdmsr
124	orl $(1 << 11), %eax	135	orl $(1 << 11), %eax
125	orl $(0xfee00000), %eax	136	orl $(0xfee00000), %eax
126	wrmsr	137	wrmsr
127	ret	138	ret
128		139
129	# Clear nested flag	140	# Clear nested flag
130	# overwrites %ecx	141	# overwrites %ecx
131	.macro CLEAR_NT_FLAG	142	.macro CLEAR_NT_FLAG
132	pushfl	143	pushfl
133	pop %ecx	144	pop %ecx
134	and $0xffffbfff, %ecx	145	and $0xffffbfff, %ecx
135	push %ecx	146	push %ecx
136	popfl	147	popfl
137	.endm	148	.endm
138		149
139	## Declare interrupt handlers	150	## Declare interrupt handlers
140	#	151	#
141	# Declare interrupt handlers for n interrupt	152	# Declare interrupt handlers for n interrupt
142	# vectors starting at vector i.	153	# vectors starting at vector i.
143	#	154	#
144	# The handlers setup data segment registers	155	# The handlers setup data segment registers
145	# and call exc_dispatch().	156	# and call exc_dispatch().
146	#	157	#
147	#define INTERRUPT_ALIGN 64	158	#define INTERRUPT_ALIGN 64
148	.macro handler i n	159	.macro handler i n
149		160
150	.ifeq \i - 0x30 # Syscall handler	161	.ifeq \i - 0x30 # Syscall handler
151	pushl %ds	162	pushl %ds
152	pushl %es	163	pushl %es
153	pushl %fs	164	pushl %fs
154	pushl %gs	165	pushl %gs
155		166
156	#	167	#
157	# Push syscall arguments onto the stack	168	# Push syscall arguments onto the stack
158	#	169	#
159	# NOTE: The idea behind the order of arguments passed in registers is to	170	# NOTE: The idea behind the order of arguments passed in registers is to
160	# use all scratch registers first and preserved registers next.	171	# use all scratch registers first and preserved registers next.
161	# An optimized libc syscall wrapper can make use of this setup.	172	# An optimized libc syscall wrapper can make use of this setup.
162	#	173	#
163	pushl %eax	174	pushl %eax
164	pushl %ebp	175	pushl %ebp
165	pushl %edi	176	pushl %edi
166	pushl %esi	177	pushl %esi
167	pushl %ebx	178	pushl %ebx
168	pushl %ecx	179	pushl %ecx
169	pushl %edx	180	pushl %edx
170		181
171	# we must fill the data segment registers	182	# we must fill the data segment registers
172	movw $16, %ax	183	movw $16, %ax
173	movw %ax, %ds	184	movw %ax, %ds
174	movw %ax, %es	185	movw %ax, %es
175		186
176	cld	187	cld
177	sti	188	sti
178	# syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax)	189	# syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax)
179	call syscall_handler	190	call syscall_handler
180	cli	191	cli
181	addl $28, %esp # clean-up of parameters	192	addl $28, %esp # clean-up of parameters
182		193
183	popl %gs	194	popl %gs
184	popl %fs	195	popl %fs
185	popl %es	196	popl %es
186	popl %ds	197	popl %ds
187		198
188	CLEAR_NT_FLAG	199	CLEAR_NT_FLAG
189	iret	200	iret
190	.else	201	.else
191	/*	202	/*
192	* This macro distinguishes between two versions of ia32 exceptions.	203	* This macro distinguishes between two versions of ia32 exceptions.
193	* One version has error word and the other does not have it.	204	* One version has error word and the other does not have it.
194	* The latter version fakes the error word on the stack so that the	205	* The latter version fakes the error word on the stack so that the
195	* handlers and istate_t can be the same for both types.	206	* handlers and istate_t can be the same for both types.
196	*/	207	*/
197	.iflt \i - 32	208	.iflt \i - 32
198	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST	209	.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
199	/*	210	/*
200	* With error word, do nothing	211	* With error word, do nothing
201	*/	212	*/
202	.else	213	.else
203	/*	214	/*
204	* Version without error word,	215	* Version without error word,
205	*/	216	*/
206	subl $4, %esp	217	subl $4, %esp
207	.endif	218	.endif
208	.else	219	.else
209	/*	220	/*
210	* Version without error word,	221	* Version without error word,
211	*/	222	*/
212	subl $4, %esp	223	subl $4, %esp
213	.endif	224	.endif
214		225
215	pushl %ds	226	pushl %ds
216	pushl %es	227	pushl %es
217	pushl %fs	228	pushl %fs
218	pushl %gs	229	pushl %gs
219		230
220	#ifdef CONFIG_DEBUG_ALLREGS	231	#ifdef CONFIG_DEBUG_ALLREGS
221	pushl %ebx	232	pushl %ebx
222	pushl %ebp	233	pushl %ebp
223	pushl %edi	234	pushl %edi
224	pushl %esi	235	pushl %esi
225	#else	236	#else
226	subl $16, %esp	237	subl $16, %esp
227	#endif	238	#endif
228	pushl %edx	239	pushl %edx
229	pushl %ecx	240	pushl %ecx
230	pushl %eax	241	pushl %eax
231		242
232	# we must fill the data segment registers	243	# we must fill the data segment registers
233	movw $16, %ax	244	movw $16, %ax
234	movw %ax, %ds	245	movw %ax, %ds
235	movw %ax, %es	246	movw %ax, %es
236		247
237	cld	248	cld
238		249
239	pushl %esp # *istate	250	pushl %esp # *istate
240	pushl $(\i) # intnum	251	pushl $(\i) # intnum
241	call exc_dispatch # excdispatch(intnum, *istate)	252	call exc_dispatch # excdispatch(intnum, *istate)
242	addl $8, %esp # Clear arguments from stack	253	addl $8, %esp # Clear arguments from stack
243		254
244	CLEAR_NT_FLAG # Modifies %ecx	255	CLEAR_NT_FLAG # Modifies %ecx
245		256
246	popl %eax	257	popl %eax
247	popl %ecx	258	popl %ecx
248	popl %edx	259	popl %edx
249	#ifdef CONFIG_DEBUG_ALLREGS	260	#ifdef CONFIG_DEBUG_ALLREGS
250	popl %esi	261	popl %esi
251	popl %edi	262	popl %edi
252	popl %ebp	263	popl %ebp
253	popl %ebx	264	popl %ebx
254	#else	265	#else
255	addl $16, %esp	266	addl $16, %esp
256	#endif	267	#endif
257		268
258	popl %gs	269	popl %gs
259	popl %fs	270	popl %fs
260	popl %es	271	popl %es
261	popl %ds	272	popl %ds
262		273
263	addl $4, %esp # Skip error word, no matter whether real or fake.	274	addl $4, %esp # Skip error word, no matter whether real or fake.
264	iret	275	iret
265	.endif	276	.endif
266		277
267	.align INTERRUPT_ALIGN	278	.align INTERRUPT_ALIGN
268	.if (\n- \i) - 1	279	.if (\n- \i) - 1
269	handler "(\i + 1)", \n	280	handler "(\i + 1)", \n
270	.endif	281	.endif
271	.endm	282	.endm
272		283
273	# keep in sync with pm.h !!!	284	# keep in sync with pm.h !!!
274	IDT_ITEMS = 64	285	IDT_ITEMS = 64
275	.align INTERRUPT_ALIGN	286	.align INTERRUPT_ALIGN
276	interrupt_handlers:	287	interrupt_handlers:
277	h_start:	288	h_start:
278	handler 0 IDT_ITEMS	289	handler 0 IDT_ITEMS
279	h_end:	290	h_end:
280		291
281	.data	292	.data
282	.global interrupt_handler_size	293	.global interrupt_handler_size
283		294
284	interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS	295	interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS
285		296

Subversion Repositories HelenOS

(root)/branches/dynload/kernel/arch/ia32/src/asm.S – Rev 2927 → 3107